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Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wue09b5362014-08-07 09:25:14 +080026 */
27
28#ifndef QUEUE_H
29#define QUEUE_H
30
Chia-I Wuc5438c22014-08-19 14:03:06 +080031#include "kmd/winsys.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080032#include "intel.h"
Chia-I Wucdcff732014-08-19 14:44:15 +080033#include "gpu.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080034#include "obj.h"
35
Chia-I Wuec841722014-08-25 22:36:01 +080036#define INTEL_QUEUE_ATOMIC_COUNTER_COUNT 1024
37
Chia-I Wu34f45182014-08-19 14:02:59 +080038struct intel_cmd;
Chia-I Wue09b5362014-08-07 09:25:14 +080039struct intel_dev;
40
41struct intel_queue {
42 struct intel_base base;
43
44 struct intel_dev *dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +080045 enum intel_ring_type ring;
Chia-I Wu34f45182014-08-19 14:02:59 +080046
Chia-I Wu63883292014-08-25 13:50:26 +080047 struct intel_bo *atomic_bo;
48 struct intel_bo *select_graphics_bo;
49 struct intel_bo *select_compute_bo;
Chia-I Wu3ad3c542014-08-25 11:09:17 +080050
Chia-I Wu34f45182014-08-19 14:02:59 +080051 struct intel_cmd *last_submitted_cmd;
Chia-I Wu63883292014-08-25 13:50:26 +080052 int last_pipeline_select;
Chia-I Wue09b5362014-08-07 09:25:14 +080053};
54
55static inline struct intel_queue *intel_queue(XGL_QUEUE queue)
56{
57 return (struct intel_queue *) queue;
58}
59
Chia-I Wu9ae59c12014-08-07 10:08:49 +080060XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +080061 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +080062 struct intel_queue **queue_ret);
Chia-I Wue09b5362014-08-07 09:25:14 +080063void intel_queue_destroy(struct intel_queue *queue);
64
65XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout);
66
67XGL_RESULT XGLAPI intelQueueSetGlobalMemReferences(
68 XGL_QUEUE queue,
69 XGL_UINT memRefCount,
70 const XGL_MEMORY_REF* pMemRefs);
71
72XGL_RESULT XGLAPI intelQueueWaitIdle(
73 XGL_QUEUE queue);
74
Chia-I Wu251e7d92014-08-19 13:35:42 +080075XGL_RESULT XGLAPI intelQueueSubmit(
76 XGL_QUEUE queue,
77 XGL_UINT cmdBufferCount,
78 const XGL_CMD_BUFFER* pCmdBuffers,
79 XGL_UINT memRefCount,
80 const XGL_MEMORY_REF* pMemRefs,
81 XGL_FENCE fence);
82
83XGL_RESULT XGLAPI intelOpenSharedQueueSemaphore(
84 XGL_DEVICE device,
85 const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo,
86 XGL_QUEUE_SEMAPHORE* pSemaphore);
87
88XGL_RESULT XGLAPI intelCreateQueueSemaphore(
89 XGL_DEVICE device,
90 const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo,
91 XGL_QUEUE_SEMAPHORE* pSemaphore);
92
93XGL_RESULT XGLAPI intelSignalQueueSemaphore(
94 XGL_QUEUE queue,
95 XGL_QUEUE_SEMAPHORE semaphore);
96
97XGL_RESULT XGLAPI intelWaitQueueSemaphore(
98 XGL_QUEUE queue,
99 XGL_QUEUE_SEMAPHORE semaphore);
100
Chia-I Wue09b5362014-08-07 09:25:14 +0800101#endif /* QUEUE_H */