Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
| 28 | #ifndef CMD_PRIV_H |
| 29 | #define CMD_PRIV_H |
| 30 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 31 | #include "genhw/genhw.h" |
Chia-I Wu | 32710d7 | 2014-08-20 16:05:22 +0800 | [diff] [blame] | 32 | #include "dev.h" |
| 33 | #include "gpu.h" |
Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 34 | #include "cmd.h" |
| 35 | |
Chia-I Wu | 32710d7 | 2014-08-20 16:05:22 +0800 | [diff] [blame] | 36 | #define CMD_ASSERT(cmd, min_gen, max_gen) \ |
| 37 | INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen)) |
| 38 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 39 | enum intel_cmd_item_type { |
| 40 | /* for state buffer */ |
| 41 | INTEL_CMD_ITEM_BLOB, |
| 42 | INTEL_CMD_ITEM_CLIP_VIEWPORT, |
| 43 | INTEL_CMD_ITEM_SF_VIEWPORT, |
| 44 | INTEL_CMD_ITEM_SCISSOR_RECT, |
| 45 | INTEL_CMD_ITEM_CC_VIEWPORT, |
| 46 | INTEL_CMD_ITEM_COLOR_CALC, |
| 47 | INTEL_CMD_ITEM_DEPTH_STENCIL, |
| 48 | INTEL_CMD_ITEM_BLEND, |
| 49 | INTEL_CMD_ITEM_SAMPLER, |
| 50 | |
| 51 | /* for surface buffer */ |
| 52 | INTEL_CMD_ITEM_SURFACE, |
| 53 | INTEL_CMD_ITEM_BINDING_TABLE, |
| 54 | |
| 55 | /* for instruction buffer */ |
| 56 | INTEL_CMD_ITEM_KERNEL, |
| 57 | |
| 58 | INTEL_CMD_ITEM_COUNT, |
| 59 | }; |
| 60 | |
| 61 | struct intel_cmd_item { |
| 62 | enum intel_cmd_item_type type; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 63 | size_t offset; |
| 64 | size_t size; |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 65 | }; |
| 66 | |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 67 | #define INTEL_CMD_RELOC_TARGET_IS_WRITER (1u << 31) |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 68 | struct intel_cmd_reloc { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 69 | enum intel_cmd_writer_type which; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 70 | size_t offset; |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 71 | |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 72 | intptr_t target; |
| 73 | uint32_t target_offset; |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 74 | |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 75 | uint32_t flags; |
Chia-I Wu | 958d1b7 | 2014-08-21 11:28:11 +0800 | [diff] [blame] | 76 | }; |
| 77 | |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 78 | struct intel_ds_view; |
| 79 | |
Chia-I Wu | 29e6f50 | 2014-11-24 14:27:29 +0800 | [diff] [blame] | 80 | enum intel_cmd_meta_mode { |
| 81 | /* |
Chia-I Wu | 4d344e6 | 2014-12-20 21:06:04 +0800 | [diff] [blame] | 82 | * Draw POINTLIST of (width * height) vertices with only VS enabled. The |
| 83 | * vertex id is from 0 to (width * height - 1). |
Chia-I Wu | 29e6f50 | 2014-11-24 14:27:29 +0800 | [diff] [blame] | 84 | */ |
| 85 | INTEL_CMD_META_VS_POINTS, |
| 86 | |
| 87 | /* |
| 88 | * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height) |
| 89 | * with only FS enabled. |
| 90 | */ |
| 91 | INTEL_CMD_META_FS_RECT, |
| 92 | |
| 93 | /* |
| 94 | * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height) |
| 95 | * with only depth/stencil enabled. |
| 96 | */ |
| 97 | INTEL_CMD_META_DEPTH_STENCIL_RECT, |
| 98 | }; |
| 99 | |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 100 | struct intel_cmd_meta { |
Chia-I Wu | 29e6f50 | 2014-11-24 14:27:29 +0800 | [diff] [blame] | 101 | enum intel_cmd_meta_mode mode; |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 102 | enum intel_dev_meta_shader shader_id; |
| 103 | |
| 104 | struct { |
| 105 | bool valid; |
| 106 | |
| 107 | uint32_t surface[8]; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 108 | uint32_t surface_len; |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 109 | |
| 110 | intptr_t reloc_target; |
| 111 | uint32_t reloc_offset; |
| 112 | uint32_t reloc_flags; |
| 113 | |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 114 | uint32_t lod, layer; |
| 115 | uint32_t x, y; |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 116 | } src, dst; |
| 117 | |
Chia-I Wu | 429a0aa | 2014-10-24 11:57:51 +0800 | [diff] [blame] | 118 | struct { |
| 119 | struct intel_ds_view *view; |
Tony Barbour | fa6cac7 | 2015-01-16 14:27:35 -0700 | [diff] [blame] | 120 | uint32_t stencil_ref; |
| 121 | XGL_IMAGE_ASPECT aspect; |
Chia-I Wu | 429a0aa | 2014-10-24 11:57:51 +0800 | [diff] [blame] | 122 | } ds; |
| 123 | |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 124 | uint32_t clear_val[4]; |
| 125 | |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 126 | uint32_t width, height; |
| 127 | uint32_t samples; |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 128 | }; |
| 129 | |
Chia-I Wu | 9f03986 | 2014-08-20 15:39:56 +0800 | [diff] [blame] | 130 | static inline int cmd_gen(const struct intel_cmd *cmd) |
| 131 | { |
| 132 | return intel_gpu_gen(cmd->dev->gpu); |
| 133 | } |
| 134 | |
Chia-I Wu | 4e5577a | 2015-02-10 11:04:44 -0700 | [diff] [blame] | 135 | static inline void cmd_fail(struct intel_cmd *cmd, XGL_RESULT result) |
| 136 | { |
| 137 | intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR, |
| 138 | XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0, |
| 139 | "command building error"); |
| 140 | |
| 141 | cmd->result = result; |
| 142 | } |
| 143 | |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 144 | static inline void cmd_reserve_reloc(struct intel_cmd *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 145 | uint32_t reloc_len) |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 146 | { |
| 147 | /* fail silently */ |
| 148 | if (cmd->reloc_used + reloc_len > cmd->reloc_count) { |
| 149 | cmd->reloc_used = 0; |
Chia-I Wu | 4e5577a | 2015-02-10 11:04:44 -0700 | [diff] [blame] | 150 | cmd_fail(cmd, XGL_ERROR_TOO_MANY_MEMORY_REFERENCES); |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 151 | } |
| 152 | assert(cmd->reloc_used + reloc_len <= cmd->reloc_count); |
| 153 | } |
| 154 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 155 | void cmd_writer_grow(struct intel_cmd *cmd, |
Chia-I Wu | 3c3edc0 | 2014-09-09 10:32:59 +0800 | [diff] [blame] | 156 | enum intel_cmd_writer_type which, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 157 | size_t new_size); |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 158 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 159 | void cmd_writer_record(struct intel_cmd *cmd, |
| 160 | enum intel_cmd_writer_type which, |
| 161 | enum intel_cmd_item_type type, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 162 | size_t offset, size_t size); |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 163 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 164 | /** |
| 165 | * Return an offset to a region that is aligned to \p alignment and has at |
| 166 | * least \p size bytes. |
| 167 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 168 | static inline size_t cmd_writer_reserve(struct intel_cmd *cmd, |
| 169 | enum intel_cmd_writer_type which, |
| 170 | size_t alignment, size_t size) |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 171 | { |
| 172 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 173 | size_t offset; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 174 | |
| 175 | assert(alignment && u_is_pow2(alignment)); |
| 176 | offset = u_align(writer->used, alignment); |
| 177 | |
| 178 | if (offset + size > writer->size) { |
| 179 | cmd_writer_grow(cmd, which, offset + size); |
| 180 | /* align again in case of errors */ |
| 181 | offset = u_align(writer->used, alignment); |
| 182 | |
| 183 | assert(offset + size <= writer->size); |
| 184 | } |
| 185 | |
| 186 | return offset; |
| 187 | } |
Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 188 | |
Chia-I Wu | 32710d7 | 2014-08-20 16:05:22 +0800 | [diff] [blame] | 189 | /** |
Chia-I Wu | bda55fd | 2014-08-25 12:46:10 +0800 | [diff] [blame] | 190 | * Add a reloc at \p pos. No error checking. |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 191 | */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 192 | static inline void cmd_writer_reloc(struct intel_cmd *cmd, |
| 193 | enum intel_cmd_writer_type which, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 194 | size_t offset, intptr_t target, |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 195 | uint32_t target_offset, uint32_t flags) |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 196 | { |
| 197 | struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used]; |
| 198 | |
| 199 | assert(cmd->reloc_used < cmd->reloc_count); |
| 200 | |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 201 | reloc->which = which; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 202 | reloc->offset = offset; |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 203 | reloc->target = target; |
| 204 | reloc->target_offset = target_offset; |
Chia-I Wu | 32a2246 | 2014-08-26 14:13:46 +0800 | [diff] [blame] | 205 | reloc->flags = flags; |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 206 | |
| 207 | cmd->reloc_used++; |
| 208 | } |
| 209 | |
| 210 | /** |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 211 | * Reserve a region from the state buffer. The offset, in bytes, to the |
| 212 | * reserved region is returned. |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 213 | * |
| 214 | * Note that \p alignment is in bytes and \p len is in DWords. |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 215 | */ |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 216 | static inline uint32_t cmd_state_reserve(struct intel_cmd *cmd, |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 217 | enum intel_cmd_item_type item, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 218 | size_t alignment, uint32_t len) |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 219 | { |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 220 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE; |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 221 | const size_t size = len << 2; |
| 222 | const size_t offset = cmd_writer_reserve(cmd, which, alignment, size); |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 223 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 224 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 225 | /* all states are at least aligned to 32-bytes */ |
| 226 | assert(alignment % 32 == 0); |
| 227 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 228 | writer->used = offset + size; |
| 229 | |
Chia-I Wu | 465fe21 | 2015-02-11 11:27:06 -0700 | [diff] [blame^] | 230 | if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG)) |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 231 | cmd_writer_record(cmd, which, item, offset, size); |
| 232 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 233 | return offset; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /** |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 237 | * Get the pointer to a reserved region for updating. The pointer is only |
| 238 | * valid until the next reserve call. |
| 239 | */ |
| 240 | static inline void cmd_state_update(struct intel_cmd *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 241 | uint32_t offset, uint32_t len, |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 242 | uint32_t **dw) |
| 243 | { |
| 244 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE; |
| 245 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 246 | |
| 247 | assert(offset + (len << 2) <= writer->used); |
| 248 | |
| 249 | *dw = (uint32_t *) ((char *) writer->ptr + offset); |
| 250 | } |
| 251 | |
| 252 | /** |
| 253 | * Reserve a region from the state buffer. Both the offset, in bytes, and the |
| 254 | * pointer to the reserved region are returned. The pointer is only valid |
| 255 | * until the next reserve call. |
| 256 | * |
| 257 | * Note that \p alignment is in bytes and \p len is in DWords. |
| 258 | */ |
| 259 | static inline uint32_t cmd_state_pointer(struct intel_cmd *cmd, |
| 260 | enum intel_cmd_item_type item, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 261 | size_t alignment, uint32_t len, |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 262 | uint32_t **dw) |
| 263 | { |
| 264 | const uint32_t offset = cmd_state_reserve(cmd, item, alignment, len); |
| 265 | |
| 266 | cmd_state_update(cmd, offset, len, dw); |
| 267 | |
| 268 | return offset; |
| 269 | } |
| 270 | |
| 271 | /** |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 272 | * Write a dynamic state to the state buffer. |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 273 | */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 274 | static inline uint32_t cmd_state_write(struct intel_cmd *cmd, |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 275 | enum intel_cmd_item_type item, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 276 | size_t alignment, uint32_t len, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 277 | const uint32_t *dw) |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 278 | { |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 279 | uint32_t offset, *dst; |
| 280 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 281 | offset = cmd_state_pointer(cmd, item, alignment, len, &dst); |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 282 | memcpy(dst, dw, len << 2); |
| 283 | |
| 284 | return offset; |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | /** |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 288 | * Write a surface state to the surface buffer. The offset, in bytes, of the |
| 289 | * state is returned. |
| 290 | * |
| 291 | * Note that \p alignment is in bytes and \p len is in DWords. |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 292 | */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 293 | static inline uint32_t cmd_surface_write(struct intel_cmd *cmd, |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 294 | enum intel_cmd_item_type item, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 295 | size_t alignment, uint32_t len, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 296 | const uint32_t *dw) |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 297 | { |
Chia-I Wu | 15cccf7 | 2015-02-10 04:07:40 +0800 | [diff] [blame] | 298 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE; |
Chia-I Wu | f98dd88 | 2015-02-10 04:17:47 +0800 | [diff] [blame] | 299 | const size_t size = len << 2; |
Chia-I Wu | 15cccf7 | 2015-02-10 04:07:40 +0800 | [diff] [blame] | 300 | const uint32_t offset = cmd_writer_reserve(cmd, which, alignment, size); |
| 301 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 302 | uint32_t *dst; |
| 303 | |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 304 | assert(item == INTEL_CMD_ITEM_SURFACE || |
| 305 | item == INTEL_CMD_ITEM_BINDING_TABLE); |
| 306 | |
Chia-I Wu | 15cccf7 | 2015-02-10 04:07:40 +0800 | [diff] [blame] | 307 | /* all states are at least aligned to 32-bytes */ |
| 308 | assert(alignment % 32 == 0); |
| 309 | |
| 310 | writer->used = offset + size; |
| 311 | |
| 312 | if (intel_debug & INTEL_DEBUG_BATCH) |
| 313 | cmd_writer_record(cmd, which, item, offset, size); |
| 314 | |
| 315 | dst = (uint32_t *) ((char *) writer->ptr + offset); |
| 316 | memcpy(dst, dw, size); |
| 317 | |
| 318 | return offset; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | /** |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 322 | * Add a relocation entry for a DWord of a surface state. |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 323 | */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 324 | static inline void cmd_surface_reloc(struct intel_cmd *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 325 | uint32_t offset, uint32_t dw_index, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 326 | struct intel_bo *bo, |
| 327 | uint32_t bo_offset, uint32_t reloc_flags) |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 328 | { |
Chia-I Wu | 15cccf7 | 2015-02-10 04:07:40 +0800 | [diff] [blame] | 329 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE; |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 330 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 331 | cmd_writer_reloc(cmd, which, offset + (dw_index << 2), |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 332 | (intptr_t) bo, bo_offset, reloc_flags); |
| 333 | } |
| 334 | |
| 335 | static inline void cmd_surface_reloc_writer(struct intel_cmd *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 336 | uint32_t offset, uint32_t dw_index, |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 337 | enum intel_cmd_writer_type writer, |
| 338 | uint32_t writer_offset) |
| 339 | { |
Chia-I Wu | 15cccf7 | 2015-02-10 04:07:40 +0800 | [diff] [blame] | 340 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE; |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 341 | |
| 342 | cmd_writer_reloc(cmd, which, offset + (dw_index << 2), |
| 343 | (intptr_t) writer, writer_offset, |
| 344 | INTEL_CMD_RELOC_TARGET_IS_WRITER); |
Chia-I Wu | cdff059 | 2014-08-22 09:27:36 +0800 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | /** |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 348 | * Write a kernel to the instruction buffer. The offset, in bytes, of the |
| 349 | * kernel is returned. |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 350 | */ |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 351 | static inline uint32_t cmd_instruction_write(struct intel_cmd *cmd, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 352 | size_t size, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 353 | const void *kernel) |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 354 | { |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 355 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_INSTRUCTION; |
| 356 | /* |
| 357 | * From the Sandy Bridge PRM, volume 4 part 2, page 112: |
| 358 | * |
| 359 | * "Due to prefetch of the instruction stream, the EUs may attempt to |
| 360 | * access up to 8 instructions (128 bytes) beyond the end of the |
| 361 | * kernel program - possibly into the next memory page. Although |
| 362 | * these instructions will not be executed, software must account for |
| 363 | * the prefetch in order to avoid invalid page access faults." |
| 364 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 365 | const size_t reserved_size = size + 128; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 366 | /* kernels are aligned to 64 bytes */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 367 | const size_t alignment = 64; |
| 368 | const size_t offset = cmd_writer_reserve(cmd, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 369 | which, alignment, reserved_size); |
| 370 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 371 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 372 | memcpy((char *) writer->ptr + offset, kernel, size); |
Chia-I Wu | 5e25c27 | 2014-08-21 20:19:12 +0800 | [diff] [blame] | 373 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 374 | writer->used = offset + size; |
| 375 | |
Chia-I Wu | 465fe21 | 2015-02-11 11:27:06 -0700 | [diff] [blame^] | 376 | if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG)) |
Chia-I Wu | 00b51a8 | 2014-09-09 12:07:37 +0800 | [diff] [blame] | 377 | cmd_writer_record(cmd, which, INTEL_CMD_ITEM_KERNEL, offset, size); |
| 378 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 379 | return offset; |
| 380 | } |
| 381 | |
| 382 | /** |
| 383 | * Reserve a region from the batch buffer. Both the offset, in DWords, and |
Chia-I Wu | 5da476a | 2014-12-10 08:50:28 +0800 | [diff] [blame] | 384 | * the pointer to the reserved region are returned. The pointer is only valid |
| 385 | * until the next reserve call. |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 386 | * |
| 387 | * Note that \p len is in DWords. |
| 388 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 389 | static inline uint32_t cmd_batch_pointer(struct intel_cmd *cmd, |
| 390 | uint32_t len, uint32_t **dw) |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 391 | { |
| 392 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH; |
| 393 | /* |
| 394 | * We know the batch bo is always aligned. Using 1 here should allow the |
| 395 | * compiler to optimize away aligning. |
| 396 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 397 | const size_t alignment = 1; |
| 398 | const size_t size = len << 2; |
| 399 | const size_t offset = cmd_writer_reserve(cmd, which, alignment, size); |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 400 | struct intel_cmd_writer *writer = &cmd->writers[which]; |
| 401 | |
| 402 | assert(offset % 4 == 0); |
| 403 | *dw = (uint32_t *) ((char *) writer->ptr + offset); |
| 404 | |
| 405 | writer->used = offset + size; |
| 406 | |
| 407 | return offset >> 2; |
| 408 | } |
| 409 | |
| 410 | /** |
| 411 | * Write a command to the batch buffer. |
| 412 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 413 | static inline uint32_t cmd_batch_write(struct intel_cmd *cmd, |
| 414 | uint32_t len, const uint32_t *dw) |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 415 | { |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 416 | uint32_t pos; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 417 | uint32_t *dst; |
| 418 | |
| 419 | pos = cmd_batch_pointer(cmd, len, &dst); |
| 420 | memcpy(dst, dw, len << 2); |
| 421 | |
| 422 | return pos; |
| 423 | } |
| 424 | |
| 425 | /** |
| 426 | * Add a relocation entry for a DWord of a command. |
| 427 | */ |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 428 | static inline void cmd_batch_reloc(struct intel_cmd *cmd, uint32_t pos, |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 429 | struct intel_bo *bo, |
| 430 | uint32_t bo_offset, uint32_t reloc_flags) |
| 431 | { |
| 432 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH; |
| 433 | |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 434 | cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) bo, bo_offset, reloc_flags); |
| 435 | } |
| 436 | |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 437 | static inline void cmd_batch_reloc_writer(struct intel_cmd *cmd, uint32_t pos, |
Chia-I Wu | d7d1e48 | 2014-10-18 13:25:10 +0800 | [diff] [blame] | 438 | enum intel_cmd_writer_type writer, |
| 439 | uint32_t writer_offset) |
| 440 | { |
| 441 | const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH; |
| 442 | |
| 443 | cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) writer, writer_offset, |
| 444 | INTEL_CMD_RELOC_TARGET_IS_WRITER); |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 445 | } |
| 446 | |
Chia-I Wu | 66bdcd7 | 2015-02-10 04:11:31 +0800 | [diff] [blame] | 447 | void cmd_batch_state_base_address(struct intel_cmd *cmd); |
| 448 | |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 449 | /** |
Chia-I Wu | 48c283d | 2014-08-25 23:13:46 +0800 | [diff] [blame] | 450 | * Begin the batch buffer. |
Chia-I Wu | 79dfbb3 | 2014-08-25 12:19:02 +0800 | [diff] [blame] | 451 | */ |
| 452 | static inline void cmd_batch_begin(struct intel_cmd *cmd) |
| 453 | { |
Chia-I Wu | 66bdcd7 | 2015-02-10 04:11:31 +0800 | [diff] [blame] | 454 | cmd_batch_state_base_address(cmd); |
Chia-I Wu | 79dfbb3 | 2014-08-25 12:19:02 +0800 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | /** |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 458 | * End the batch buffer. |
| 459 | */ |
| 460 | static inline void cmd_batch_end(struct intel_cmd *cmd) |
| 461 | { |
Chia-I Wu | 68f319d | 2014-09-09 09:43:21 +0800 | [diff] [blame] | 462 | struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_BATCH]; |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 463 | uint32_t *dw; |
Chia-I Wu | 79dfbb3 | 2014-08-25 12:19:02 +0800 | [diff] [blame] | 464 | |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 465 | if (writer->used & 0x7) { |
| 466 | cmd_batch_pointer(cmd, 1, &dw); |
| 467 | dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END); |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 468 | } else { |
Chia-I Wu | 72292b7 | 2014-09-09 10:48:33 +0800 | [diff] [blame] | 469 | cmd_batch_pointer(cmd, 2, &dw); |
| 470 | dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END); |
| 471 | dw[1] = GEN6_MI_CMD(MI_NOOP); |
Chia-I Wu | e24c329 | 2014-08-21 14:05:23 +0800 | [diff] [blame] | 472 | } |
Chia-I Wu | 343b137 | 2014-08-20 16:39:20 +0800 | [diff] [blame] | 473 | } |
| 474 | |
Chia-I Wu | 525c660 | 2014-08-27 10:22:34 +0800 | [diff] [blame] | 475 | void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0); |
Chia-I Wu | 3fb47ce | 2014-10-28 11:19:36 +0800 | [diff] [blame] | 476 | void cmd_batch_flush_all(struct intel_cmd *cmd); |
Chia-I Wu | 525c660 | 2014-08-27 10:22:34 +0800 | [diff] [blame] | 477 | |
Chia-I Wu | 759fa2e | 2014-08-30 18:44:47 +0800 | [diff] [blame] | 478 | void cmd_batch_depth_count(struct intel_cmd *cmd, |
| 479 | struct intel_bo *bo, |
| 480 | XGL_GPU_SIZE offset); |
| 481 | |
Chia-I Wu | e8dbd5d | 2014-08-31 13:15:58 +0800 | [diff] [blame] | 482 | void cmd_batch_timestamp(struct intel_cmd *cmd, |
| 483 | struct intel_bo *bo, |
| 484 | XGL_GPU_SIZE offset); |
| 485 | |
| 486 | void cmd_batch_immediate(struct intel_cmd *cmd, |
Mike Stroyan | 55658c2 | 2014-12-04 11:08:39 +0000 | [diff] [blame] | 487 | uint32_t pipe_control_flags, |
Chia-I Wu | e8dbd5d | 2014-08-31 13:15:58 +0800 | [diff] [blame] | 488 | struct intel_bo *bo, |
| 489 | XGL_GPU_SIZE offset, |
| 490 | uint64_t val); |
Chia-I Wu | 1cbc005 | 2014-08-25 09:50:12 +0800 | [diff] [blame] | 491 | |
Chia-I Wu | c14d156 | 2014-10-17 09:49:22 +0800 | [diff] [blame] | 492 | void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta); |
| 493 | |
Chia-I Wu | 00a23b2 | 2014-08-20 15:28:08 +0800 | [diff] [blame] | 494 | #endif /* CMD_PRIV_H */ |