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Chia-I Wu00a23b22014-08-20 15:28:08 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu00a23b22014-08-20 15:28:08 +080026 */
27
28#ifndef CMD_PRIV_H
29#define CMD_PRIV_H
30
Chia-I Wue24c3292014-08-21 14:05:23 +080031#include "genhw/genhw.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080032#include "dev.h"
33#include "gpu.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd.h"
35
Chia-I Wu32710d72014-08-20 16:05:22 +080036#define CMD_ASSERT(cmd, min_gen, max_gen) \
37 INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
38
Chia-I Wu00b51a82014-09-09 12:07:37 +080039enum intel_cmd_item_type {
40 /* for state buffer */
41 INTEL_CMD_ITEM_BLOB,
42 INTEL_CMD_ITEM_CLIP_VIEWPORT,
43 INTEL_CMD_ITEM_SF_VIEWPORT,
44 INTEL_CMD_ITEM_SCISSOR_RECT,
45 INTEL_CMD_ITEM_CC_VIEWPORT,
46 INTEL_CMD_ITEM_COLOR_CALC,
47 INTEL_CMD_ITEM_DEPTH_STENCIL,
48 INTEL_CMD_ITEM_BLEND,
49 INTEL_CMD_ITEM_SAMPLER,
50
51 /* for surface buffer */
52 INTEL_CMD_ITEM_SURFACE,
53 INTEL_CMD_ITEM_BINDING_TABLE,
54
55 /* for instruction buffer */
56 INTEL_CMD_ITEM_KERNEL,
57
58 INTEL_CMD_ITEM_COUNT,
59};
60
61struct intel_cmd_item {
62 enum intel_cmd_item_type type;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060063 size_t offset;
64 size_t size;
Chia-I Wu00b51a82014-09-09 12:07:37 +080065};
66
Chia-I Wud7d1e482014-10-18 13:25:10 +080067#define INTEL_CMD_RELOC_TARGET_IS_WRITER (1u << 31)
Chia-I Wu958d1b72014-08-21 11:28:11 +080068struct intel_cmd_reloc {
Chia-I Wu68f319d2014-09-09 09:43:21 +080069 enum intel_cmd_writer_type which;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060070 size_t offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080071
Chia-I Wud7d1e482014-10-18 13:25:10 +080072 intptr_t target;
73 uint32_t target_offset;
Chia-I Wu958d1b72014-08-21 11:28:11 +080074
Chia-I Wu32a22462014-08-26 14:13:46 +080075 uint32_t flags;
Chia-I Wu958d1b72014-08-21 11:28:11 +080076};
77
Chia-I Wuc14d1562014-10-17 09:49:22 +080078struct intel_ds_view;
79
Chia-I Wu29e6f502014-11-24 14:27:29 +080080enum intel_cmd_meta_mode {
81 /*
Chia-I Wu4d344e62014-12-20 21:06:04 +080082 * Draw POINTLIST of (width * height) vertices with only VS enabled. The
83 * vertex id is from 0 to (width * height - 1).
Chia-I Wu29e6f502014-11-24 14:27:29 +080084 */
85 INTEL_CMD_META_VS_POINTS,
86
87 /*
88 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
89 * with only FS enabled.
90 */
91 INTEL_CMD_META_FS_RECT,
92
93 /*
94 * Draw a RECTLIST from (dst.x, dst.y) to (dst.x + width, dst.y + height)
95 * with only depth/stencil enabled.
96 */
97 INTEL_CMD_META_DEPTH_STENCIL_RECT,
98};
99
Chia-I Wuc14d1562014-10-17 09:49:22 +0800100struct intel_cmd_meta {
Chia-I Wu29e6f502014-11-24 14:27:29 +0800101 enum intel_cmd_meta_mode mode;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800102 enum intel_dev_meta_shader shader_id;
103
104 struct {
105 bool valid;
106
107 uint32_t surface[8];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600108 uint32_t surface_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800109
110 intptr_t reloc_target;
111 uint32_t reloc_offset;
112 uint32_t reloc_flags;
113
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600114 uint32_t lod, layer;
115 uint32_t x, y;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800116 } src, dst;
117
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800118 struct {
119 struct intel_ds_view *view;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700120 uint32_t stencil_ref;
121 XGL_IMAGE_ASPECT aspect;
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800122 } ds;
123
Chia-I Wuc14d1562014-10-17 09:49:22 +0800124 uint32_t clear_val[4];
125
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600126 uint32_t width, height;
127 uint32_t samples;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800128};
129
Chia-I Wu9f039862014-08-20 15:39:56 +0800130static inline int cmd_gen(const struct intel_cmd *cmd)
131{
132 return intel_gpu_gen(cmd->dev->gpu);
133}
134
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700135static inline void cmd_fail(struct intel_cmd *cmd, XGL_RESULT result)
136{
137 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
138 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
139 "command building error");
140
141 cmd->result = result;
142}
143
Chia-I Wucdff0592014-08-22 09:27:36 +0800144static inline void cmd_reserve_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600145 uint32_t reloc_len)
Chia-I Wucdff0592014-08-22 09:27:36 +0800146{
147 /* fail silently */
148 if (cmd->reloc_used + reloc_len > cmd->reloc_count) {
149 cmd->reloc_used = 0;
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700150 cmd_fail(cmd, XGL_ERROR_TOO_MANY_MEMORY_REFERENCES);
Chia-I Wucdff0592014-08-22 09:27:36 +0800151 }
152 assert(cmd->reloc_used + reloc_len <= cmd->reloc_count);
153}
154
Chia-I Wue24c3292014-08-21 14:05:23 +0800155void cmd_writer_grow(struct intel_cmd *cmd,
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800156 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600157 size_t new_size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800158
Chia-I Wu00b51a82014-09-09 12:07:37 +0800159void cmd_writer_record(struct intel_cmd *cmd,
160 enum intel_cmd_writer_type which,
161 enum intel_cmd_item_type type,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600162 size_t offset, size_t size);
Chia-I Wu00b51a82014-09-09 12:07:37 +0800163
Chia-I Wu72292b72014-09-09 10:48:33 +0800164/**
165 * Return an offset to a region that is aligned to \p alignment and has at
166 * least \p size bytes.
167 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600168static inline size_t cmd_writer_reserve(struct intel_cmd *cmd,
169 enum intel_cmd_writer_type which,
170 size_t alignment, size_t size)
Chia-I Wu72292b72014-09-09 10:48:33 +0800171{
172 struct intel_cmd_writer *writer = &cmd->writers[which];
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600173 size_t offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800174
175 assert(alignment && u_is_pow2(alignment));
176 offset = u_align(writer->used, alignment);
177
178 if (offset + size > writer->size) {
179 cmd_writer_grow(cmd, which, offset + size);
180 /* align again in case of errors */
181 offset = u_align(writer->used, alignment);
182
183 assert(offset + size <= writer->size);
184 }
185
186 return offset;
187}
Chia-I Wu00a23b22014-08-20 15:28:08 +0800188
Chia-I Wu32710d72014-08-20 16:05:22 +0800189/**
Chia-I Wubda55fd2014-08-25 12:46:10 +0800190 * Add a reloc at \p pos. No error checking.
Chia-I Wucdff0592014-08-22 09:27:36 +0800191 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800192static inline void cmd_writer_reloc(struct intel_cmd *cmd,
193 enum intel_cmd_writer_type which,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600194 size_t offset, intptr_t target,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800195 uint32_t target_offset, uint32_t flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800196{
197 struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used];
198
199 assert(cmd->reloc_used < cmd->reloc_count);
200
Chia-I Wu68f319d2014-09-09 09:43:21 +0800201 reloc->which = which;
Chia-I Wu72292b72014-09-09 10:48:33 +0800202 reloc->offset = offset;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800203 reloc->target = target;
204 reloc->target_offset = target_offset;
Chia-I Wu32a22462014-08-26 14:13:46 +0800205 reloc->flags = flags;
Chia-I Wucdff0592014-08-22 09:27:36 +0800206
207 cmd->reloc_used++;
208}
209
210/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800211 * Reserve a region from the state buffer. The offset, in bytes, to the
212 * reserved region is returned.
Chia-I Wu72292b72014-09-09 10:48:33 +0800213 *
214 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800215 */
Chia-I Wu5da476a2014-12-10 08:50:28 +0800216static inline uint32_t cmd_state_reserve(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800217 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600218 size_t alignment, uint32_t len)
Chia-I Wue24c3292014-08-21 14:05:23 +0800219{
Chia-I Wu72292b72014-09-09 10:48:33 +0800220 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600221 const size_t size = len << 2;
222 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800223 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800224
Chia-I Wu72292b72014-09-09 10:48:33 +0800225 /* all states are at least aligned to 32-bytes */
226 assert(alignment % 32 == 0);
227
Chia-I Wu72292b72014-09-09 10:48:33 +0800228 writer->used = offset + size;
229
Chia-I Wu465fe212015-02-11 11:27:06 -0700230 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800231 cmd_writer_record(cmd, which, item, offset, size);
232
Chia-I Wu72292b72014-09-09 10:48:33 +0800233 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800234}
235
236/**
Chia-I Wu5da476a2014-12-10 08:50:28 +0800237 * Get the pointer to a reserved region for updating. The pointer is only
238 * valid until the next reserve call.
239 */
240static inline void cmd_state_update(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600241 uint32_t offset, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800242 uint32_t **dw)
243{
244 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_STATE;
245 struct intel_cmd_writer *writer = &cmd->writers[which];
246
247 assert(offset + (len << 2) <= writer->used);
248
249 *dw = (uint32_t *) ((char *) writer->ptr + offset);
250}
251
252/**
253 * Reserve a region from the state buffer. Both the offset, in bytes, and the
254 * pointer to the reserved region are returned. The pointer is only valid
255 * until the next reserve call.
256 *
257 * Note that \p alignment is in bytes and \p len is in DWords.
258 */
259static inline uint32_t cmd_state_pointer(struct intel_cmd *cmd,
260 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600261 size_t alignment, uint32_t len,
Chia-I Wu5da476a2014-12-10 08:50:28 +0800262 uint32_t **dw)
263{
264 const uint32_t offset = cmd_state_reserve(cmd, item, alignment, len);
265
266 cmd_state_update(cmd, offset, len, dw);
267
268 return offset;
269}
270
271/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800272 * Write a dynamic state to the state buffer.
Chia-I Wucdff0592014-08-22 09:27:36 +0800273 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800274static inline uint32_t cmd_state_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800275 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600276 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800277 const uint32_t *dw)
Chia-I Wucdff0592014-08-22 09:27:36 +0800278{
Chia-I Wu72292b72014-09-09 10:48:33 +0800279 uint32_t offset, *dst;
280
Chia-I Wu00b51a82014-09-09 12:07:37 +0800281 offset = cmd_state_pointer(cmd, item, alignment, len, &dst);
Chia-I Wu72292b72014-09-09 10:48:33 +0800282 memcpy(dst, dw, len << 2);
283
284 return offset;
Chia-I Wucdff0592014-08-22 09:27:36 +0800285}
286
287/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800288 * Write a surface state to the surface buffer. The offset, in bytes, of the
289 * state is returned.
290 *
291 * Note that \p alignment is in bytes and \p len is in DWords.
Chia-I Wue24c3292014-08-21 14:05:23 +0800292 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800293static inline uint32_t cmd_surface_write(struct intel_cmd *cmd,
Chia-I Wu00b51a82014-09-09 12:07:37 +0800294 enum intel_cmd_item_type item,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600295 size_t alignment, uint32_t len,
Chia-I Wu72292b72014-09-09 10:48:33 +0800296 const uint32_t *dw)
Chia-I Wue24c3292014-08-21 14:05:23 +0800297{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800298 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wuf98dd882015-02-10 04:17:47 +0800299 const size_t size = len << 2;
Chia-I Wu15cccf72015-02-10 04:07:40 +0800300 const uint32_t offset = cmd_writer_reserve(cmd, which, alignment, size);
301 struct intel_cmd_writer *writer = &cmd->writers[which];
302 uint32_t *dst;
303
Chia-I Wu00b51a82014-09-09 12:07:37 +0800304 assert(item == INTEL_CMD_ITEM_SURFACE ||
305 item == INTEL_CMD_ITEM_BINDING_TABLE);
306
Chia-I Wu15cccf72015-02-10 04:07:40 +0800307 /* all states are at least aligned to 32-bytes */
308 assert(alignment % 32 == 0);
309
310 writer->used = offset + size;
311
312 if (intel_debug & INTEL_DEBUG_BATCH)
313 cmd_writer_record(cmd, which, item, offset, size);
314
315 dst = (uint32_t *) ((char *) writer->ptr + offset);
316 memcpy(dst, dw, size);
317
318 return offset;
Chia-I Wue24c3292014-08-21 14:05:23 +0800319}
320
321/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800322 * Add a relocation entry for a DWord of a surface state.
Chia-I Wucdff0592014-08-22 09:27:36 +0800323 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800324static inline void cmd_surface_reloc(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600325 uint32_t offset, uint32_t dw_index,
Chia-I Wu72292b72014-09-09 10:48:33 +0800326 struct intel_bo *bo,
327 uint32_t bo_offset, uint32_t reloc_flags)
Chia-I Wucdff0592014-08-22 09:27:36 +0800328{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800329 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wucdff0592014-08-22 09:27:36 +0800330
Chia-I Wu72292b72014-09-09 10:48:33 +0800331 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
Chia-I Wud7d1e482014-10-18 13:25:10 +0800332 (intptr_t) bo, bo_offset, reloc_flags);
333}
334
335static inline void cmd_surface_reloc_writer(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600336 uint32_t offset, uint32_t dw_index,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800337 enum intel_cmd_writer_type writer,
338 uint32_t writer_offset)
339{
Chia-I Wu15cccf72015-02-10 04:07:40 +0800340 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_SURFACE;
Chia-I Wud7d1e482014-10-18 13:25:10 +0800341
342 cmd_writer_reloc(cmd, which, offset + (dw_index << 2),
343 (intptr_t) writer, writer_offset,
344 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wucdff0592014-08-22 09:27:36 +0800345}
346
347/**
Chia-I Wu72292b72014-09-09 10:48:33 +0800348 * Write a kernel to the instruction buffer. The offset, in bytes, of the
349 * kernel is returned.
Chia-I Wue24c3292014-08-21 14:05:23 +0800350 */
Chia-I Wu72292b72014-09-09 10:48:33 +0800351static inline uint32_t cmd_instruction_write(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600352 size_t size,
Chia-I Wu72292b72014-09-09 10:48:33 +0800353 const void *kernel)
Chia-I Wue24c3292014-08-21 14:05:23 +0800354{
Chia-I Wu72292b72014-09-09 10:48:33 +0800355 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_INSTRUCTION;
356 /*
357 * From the Sandy Bridge PRM, volume 4 part 2, page 112:
358 *
359 * "Due to prefetch of the instruction stream, the EUs may attempt to
360 * access up to 8 instructions (128 bytes) beyond the end of the
361 * kernel program - possibly into the next memory page. Although
362 * these instructions will not be executed, software must account for
363 * the prefetch in order to avoid invalid page access faults."
364 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600365 const size_t reserved_size = size + 128;
Chia-I Wu72292b72014-09-09 10:48:33 +0800366 /* kernels are aligned to 64 bytes */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600367 const size_t alignment = 64;
368 const size_t offset = cmd_writer_reserve(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800369 which, alignment, reserved_size);
370 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +0800371
Chia-I Wu72292b72014-09-09 10:48:33 +0800372 memcpy((char *) writer->ptr + offset, kernel, size);
Chia-I Wu5e25c272014-08-21 20:19:12 +0800373
Chia-I Wu72292b72014-09-09 10:48:33 +0800374 writer->used = offset + size;
375
Chia-I Wu465fe212015-02-11 11:27:06 -0700376 if (intel_debug & (INTEL_DEBUG_BATCH | INTEL_DEBUG_HANG))
Chia-I Wu00b51a82014-09-09 12:07:37 +0800377 cmd_writer_record(cmd, which, INTEL_CMD_ITEM_KERNEL, offset, size);
378
Chia-I Wu72292b72014-09-09 10:48:33 +0800379 return offset;
380}
381
382/**
383 * Reserve a region from the batch buffer. Both the offset, in DWords, and
Chia-I Wu5da476a2014-12-10 08:50:28 +0800384 * the pointer to the reserved region are returned. The pointer is only valid
385 * until the next reserve call.
Chia-I Wu72292b72014-09-09 10:48:33 +0800386 *
387 * Note that \p len is in DWords.
388 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600389static inline uint32_t cmd_batch_pointer(struct intel_cmd *cmd,
390 uint32_t len, uint32_t **dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800391{
392 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
393 /*
394 * We know the batch bo is always aligned. Using 1 here should allow the
395 * compiler to optimize away aligning.
396 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600397 const size_t alignment = 1;
398 const size_t size = len << 2;
399 const size_t offset = cmd_writer_reserve(cmd, which, alignment, size);
Chia-I Wu72292b72014-09-09 10:48:33 +0800400 struct intel_cmd_writer *writer = &cmd->writers[which];
401
402 assert(offset % 4 == 0);
403 *dw = (uint32_t *) ((char *) writer->ptr + offset);
404
405 writer->used = offset + size;
406
407 return offset >> 2;
408}
409
410/**
411 * Write a command to the batch buffer.
412 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600413static inline uint32_t cmd_batch_write(struct intel_cmd *cmd,
414 uint32_t len, const uint32_t *dw)
Chia-I Wu72292b72014-09-09 10:48:33 +0800415{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600416 uint32_t pos;
Chia-I Wu72292b72014-09-09 10:48:33 +0800417 uint32_t *dst;
418
419 pos = cmd_batch_pointer(cmd, len, &dst);
420 memcpy(dst, dw, len << 2);
421
422 return pos;
423}
424
425/**
426 * Add a relocation entry for a DWord of a command.
427 */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600428static inline void cmd_batch_reloc(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wu72292b72014-09-09 10:48:33 +0800429 struct intel_bo *bo,
430 uint32_t bo_offset, uint32_t reloc_flags)
431{
432 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
433
Chia-I Wud7d1e482014-10-18 13:25:10 +0800434 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) bo, bo_offset, reloc_flags);
435}
436
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600437static inline void cmd_batch_reloc_writer(struct intel_cmd *cmd, uint32_t pos,
Chia-I Wud7d1e482014-10-18 13:25:10 +0800438 enum intel_cmd_writer_type writer,
439 uint32_t writer_offset)
440{
441 const enum intel_cmd_writer_type which = INTEL_CMD_WRITER_BATCH;
442
443 cmd_writer_reloc(cmd, which, pos << 2, (intptr_t) writer, writer_offset,
444 INTEL_CMD_RELOC_TARGET_IS_WRITER);
Chia-I Wue24c3292014-08-21 14:05:23 +0800445}
446
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800447void cmd_batch_state_base_address(struct intel_cmd *cmd);
448
Chia-I Wue24c3292014-08-21 14:05:23 +0800449/**
Chia-I Wu48c283d2014-08-25 23:13:46 +0800450 * Begin the batch buffer.
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800451 */
452static inline void cmd_batch_begin(struct intel_cmd *cmd)
453{
Chia-I Wu66bdcd72015-02-10 04:11:31 +0800454 cmd_batch_state_base_address(cmd);
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800455}
456
457/**
Chia-I Wue24c3292014-08-21 14:05:23 +0800458 * End the batch buffer.
459 */
460static inline void cmd_batch_end(struct intel_cmd *cmd)
461{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800462 struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_BATCH];
Chia-I Wu72292b72014-09-09 10:48:33 +0800463 uint32_t *dw;
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800464
Chia-I Wu72292b72014-09-09 10:48:33 +0800465 if (writer->used & 0x7) {
466 cmd_batch_pointer(cmd, 1, &dw);
467 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
Chia-I Wue24c3292014-08-21 14:05:23 +0800468 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +0800469 cmd_batch_pointer(cmd, 2, &dw);
470 dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
471 dw[1] = GEN6_MI_CMD(MI_NOOP);
Chia-I Wue24c3292014-08-21 14:05:23 +0800472 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800473}
474
Chia-I Wu525c6602014-08-27 10:22:34 +0800475void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0);
Chia-I Wu3fb47ce2014-10-28 11:19:36 +0800476void cmd_batch_flush_all(struct intel_cmd *cmd);
Chia-I Wu525c6602014-08-27 10:22:34 +0800477
Chia-I Wu759fa2e2014-08-30 18:44:47 +0800478void cmd_batch_depth_count(struct intel_cmd *cmd,
479 struct intel_bo *bo,
480 XGL_GPU_SIZE offset);
481
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800482void cmd_batch_timestamp(struct intel_cmd *cmd,
483 struct intel_bo *bo,
484 XGL_GPU_SIZE offset);
485
486void cmd_batch_immediate(struct intel_cmd *cmd,
Mike Stroyan55658c22014-12-04 11:08:39 +0000487 uint32_t pipe_control_flags,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +0800488 struct intel_bo *bo,
489 XGL_GPU_SIZE offset,
490 uint64_t val);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800491
Chia-I Wuc14d1562014-10-17 09:49:22 +0800492void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta);
493
Chia-I Wu00a23b22014-08-20 15:28:08 +0800494#endif /* CMD_PRIV_H */