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Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
Chia-I Wu714df452015-01-01 07:55:04 +080028#include "buf.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080029#include "img.h"
30#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080031#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080032#include "cmd_priv.h"
33
Chia-I Wu714df452015-01-01 07:55:04 +080034static XGL_RESULT cmd_meta_create_buf_view(struct intel_cmd *cmd,
35 XGL_BUFFER buf,
36 XGL_GPU_SIZE range,
37 XGL_FORMAT format,
38 struct intel_buf_view **view)
Chia-I Wuc14d1562014-10-17 09:49:22 +080039{
Chia-I Wu714df452015-01-01 07:55:04 +080040 XGL_BUFFER_VIEW_CREATE_INFO info;
Chia-I Wuc14d1562014-10-17 09:49:22 +080041
42 memset(&info, 0, sizeof(info));
Chia-I Wu714df452015-01-01 07:55:04 +080043 info.sType = XGL_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO;
44 info.buffer = buf;
45 info.viewType = XGL_BUFFER_VIEW_TYPED;
Chia-I Wuc14d1562014-10-17 09:49:22 +080046 info.stride = icd_format_get_size(format);
47 info.format = format;
Chia-I Wu714df452015-01-01 07:55:04 +080048 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
49 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
50 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
51 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
52 info.range = range;
Chia-I Wuc14d1562014-10-17 09:49:22 +080053
Chia-I Wubc7a30c2014-12-13 15:54:10 +080054 /*
55 * We do not rely on the hardware to avoid out-of-bound access. But we do
56 * not want the hardware to ignore the last element either.
57 */
58 if (info.range % info.stride)
59 info.range += info.stride - (info.range % info.stride);
60
Chia-I Wu714df452015-01-01 07:55:04 +080061 return intel_buf_view_create(cmd->dev, &info, view);
Chia-I Wuc14d1562014-10-17 09:49:22 +080062}
63
Chia-I Wu714df452015-01-01 07:55:04 +080064static void cmd_meta_set_src_for_buf(struct intel_cmd *cmd,
65 const struct intel_buf *buf,
Chia-I Wuc14d1562014-10-17 09:49:22 +080066 XGL_FORMAT format,
67 struct intel_cmd_meta *meta)
68{
Chia-I Wu714df452015-01-01 07:55:04 +080069 struct intel_buf_view *view;
70 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +080071
Chia-I Wu714df452015-01-01 07:55:04 +080072 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) buf,
73 buf->size, format, &view);
74 if (res != XGL_SUCCESS) {
75 cmd->result = res;
76 return;
77 }
Chia-I Wuc14d1562014-10-17 09:49:22 +080078
79 meta->src.valid = true;
80
Chia-I Wu714df452015-01-01 07:55:04 +080081 memcpy(meta->src.surface, view->cmd,
82 sizeof(view->cmd[0]) * view->cmd_len);
83 meta->src.surface_len = view->cmd_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +080084
Chia-I Wu714df452015-01-01 07:55:04 +080085 intel_buf_view_destroy(view);
86
87 meta->src.reloc_target = (intptr_t) buf->obj.mem->bo;
Chia-I Wuc14d1562014-10-17 09:49:22 +080088 meta->src.reloc_offset = 0;
89 meta->src.reloc_flags = 0;
90}
91
Chia-I Wu714df452015-01-01 07:55:04 +080092static void cmd_meta_set_dst_for_buf(struct intel_cmd *cmd,
93 const struct intel_buf *buf,
Chia-I Wuc14d1562014-10-17 09:49:22 +080094 XGL_FORMAT format,
95 struct intel_cmd_meta *meta)
96{
Chia-I Wu714df452015-01-01 07:55:04 +080097 struct intel_buf_view *view;
98 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +080099
Chia-I Wu714df452015-01-01 07:55:04 +0800100 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) buf,
101 buf->size, format, &view);
102 if (res != XGL_SUCCESS) {
103 cmd->result = res;
104 return;
105 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800106
107 meta->dst.valid = true;
108
Chia-I Wu714df452015-01-01 07:55:04 +0800109 memcpy(meta->dst.surface, view->cmd,
110 sizeof(view->cmd[0]) * view->cmd_len);
111 meta->dst.surface_len = view->cmd_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800112
Chia-I Wu714df452015-01-01 07:55:04 +0800113 intel_buf_view_destroy(view);
114
115 meta->dst.reloc_target = (intptr_t) buf->obj.mem->bo;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800116 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800117 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800118}
119
120static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
121 const struct intel_img *img,
122 XGL_FORMAT format,
123 XGL_IMAGE_ASPECT aspect,
124 struct intel_cmd_meta *meta)
125{
126 XGL_IMAGE_VIEW_CREATE_INFO info;
127 struct intel_img_view *view;
128 XGL_RESULT ret;
129
130 memset(&info, 0, sizeof(info));
131 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
132 info.image = (XGL_IMAGE) img;
133
134 switch (img->type) {
135 case XGL_IMAGE_1D:
136 info.viewType = XGL_IMAGE_VIEW_1D;
137 break;
138 case XGL_IMAGE_2D:
139 info.viewType = XGL_IMAGE_VIEW_2D;
140 break;
141 case XGL_IMAGE_3D:
142 info.viewType = XGL_IMAGE_VIEW_3D;
143 break;
144 default:
145 break;
146 }
147
148 info.format = format;
149 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
150 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
151 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
152 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
153 info.subresourceRange.aspect = aspect;
154 info.subresourceRange.baseMipLevel = 0;
155 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
156 info.subresourceRange.baseArraySlice = 0;
157 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
158
159 ret = intel_img_view_create(cmd->dev, &info, &view);
160 if (ret != XGL_SUCCESS) {
161 cmd->result = ret;
162 return;
163 }
164
165 meta->src.valid = true;
166
167 memcpy(meta->src.surface, view->cmd,
168 sizeof(view->cmd[0]) * view->cmd_len);
169 meta->src.surface_len = view->cmd_len;
170
171 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
172 meta->src.reloc_offset = 0;
173 meta->src.reloc_flags = 0;
174
175 intel_img_view_destroy(view);
176}
177
Chia-I Wu83084ba2014-12-04 12:49:52 +0800178static void cmd_meta_adjust_compressed_dst(struct intel_cmd *cmd,
179 const struct intel_img *img,
180 struct intel_cmd_meta *meta)
181{
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800182 XGL_INT w, h, layer;
183 unsigned x_offset, y_offset;
Chia-I Wu83084ba2014-12-04 12:49:52 +0800184
185 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
186 w = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_WIDTH);
187 h = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800188 layer = GEN_EXTRACT(meta->dst.surface[4],
189 GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800190 } else {
191 w = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_WIDTH);
192 h = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800193 layer = GEN_EXTRACT(meta->dst.surface[4],
194 GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800195 }
196
197 /* note that the width/height fields have the real values minus 1 */
198 w = (w + img->layout.block_width) / img->layout.block_width - 1;
199 h = (h + img->layout.block_height) / img->layout.block_height - 1;
200
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800201 /* adjust width and height */
Chia-I Wu83084ba2014-12-04 12:49:52 +0800202 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800203 meta->dst.surface[2] &= ~(GEN7_SURFACE_DW2_WIDTH__MASK |
204 GEN7_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800205 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN7_SURFACE_DW2_WIDTH) |
206 GEN_SHIFT32(h, GEN7_SURFACE_DW2_HEIGHT);
207 } else {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800208 meta->dst.surface[2] &= ~(GEN6_SURFACE_DW2_WIDTH__MASK |
209 GEN6_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800210 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN6_SURFACE_DW2_WIDTH) |
211 GEN_SHIFT32(h, GEN6_SURFACE_DW2_HEIGHT);
212 }
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800213
214 if (!layer)
215 return;
216
217 meta->dst.reloc_offset = intel_layout_get_slice_tile_offset(&img->layout,
218 0, layer, &x_offset, &y_offset);
219
220 /*
221 * The lower 2 bits (or 1 bit for Y) are missing. This may be a problem
222 * for small images (16x16 or smaller). We will need to adjust the
223 * drawing rectangle instead.
224 */
225 x_offset = (x_offset / img->layout.block_width) >> 2;
226 y_offset = (y_offset / img->layout.block_height) >> 1;
227
228 /* adjust min array element and X/Y offsets */
229 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
230 meta->dst.surface[4] &= ~GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
231 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN7_SURFACE_DW5_X_OFFSET) |
232 GEN_SHIFT32(y_offset, GEN7_SURFACE_DW5_Y_OFFSET);
233 } else {
234 meta->dst.surface[4] &= ~GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
235 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN6_SURFACE_DW5_X_OFFSET) |
236 GEN_SHIFT32(y_offset, GEN6_SURFACE_DW5_Y_OFFSET);
237 }
Chia-I Wu83084ba2014-12-04 12:49:52 +0800238}
239
Chia-I Wuc14d1562014-10-17 09:49:22 +0800240static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
241 const struct intel_img *img,
242 XGL_FORMAT format,
243 XGL_UINT lod, XGL_UINT layer,
244 struct intel_cmd_meta *meta)
245{
246 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
247 struct intel_rt_view *rt;
248 XGL_RESULT ret;
249
250 memset(&info, 0, sizeof(info));
251 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
252 info.image = (XGL_IMAGE) img;
253 info.format = format;
254 info.mipLevel = lod;
255 info.baseArraySlice = layer;
256 info.arraySize = 1;
257
258 ret = intel_rt_view_create(cmd->dev, &info, &rt);
259 if (ret != XGL_SUCCESS) {
260 cmd->result = ret;
261 return;
262 }
263
264 meta->dst.valid = true;
265
266 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
267 meta->dst.surface_len = rt->cmd_len;
268
269 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
270 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800271 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800272
Chia-I Wu83084ba2014-12-04 12:49:52 +0800273 if (icd_format_is_compressed(img->layout.format))
274 cmd_meta_adjust_compressed_dst(cmd, img, meta);
275
Chia-I Wuc14d1562014-10-17 09:49:22 +0800276 intel_rt_view_destroy(rt);
277}
278
279static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
280 enum intel_cmd_writer_type writer,
281 XGL_GPU_SIZE size,
282 XGL_FORMAT format,
283 struct intel_cmd_meta *meta)
284{
Chia-I Wu714df452015-01-01 07:55:04 +0800285 struct intel_buf_view *view;
286 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800287
Chia-I Wu714df452015-01-01 07:55:04 +0800288 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) XGL_NULL_HANDLE,
289 size, format, &view);
290 if (res != XGL_SUCCESS) {
291 cmd->result = res;
292 return;
293 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800294
295 meta->src.valid = true;
296
Chia-I Wu714df452015-01-01 07:55:04 +0800297 memcpy(meta->src.surface, view->cmd,
298 sizeof(view->cmd[0]) * view->cmd_len);
299 meta->src.surface_len = view->cmd_len;
300
301 intel_buf_view_destroy(view);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800302
303 meta->src.reloc_target = (intptr_t) writer;
304 meta->src.reloc_offset = 0;
305 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
306}
307
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800308static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
309 const struct intel_img *img,
310 XGL_UINT lod, XGL_UINT layer,
311 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800312{
313 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
314 struct intel_ds_view *ds;
315 XGL_RESULT ret;
316
317 memset(&info, 0, sizeof(info));
318 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
319 info.image = (XGL_IMAGE) img;
320 info.mipLevel = lod;
321 info.baseArraySlice = layer;
322 info.arraySize = 1;
323
324 ret = intel_ds_view_create(cmd->dev, &info, &ds);
325 if (ret != XGL_SUCCESS) {
326 cmd->result = ret;
327 return;
328 }
329
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800330 meta->ds.view = ds;
331}
332
333static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
334 XGL_IMAGE_ASPECT aspect,
335 XGL_UINT32 stencil_ref,
336 struct intel_cmd_meta *meta)
337{
Tony Barbourfa6cac72015-01-16 14:27:35 -0700338 meta->ds.stencil_ref = stencil_ref;
339 meta->ds.aspect = aspect;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800340}
341
342static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
343 const struct intel_img *img,
344 bool copy_array)
345{
346 enum intel_dev_meta_shader shader_id;
347
348 switch (img->type) {
349 case XGL_IMAGE_1D:
350 shader_id = (copy_array) ?
351 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
352 break;
353 case XGL_IMAGE_2D:
354 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
355 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
356 INTEL_DEV_META_FS_COPY_2D;
357 break;
358 case XGL_IMAGE_3D:
359 default:
360 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
361 break;
362 }
363
364 return shader_id;
365}
366
Chia-I Wuf3a27252014-11-24 15:27:01 +0800367static bool cmd_meta_mem_dword_aligned(const struct intel_cmd *cmd,
368 XGL_GPU_SIZE src_offset,
369 XGL_GPU_SIZE dst_offset,
370 XGL_GPU_SIZE size)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800371{
Chia-I Wuf3a27252014-11-24 15:27:01 +0800372 return !((src_offset | dst_offset | size) & 0x3);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800373}
374
375static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
376 XGL_FORMAT format)
377{
378 format.numericFormat = XGL_NUM_FMT_UINT;
379
Chia-I Wuffdde352014-12-20 15:12:16 +0800380 switch (icd_format_get_size(format)) {
381 case 1:
382 format.channelFormat = XGL_CH_FMT_R8;
383 break;
384 case 2:
385 format.channelFormat = XGL_CH_FMT_R16;
386 break;
387 case 4:
388 format.channelFormat = XGL_CH_FMT_R32;
389 break;
390 case 8:
391 format.channelFormat = XGL_CH_FMT_R32G32;
392 break;
393 case 16:
394 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
395 break;
396 default:
397 assert(!"unsupported image format for raw blit op");
398 format.channelFormat = XGL_CH_FMT_UNDEFINED;
399 format.numericFormat = XGL_NUM_FMT_UNDEFINED;
400 break;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800401 }
402
403 return format;
404}
405
Chia-I Wu714df452015-01-01 07:55:04 +0800406ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800407 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800408 XGL_BUFFER srcBuffer,
409 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800410 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800411 const XGL_BUFFER_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800412{
413 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800414 struct intel_buf *src = intel_buf(srcBuffer);
415 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800416 struct intel_cmd_meta meta;
417 XGL_FORMAT format;
418 XGL_UINT i;
419
420 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800421 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800422
Chia-I Wuc14d1562014-10-17 09:49:22 +0800423 meta.height = 1;
424 meta.samples = 1;
425
426 format.channelFormat = XGL_CH_FMT_UNDEFINED;
427 format.numericFormat = XGL_NUM_FMT_UINT;
428
429 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800430 const XGL_BUFFER_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800431 XGL_CHANNEL_FORMAT ch;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800432
Chia-I Wuf3a27252014-11-24 15:27:01 +0800433 meta.src.x = region->srcOffset;
434 meta.dst.x = region->destOffset;
435 meta.width = region->copySize;
436
437 if (cmd_meta_mem_dword_aligned(cmd, region->srcOffset,
438 region->destOffset, region->copySize)) {
439 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
440 meta.src.x /= 4;
441 meta.dst.x /= 4;
442 meta.width /= 4;
443
444 /*
445 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to
446 * be 16
447 */
448 ch = XGL_CH_FMT_R32G32B32A32;
449 } else {
450 if (cmd_gen(cmd) == INTEL_GEN(6)) {
451 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
452 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
Chia-I Wu714df452015-01-01 07:55:04 +0800453 "unaligned xglCmdCopyBuffer unsupported");
Chia-I Wuf3a27252014-11-24 15:27:01 +0800454 cmd->result = XGL_ERROR_UNKNOWN;
455 continue;
456 }
457
458 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM_UNALIGNED;
459
460 /*
461 * INTEL_DEV_META_VS_COPY_MEM_UNALIGNED is untyped but expects the
462 * stride to be 4
463 */
464 ch = XGL_CH_FMT_R8G8B8A8;
465 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800466
467 if (format.channelFormat != ch) {
468 format.channelFormat = ch;
469
Chia-I Wu714df452015-01-01 07:55:04 +0800470 cmd_meta_set_src_for_buf(cmd, src, format, &meta);
471 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800472 }
473
Chia-I Wuc14d1562014-10-17 09:49:22 +0800474 cmd_draw_meta(cmd, &meta);
475 }
476}
477
Chia-I Wu96177272015-01-03 15:27:41 +0800478ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800479 XGL_CMD_BUFFER cmdBuffer,
480 XGL_IMAGE srcImage,
481 XGL_IMAGE destImage,
482 XGL_UINT regionCount,
483 const XGL_IMAGE_COPY* pRegions)
484{
485 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
486 struct intel_img *src = intel_img(srcImage);
487 struct intel_img *dst = intel_img(destImage);
488 struct intel_cmd_meta meta;
489 XGL_FORMAT raw_format;
490 bool raw_copy;
491 XGL_UINT i;
492
493 if (src->type != dst->type) {
494 cmd->result = XGL_ERROR_UNKNOWN;
495 return;
496 }
497
498 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
499 raw_copy = true;
500 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
501 } else if (icd_format_is_compressed(src->layout.format) ||
502 icd_format_is_compressed(dst->layout.format)) {
503 cmd->result = XGL_ERROR_UNKNOWN;
504 return;
505 }
506
507 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800508 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800509
510 cmd_meta_set_src_for_img(cmd, src,
511 (raw_copy) ? raw_format : src->layout.format,
512 XGL_IMAGE_ASPECT_COLOR, &meta);
513
514 meta.samples = dst->samples;
515
516 for (i = 0; i < regionCount; i++) {
517 const XGL_IMAGE_COPY *region = &pRegions[i];
518 XGL_UINT j;
519
520 meta.shader_id = get_shader_id(cmd->dev, src,
521 (region->extent.depth > 1));
522
523 meta.src.lod = region->srcSubresource.mipLevel;
524 meta.src.layer = region->srcSubresource.arraySlice +
525 region->srcOffset.z;
526 meta.src.x = region->srcOffset.x;
527 meta.src.y = region->srcOffset.y;
528
529 meta.dst.lod = region->destSubresource.mipLevel;
530 meta.dst.layer = region->destSubresource.arraySlice +
531 region->destOffset.z;
532 meta.dst.x = region->destOffset.x;
533 meta.dst.y = region->destOffset.y;
534
535 meta.width = region->extent.width;
536 meta.height = region->extent.height;
537
538 for (j = 0; j < region->extent.depth; j++) {
539 cmd_meta_set_dst_for_img(cmd, dst,
540 (raw_copy) ? raw_format : dst->layout.format,
541 meta.dst.lod, meta.dst.layer, &meta);
542
543 cmd_draw_meta(cmd, &meta);
544
545 meta.src.layer++;
546 meta.dst.layer++;
547 }
548 }
549}
550
Chia-I Wu714df452015-01-01 07:55:04 +0800551ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyBufferToImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800552 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800553 XGL_BUFFER srcBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800554 XGL_IMAGE destImage,
555 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800556 const XGL_BUFFER_IMAGE_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800557{
558 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800559 struct intel_buf *buf = intel_buf(srcBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800560 struct intel_img *img = intel_img(destImage);
561 struct intel_cmd_meta meta;
562 XGL_FORMAT format;
563 XGL_UINT i;
564
565 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800566 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800567
568 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
569 meta.samples = img->samples;
570
571 format = cmd_meta_img_raw_format(cmd, img->layout.format);
Chia-I Wu714df452015-01-01 07:55:04 +0800572 cmd_meta_set_src_for_buf(cmd, buf, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800573
574 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800575 const XGL_BUFFER_IMAGE_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800576 XGL_UINT j;
577
Chia-I Wu714df452015-01-01 07:55:04 +0800578 meta.src.x = region->bufferOffset / icd_format_get_size(format);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800579
580 meta.dst.lod = region->imageSubresource.mipLevel;
581 meta.dst.layer = region->imageSubresource.arraySlice +
582 region->imageOffset.z;
583 meta.dst.x = region->imageOffset.x;
584 meta.dst.y = region->imageOffset.y;
585
586 meta.width = region->imageExtent.width;
587 meta.height = region->imageExtent.height;
588
589 for (j = 0; j < region->imageExtent.depth; j++) {
590 cmd_meta_set_dst_for_img(cmd, img, format,
591 meta.dst.lod, meta.dst.layer, &meta);
592
593 cmd_draw_meta(cmd, &meta);
594
595 meta.src.x += meta.width * meta.height;
596 meta.dst.layer++;
597 }
598 }
599}
600
Chia-I Wu714df452015-01-01 07:55:04 +0800601ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyImageToBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800602 XGL_CMD_BUFFER cmdBuffer,
603 XGL_IMAGE srcImage,
Chia-I Wu714df452015-01-01 07:55:04 +0800604 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800605 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800606 const XGL_BUFFER_IMAGE_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800607{
608 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
609 struct intel_img *img = intel_img(srcImage);
Chia-I Wu714df452015-01-01 07:55:04 +0800610 struct intel_buf *buf = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800611 struct intel_cmd_meta meta;
Chia-I Wu714df452015-01-01 07:55:04 +0800612 XGL_FORMAT img_format, buf_format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800613 XGL_UINT i;
614
615 memset(&meta, 0, sizeof(meta));
Chia-I Wua44b6482014-12-20 14:58:01 +0800616 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800617
Chia-I Wua44b6482014-12-20 14:58:01 +0800618 img_format = cmd_meta_img_raw_format(cmd, img->layout.format);
Chia-I Wu714df452015-01-01 07:55:04 +0800619 buf_format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800620
Chia-I Wu714df452015-01-01 07:55:04 +0800621 /* buf_format is ignored by hw, but we derive stride from it */
Chia-I Wua44b6482014-12-20 14:58:01 +0800622 switch (img_format.channelFormat) {
623 case XGL_CH_FMT_R8:
624 meta.shader_id = INTEL_DEV_META_VS_COPY_R8_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800625 buf_format.channelFormat = XGL_CH_FMT_R8G8B8A8;
Chia-I Wua44b6482014-12-20 14:58:01 +0800626 break;
627 case XGL_CH_FMT_R16:
628 meta.shader_id = INTEL_DEV_META_VS_COPY_R16_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800629 buf_format.channelFormat = XGL_CH_FMT_R8G8B8A8;
Chia-I Wua44b6482014-12-20 14:58:01 +0800630 break;
631 case XGL_CH_FMT_R32:
632 meta.shader_id = INTEL_DEV_META_VS_COPY_R32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800633 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800634 break;
635 case XGL_CH_FMT_R32G32:
636 meta.shader_id = INTEL_DEV_META_VS_COPY_R32G32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800637 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800638 break;
639 case XGL_CH_FMT_R32G32B32A32:
640 meta.shader_id = INTEL_DEV_META_VS_COPY_R32G32B32A32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800641 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800642 break;
643 default:
644 break;
645 }
646
647 if (img_format.channelFormat == XGL_CH_FMT_UNDEFINED ||
648 (cmd_gen(cmd) == INTEL_GEN(6) &&
649 icd_format_get_size(img_format) < 4)) {
650 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
651 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
Chia-I Wu714df452015-01-01 07:55:04 +0800652 "xglCmdCopyImageToBuffer with bpp %d unsupported",
Chia-I Wua44b6482014-12-20 14:58:01 +0800653 icd_format_get_size(img->layout.format));
654 cmd->result = XGL_ERROR_UNKNOWN;
655 return;
656 }
657
658 cmd_meta_set_src_for_img(cmd, img, img_format,
659 XGL_IMAGE_ASPECT_COLOR, &meta);
Chia-I Wu714df452015-01-01 07:55:04 +0800660 cmd_meta_set_dst_for_buf(cmd, buf, buf_format, &meta);
Chia-I Wua44b6482014-12-20 14:58:01 +0800661
Chia-I Wuc14d1562014-10-17 09:49:22 +0800662 meta.samples = 1;
663
664 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800665 const XGL_BUFFER_IMAGE_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800666 XGL_UINT j;
667
Chia-I Wuc14d1562014-10-17 09:49:22 +0800668 meta.src.lod = region->imageSubresource.mipLevel;
669 meta.src.layer = region->imageSubresource.arraySlice +
670 region->imageOffset.z;
671 meta.src.x = region->imageOffset.x;
672 meta.src.y = region->imageOffset.y;
673
Chia-I Wu714df452015-01-01 07:55:04 +0800674 meta.dst.x = region->bufferOffset / icd_format_get_size(img_format);
Chia-I Wua44b6482014-12-20 14:58:01 +0800675 meta.width = region->imageExtent.width;
676 meta.height = region->imageExtent.height;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800677
678 for (j = 0; j < region->imageExtent.depth; j++) {
679 cmd_draw_meta(cmd, &meta);
680
681 meta.src.layer++;
Chia-I Wua44b6482014-12-20 14:58:01 +0800682 meta.dst.x += meta.width * meta.height;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800683 }
684 }
685}
686
Chia-I Wu96177272015-01-03 15:27:41 +0800687ICD_EXPORT XGL_VOID XGLAPI xglCmdCloneImageData(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800688 XGL_CMD_BUFFER cmdBuffer,
689 XGL_IMAGE srcImage,
690 XGL_IMAGE_STATE srcImageState,
691 XGL_IMAGE destImage,
692 XGL_IMAGE_STATE destImageState)
693{
Chia-I Wud788fc62014-12-22 14:24:11 +0800694 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
695 struct intel_img *src = intel_img(srcImage);
696 struct intel_img *dst = intel_img(destImage);
Chia-I Wu714df452015-01-01 07:55:04 +0800697 struct intel_buf *src_buf, *dst_buf;
698 XGL_BUFFER_CREATE_INFO buf_info;
699 XGL_BUFFER_COPY buf_region;
700 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800701
Chia-I Wu714df452015-01-01 07:55:04 +0800702 memset(&buf_info, 0, sizeof(buf_info));
703 buf_info.sType = XGL_STRUCTURE_TYPE_BUFFER_CREATE_INFO;
704 buf_info.size = src->obj.mem->size;
705
706 memset(&buf_region, 0, sizeof(buf_region));
707 buf_region.copySize = src->obj.mem->size;
708
709 res = intel_buf_create(cmd->dev, &buf_info, &src_buf);
710 if (res != XGL_SUCCESS) {
711 cmd->result = res;
712 return;
713 }
714
715 res = intel_buf_create(cmd->dev, &buf_info, &dst_buf);
716 if (res != XGL_SUCCESS) {
717 intel_buf_destroy(src_buf);
718 cmd->result = res;
719 return;
720 }
721
722 intel_obj_bind_mem(&src_buf->obj, src->obj.mem, 0);
723 intel_obj_bind_mem(&dst_buf->obj, dst->obj.mem, 0);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800724
Chia-I Wud788fc62014-12-22 14:24:11 +0800725 cmd_batch_flush(cmd, GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
Chia-I Wu714df452015-01-01 07:55:04 +0800726 xglCmdCopyBuffer(cmdBuffer, (XGL_BUFFER) src_buf,
727 (XGL_BUFFER) dst_buf, 1, &buf_region);
728
729 intel_buf_destroy(src_buf);
730 intel_buf_destroy(dst_buf);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800731}
732
Chia-I Wu714df452015-01-01 07:55:04 +0800733ICD_EXPORT XGL_VOID XGLAPI xglCmdUpdateBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800734 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800735 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800736 XGL_GPU_SIZE destOffset,
737 XGL_GPU_SIZE dataSize,
738 const XGL_UINT32* pData)
739{
740 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800741 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800742 struct intel_cmd_meta meta;
743 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800744 uint32_t *ptr;
745 uint32_t offset;
746
Chia-I Wuf3a27252014-11-24 15:27:01 +0800747 /* must be 4-byte aligned */
748 if ((destOffset | dataSize) & 3) {
749 cmd->result = XGL_ERROR_UNKNOWN;
750 return;
751 }
752
Chia-I Wuc14d1562014-10-17 09:49:22 +0800753 /* write to dynamic state writer first */
754 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
755 (dataSize + 3) / 4, &ptr);
756 memcpy(ptr, pData, dataSize);
757
Chia-I Wuc14d1562014-10-17 09:49:22 +0800758 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800759 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800760
Chia-I Wuf3a27252014-11-24 15:27:01 +0800761 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
762
763 meta.src.x = offset / 4;
764 meta.dst.x = destOffset / 4;
765 meta.width = dataSize / 4;
766 meta.height = 1;
767 meta.samples = 1;
768
769 /*
770 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to be 16
771 */
772 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
773 format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800774
775 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
776 offset + dataSize, format, &meta);
Chia-I Wu714df452015-01-01 07:55:04 +0800777 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800778
Chia-I Wuc14d1562014-10-17 09:49:22 +0800779 cmd_draw_meta(cmd, &meta);
780}
781
Chia-I Wu714df452015-01-01 07:55:04 +0800782ICD_EXPORT XGL_VOID XGLAPI xglCmdFillBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800783 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800784 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800785 XGL_GPU_SIZE destOffset,
786 XGL_GPU_SIZE fillSize,
787 XGL_UINT32 data)
788{
789 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800790 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800791 struct intel_cmd_meta meta;
792 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800793
794 /* must be 4-byte aligned */
795 if ((destOffset | fillSize) & 3) {
796 cmd->result = XGL_ERROR_UNKNOWN;
797 return;
798 }
799
800 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800801 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800802
Chia-I Wuf3a27252014-11-24 15:27:01 +0800803 meta.shader_id = INTEL_DEV_META_VS_FILL_MEM;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800804
805 meta.clear_val[0] = data;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800806
Chia-I Wuf3a27252014-11-24 15:27:01 +0800807 meta.dst.x = destOffset / 4;
808 meta.width = fillSize / 4;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800809 meta.height = 1;
810 meta.samples = 1;
811
Chia-I Wuf3a27252014-11-24 15:27:01 +0800812 /*
813 * INTEL_DEV_META_VS_FILL_MEM is untyped but expects the stride to be 16
814 */
815 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
816 format.numericFormat = XGL_NUM_FMT_UINT;
817
Chia-I Wu714df452015-01-01 07:55:04 +0800818 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuf3a27252014-11-24 15:27:01 +0800819
Chia-I Wuc14d1562014-10-17 09:49:22 +0800820 cmd_draw_meta(cmd, &meta);
821}
822
823static void cmd_meta_clear_image(struct intel_cmd *cmd,
824 struct intel_img *img,
825 XGL_FORMAT format,
826 struct intel_cmd_meta *meta,
827 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
828{
829 XGL_UINT mip_levels, array_size;
830 XGL_UINT i, j;
831
832 if (range->baseMipLevel >= img->mip_levels ||
833 range->baseArraySlice >= img->array_size)
834 return;
835
836 mip_levels = img->mip_levels - range->baseMipLevel;
837 if (mip_levels > range->mipLevels)
838 mip_levels = range->mipLevels;
839
840 array_size = img->array_size - range->baseArraySlice;
841 if (array_size > range->arraySize)
842 array_size = range->arraySize;
843
Chia-I Wuc14d1562014-10-17 09:49:22 +0800844 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800845 meta->dst.lod = range->baseMipLevel + i;
846 meta->dst.layer = range->baseArraySlice;
847
Chia-I Wuc14d1562014-10-17 09:49:22 +0800848 meta->width = u_minify(img->layout.width0, meta->dst.lod);
849 meta->height = u_minify(img->layout.height0, meta->dst.lod);
850
851 for (j = 0; j < array_size; j++) {
852 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
853 cmd_meta_set_dst_for_img(cmd, img, format,
854 meta->dst.lod, meta->dst.layer, meta);
855
856 cmd_draw_meta(cmd, meta);
857 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800858 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800859 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800860 cmd_meta_set_ds_state(cmd, range->aspect,
861 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800862
863 cmd_draw_meta(cmd, meta);
864
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800865 intel_ds_view_destroy(meta->ds.view);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800866 }
867
868 meta->dst.layer++;
869 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800870 }
871}
872
Chia-I Wu96177272015-01-03 15:27:41 +0800873ICD_EXPORT XGL_VOID XGLAPI xglCmdClearColorImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800874 XGL_CMD_BUFFER cmdBuffer,
875 XGL_IMAGE image,
876 const XGL_FLOAT color[4],
877 XGL_UINT rangeCount,
878 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
879{
880 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
881 struct intel_img *img = intel_img(image);
882 struct intel_cmd_meta meta;
883 XGL_UINT i;
884
885 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800886 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800887
888 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
889 meta.samples = img->samples;
890
891 meta.clear_val[0] = u_fui(color[0]);
892 meta.clear_val[1] = u_fui(color[1]);
893 meta.clear_val[2] = u_fui(color[2]);
894 meta.clear_val[3] = u_fui(color[3]);
895
896 for (i = 0; i < rangeCount; i++) {
897 cmd_meta_clear_image(cmd, img, img->layout.format,
898 &meta, &pRanges[i]);
899 }
900}
901
Chia-I Wu96177272015-01-03 15:27:41 +0800902ICD_EXPORT XGL_VOID XGLAPI xglCmdClearColorImageRaw(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800903 XGL_CMD_BUFFER cmdBuffer,
904 XGL_IMAGE image,
905 const XGL_UINT32 color[4],
906 XGL_UINT rangeCount,
907 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
908{
909 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
910 struct intel_img *img = intel_img(image);
911 struct intel_cmd_meta meta;
912 XGL_FORMAT format;
913 XGL_UINT i;
914
915 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800916 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800917
918 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
919 meta.samples = img->samples;
920
Chia-I Wuffdde352014-12-20 15:12:16 +0800921 icd_format_get_raw_value(img->layout.format, color, meta.clear_val);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800922 format = cmd_meta_img_raw_format(cmd, img->layout.format);
923
924 for (i = 0; i < rangeCount; i++)
925 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
926}
927
Chia-I Wu96177272015-01-03 15:27:41 +0800928ICD_EXPORT XGL_VOID XGLAPI xglCmdClearDepthStencil(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800929 XGL_CMD_BUFFER cmdBuffer,
930 XGL_IMAGE image,
931 XGL_FLOAT depth,
932 XGL_UINT32 stencil,
933 XGL_UINT rangeCount,
934 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
935{
936 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
937 struct intel_img *img = intel_img(image);
938 struct intel_cmd_meta meta;
939 XGL_UINT i;
940
941 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800942 meta.mode = INTEL_CMD_META_DEPTH_STENCIL_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800943
944 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
945 meta.samples = img->samples;
946
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800947 meta.clear_val[0] = u_fui(depth);
948 meta.clear_val[1] = stencil;
949
Chia-I Wuc14d1562014-10-17 09:49:22 +0800950 for (i = 0; i < rangeCount; i++) {
951 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
952
Chia-I Wuc14d1562014-10-17 09:49:22 +0800953 cmd_meta_clear_image(cmd, img, img->layout.format,
954 &meta, range);
955 }
956}
957
Chia-I Wu96177272015-01-03 15:27:41 +0800958ICD_EXPORT XGL_VOID XGLAPI xglCmdResolveImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800959 XGL_CMD_BUFFER cmdBuffer,
960 XGL_IMAGE srcImage,
961 XGL_IMAGE destImage,
962 XGL_UINT rectCount,
963 const XGL_IMAGE_RESOLVE* pRects)
964{
965 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
966 struct intel_img *src = intel_img(srcImage);
967 struct intel_img *dst = intel_img(destImage);
968 struct intel_cmd_meta meta;
969 XGL_FORMAT format;
970 XGL_UINT i;
971
972 if (src->samples <= 1 || dst->samples > 1 ||
973 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
974 cmd->result = XGL_ERROR_UNKNOWN;
975 return;
976 }
977
978 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800979 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800980
981 switch (src->samples) {
982 case 2:
983 default:
984 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
985 break;
986 case 4:
987 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
988 break;
989 case 8:
990 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
991 break;
992 case 16:
993 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
994 break;
995 }
996
997 meta.samples = 1;
998
999 format = cmd_meta_img_raw_format(cmd, src->layout.format);
1000 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
1001
1002 for (i = 0; i < rectCount; i++) {
1003 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
1004
1005 meta.src.lod = rect->srcSubresource.mipLevel;
1006 meta.src.layer = rect->srcSubresource.arraySlice;
1007 meta.src.x = rect->srcOffset.x;
1008 meta.src.y = rect->srcOffset.y;
1009
1010 meta.dst.lod = rect->destSubresource.mipLevel;
1011 meta.dst.layer = rect->destSubresource.arraySlice;
1012 meta.dst.x = rect->destOffset.x;
1013 meta.dst.y = rect->destOffset.y;
1014
1015 meta.width = rect->extent.width;
1016 meta.height = rect->extent.height;
1017
1018 cmd_meta_set_dst_for_img(cmd, dst, format,
1019 meta.dst.lod, meta.dst.layer, &meta);
1020
1021 cmd_draw_meta(cmd, &meta);
1022 }
1023}