blob: b234a5eec58aafe16e1e500ac938e0748215e3d4 [file] [log] [blame]
Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
Chia-I Wu714df452015-01-01 07:55:04 +080028#include "buf.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080029#include "img.h"
30#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080031#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080032#include "cmd_priv.h"
33
Chia-I Wu714df452015-01-01 07:55:04 +080034static XGL_RESULT cmd_meta_create_buf_view(struct intel_cmd *cmd,
35 XGL_BUFFER buf,
36 XGL_GPU_SIZE range,
37 XGL_FORMAT format,
38 struct intel_buf_view **view)
Chia-I Wuc14d1562014-10-17 09:49:22 +080039{
Chia-I Wu714df452015-01-01 07:55:04 +080040 XGL_BUFFER_VIEW_CREATE_INFO info;
Chia-I Wuc14d1562014-10-17 09:49:22 +080041
42 memset(&info, 0, sizeof(info));
Chia-I Wu714df452015-01-01 07:55:04 +080043 info.sType = XGL_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO;
44 info.buffer = buf;
45 info.viewType = XGL_BUFFER_VIEW_TYPED;
Chia-I Wuc14d1562014-10-17 09:49:22 +080046 info.stride = icd_format_get_size(format);
47 info.format = format;
Chia-I Wu714df452015-01-01 07:55:04 +080048 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
49 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
50 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
51 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
52 info.range = range;
Chia-I Wuc14d1562014-10-17 09:49:22 +080053
Chia-I Wubc7a30c2014-12-13 15:54:10 +080054 /*
55 * We do not rely on the hardware to avoid out-of-bound access. But we do
56 * not want the hardware to ignore the last element either.
57 */
58 if (info.range % info.stride)
59 info.range += info.stride - (info.range % info.stride);
60
Chia-I Wu714df452015-01-01 07:55:04 +080061 return intel_buf_view_create(cmd->dev, &info, view);
Chia-I Wuc14d1562014-10-17 09:49:22 +080062}
63
Chia-I Wu714df452015-01-01 07:55:04 +080064static void cmd_meta_set_src_for_buf(struct intel_cmd *cmd,
65 const struct intel_buf *buf,
Chia-I Wuc14d1562014-10-17 09:49:22 +080066 XGL_FORMAT format,
67 struct intel_cmd_meta *meta)
68{
Chia-I Wu714df452015-01-01 07:55:04 +080069 struct intel_buf_view *view;
70 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +080071
Chia-I Wu714df452015-01-01 07:55:04 +080072 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) buf,
73 buf->size, format, &view);
74 if (res != XGL_SUCCESS) {
75 cmd->result = res;
76 return;
77 }
Chia-I Wuc14d1562014-10-17 09:49:22 +080078
79 meta->src.valid = true;
80
Chia-I Wu714df452015-01-01 07:55:04 +080081 memcpy(meta->src.surface, view->cmd,
82 sizeof(view->cmd[0]) * view->cmd_len);
83 meta->src.surface_len = view->cmd_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +080084
Chia-I Wu714df452015-01-01 07:55:04 +080085 intel_buf_view_destroy(view);
86
87 meta->src.reloc_target = (intptr_t) buf->obj.mem->bo;
Chia-I Wuc14d1562014-10-17 09:49:22 +080088 meta->src.reloc_offset = 0;
89 meta->src.reloc_flags = 0;
90}
91
Chia-I Wu714df452015-01-01 07:55:04 +080092static void cmd_meta_set_dst_for_buf(struct intel_cmd *cmd,
93 const struct intel_buf *buf,
Chia-I Wuc14d1562014-10-17 09:49:22 +080094 XGL_FORMAT format,
95 struct intel_cmd_meta *meta)
96{
Chia-I Wu714df452015-01-01 07:55:04 +080097 struct intel_buf_view *view;
98 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +080099
Chia-I Wu714df452015-01-01 07:55:04 +0800100 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) buf,
101 buf->size, format, &view);
102 if (res != XGL_SUCCESS) {
103 cmd->result = res;
104 return;
105 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800106
107 meta->dst.valid = true;
108
Chia-I Wu714df452015-01-01 07:55:04 +0800109 memcpy(meta->dst.surface, view->cmd,
110 sizeof(view->cmd[0]) * view->cmd_len);
111 meta->dst.surface_len = view->cmd_len;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800112
Chia-I Wu714df452015-01-01 07:55:04 +0800113 intel_buf_view_destroy(view);
114
115 meta->dst.reloc_target = (intptr_t) buf->obj.mem->bo;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800116 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800117 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800118}
119
120static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
121 const struct intel_img *img,
122 XGL_FORMAT format,
123 XGL_IMAGE_ASPECT aspect,
124 struct intel_cmd_meta *meta)
125{
126 XGL_IMAGE_VIEW_CREATE_INFO info;
127 struct intel_img_view *view;
128 XGL_RESULT ret;
129
130 memset(&info, 0, sizeof(info));
131 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
132 info.image = (XGL_IMAGE) img;
133
134 switch (img->type) {
135 case XGL_IMAGE_1D:
136 info.viewType = XGL_IMAGE_VIEW_1D;
137 break;
138 case XGL_IMAGE_2D:
139 info.viewType = XGL_IMAGE_VIEW_2D;
140 break;
141 case XGL_IMAGE_3D:
142 info.viewType = XGL_IMAGE_VIEW_3D;
143 break;
144 default:
145 break;
146 }
147
148 info.format = format;
149 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
150 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
151 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
152 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
153 info.subresourceRange.aspect = aspect;
154 info.subresourceRange.baseMipLevel = 0;
155 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
156 info.subresourceRange.baseArraySlice = 0;
157 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
158
159 ret = intel_img_view_create(cmd->dev, &info, &view);
160 if (ret != XGL_SUCCESS) {
161 cmd->result = ret;
162 return;
163 }
164
165 meta->src.valid = true;
166
167 memcpy(meta->src.surface, view->cmd,
168 sizeof(view->cmd[0]) * view->cmd_len);
169 meta->src.surface_len = view->cmd_len;
170
171 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
172 meta->src.reloc_offset = 0;
173 meta->src.reloc_flags = 0;
174
175 intel_img_view_destroy(view);
176}
177
Chia-I Wu83084ba2014-12-04 12:49:52 +0800178static void cmd_meta_adjust_compressed_dst(struct intel_cmd *cmd,
179 const struct intel_img *img,
180 struct intel_cmd_meta *meta)
181{
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800182 XGL_INT w, h, layer;
183 unsigned x_offset, y_offset;
Chia-I Wu83084ba2014-12-04 12:49:52 +0800184
185 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
186 w = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_WIDTH);
187 h = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800188 layer = GEN_EXTRACT(meta->dst.surface[4],
189 GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800190 } else {
191 w = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_WIDTH);
192 h = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800193 layer = GEN_EXTRACT(meta->dst.surface[4],
194 GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800195 }
196
197 /* note that the width/height fields have the real values minus 1 */
198 w = (w + img->layout.block_width) / img->layout.block_width - 1;
199 h = (h + img->layout.block_height) / img->layout.block_height - 1;
200
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800201 /* adjust width and height */
Chia-I Wu83084ba2014-12-04 12:49:52 +0800202 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800203 meta->dst.surface[2] &= ~(GEN7_SURFACE_DW2_WIDTH__MASK |
204 GEN7_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800205 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN7_SURFACE_DW2_WIDTH) |
206 GEN_SHIFT32(h, GEN7_SURFACE_DW2_HEIGHT);
207 } else {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800208 meta->dst.surface[2] &= ~(GEN6_SURFACE_DW2_WIDTH__MASK |
209 GEN6_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800210 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN6_SURFACE_DW2_WIDTH) |
211 GEN_SHIFT32(h, GEN6_SURFACE_DW2_HEIGHT);
212 }
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800213
214 if (!layer)
215 return;
216
217 meta->dst.reloc_offset = intel_layout_get_slice_tile_offset(&img->layout,
218 0, layer, &x_offset, &y_offset);
219
220 /*
221 * The lower 2 bits (or 1 bit for Y) are missing. This may be a problem
222 * for small images (16x16 or smaller). We will need to adjust the
223 * drawing rectangle instead.
224 */
225 x_offset = (x_offset / img->layout.block_width) >> 2;
226 y_offset = (y_offset / img->layout.block_height) >> 1;
227
228 /* adjust min array element and X/Y offsets */
229 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
230 meta->dst.surface[4] &= ~GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
231 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN7_SURFACE_DW5_X_OFFSET) |
232 GEN_SHIFT32(y_offset, GEN7_SURFACE_DW5_Y_OFFSET);
233 } else {
234 meta->dst.surface[4] &= ~GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
235 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN6_SURFACE_DW5_X_OFFSET) |
236 GEN_SHIFT32(y_offset, GEN6_SURFACE_DW5_Y_OFFSET);
237 }
Chia-I Wu83084ba2014-12-04 12:49:52 +0800238}
239
Chia-I Wuc14d1562014-10-17 09:49:22 +0800240static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
241 const struct intel_img *img,
242 XGL_FORMAT format,
243 XGL_UINT lod, XGL_UINT layer,
244 struct intel_cmd_meta *meta)
245{
246 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
247 struct intel_rt_view *rt;
248 XGL_RESULT ret;
249
250 memset(&info, 0, sizeof(info));
251 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
252 info.image = (XGL_IMAGE) img;
253 info.format = format;
254 info.mipLevel = lod;
255 info.baseArraySlice = layer;
256 info.arraySize = 1;
257
258 ret = intel_rt_view_create(cmd->dev, &info, &rt);
259 if (ret != XGL_SUCCESS) {
260 cmd->result = ret;
261 return;
262 }
263
264 meta->dst.valid = true;
265
266 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
267 meta->dst.surface_len = rt->cmd_len;
268
269 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
270 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800271 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800272
Chia-I Wu83084ba2014-12-04 12:49:52 +0800273 if (icd_format_is_compressed(img->layout.format))
274 cmd_meta_adjust_compressed_dst(cmd, img, meta);
275
Chia-I Wuc14d1562014-10-17 09:49:22 +0800276 intel_rt_view_destroy(rt);
277}
278
279static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
280 enum intel_cmd_writer_type writer,
281 XGL_GPU_SIZE size,
282 XGL_FORMAT format,
283 struct intel_cmd_meta *meta)
284{
Chia-I Wu714df452015-01-01 07:55:04 +0800285 struct intel_buf_view *view;
286 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800287
Chia-I Wu714df452015-01-01 07:55:04 +0800288 res = cmd_meta_create_buf_view(cmd, (XGL_BUFFER) XGL_NULL_HANDLE,
289 size, format, &view);
290 if (res != XGL_SUCCESS) {
291 cmd->result = res;
292 return;
293 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800294
295 meta->src.valid = true;
296
Chia-I Wu714df452015-01-01 07:55:04 +0800297 memcpy(meta->src.surface, view->cmd,
298 sizeof(view->cmd[0]) * view->cmd_len);
299 meta->src.surface_len = view->cmd_len;
300
301 intel_buf_view_destroy(view);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800302
303 meta->src.reloc_target = (intptr_t) writer;
304 meta->src.reloc_offset = 0;
305 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
306}
307
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800308static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
309 const struct intel_img *img,
310 XGL_UINT lod, XGL_UINT layer,
311 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800312{
313 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
314 struct intel_ds_view *ds;
315 XGL_RESULT ret;
316
317 memset(&info, 0, sizeof(info));
318 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
319 info.image = (XGL_IMAGE) img;
320 info.mipLevel = lod;
321 info.baseArraySlice = layer;
322 info.arraySize = 1;
323
324 ret = intel_ds_view_create(cmd->dev, &info, &ds);
325 if (ret != XGL_SUCCESS) {
326 cmd->result = ret;
327 return;
328 }
329
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800330 meta->ds.view = ds;
331}
332
333static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
334 XGL_IMAGE_ASPECT aspect,
335 XGL_UINT32 stencil_ref,
336 struct intel_cmd_meta *meta)
337{
338 XGL_DEPTH_STENCIL_STATE_CREATE_INFO info;
339 struct intel_ds_state *state;
340 XGL_RESULT ret;
341
342 memset(&info, 0, sizeof(info));
343 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO;
344
345 if (aspect == XGL_IMAGE_ASPECT_DEPTH) {
346 info.depthWriteEnable = XGL_TRUE;
347 }
348 else if (aspect == XGL_IMAGE_ASPECT_STENCIL) {
349 info.stencilTestEnable = XGL_TRUE;
350 info.stencilReadMask = 0xff;
351 info.stencilWriteMask = 0xff;
352 info.front.stencilFailOp = XGL_STENCIL_OP_KEEP;
353 info.front.stencilPassOp = XGL_STENCIL_OP_REPLACE;
354 info.front.stencilDepthFailOp = XGL_STENCIL_OP_KEEP;
355 info.front.stencilFunc = XGL_COMPARE_ALWAYS;
356 info.front.stencilRef = stencil_ref;
357 info.back = info.front;
358 }
359
360 ret = intel_ds_state_create(cmd->dev, &info, &state);
361 if (ret != XGL_SUCCESS) {
362 cmd->result = ret;
363 return;
364 }
365
366 meta->ds.state = state;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800367}
368
369static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
370 const struct intel_img *img,
371 bool copy_array)
372{
373 enum intel_dev_meta_shader shader_id;
374
375 switch (img->type) {
376 case XGL_IMAGE_1D:
377 shader_id = (copy_array) ?
378 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
379 break;
380 case XGL_IMAGE_2D:
381 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
382 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
383 INTEL_DEV_META_FS_COPY_2D;
384 break;
385 case XGL_IMAGE_3D:
386 default:
387 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
388 break;
389 }
390
391 return shader_id;
392}
393
Chia-I Wuf3a27252014-11-24 15:27:01 +0800394static bool cmd_meta_mem_dword_aligned(const struct intel_cmd *cmd,
395 XGL_GPU_SIZE src_offset,
396 XGL_GPU_SIZE dst_offset,
397 XGL_GPU_SIZE size)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800398{
Chia-I Wuf3a27252014-11-24 15:27:01 +0800399 return !((src_offset | dst_offset | size) & 0x3);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800400}
401
402static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
403 XGL_FORMAT format)
404{
405 format.numericFormat = XGL_NUM_FMT_UINT;
406
Chia-I Wuffdde352014-12-20 15:12:16 +0800407 switch (icd_format_get_size(format)) {
408 case 1:
409 format.channelFormat = XGL_CH_FMT_R8;
410 break;
411 case 2:
412 format.channelFormat = XGL_CH_FMT_R16;
413 break;
414 case 4:
415 format.channelFormat = XGL_CH_FMT_R32;
416 break;
417 case 8:
418 format.channelFormat = XGL_CH_FMT_R32G32;
419 break;
420 case 16:
421 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
422 break;
423 default:
424 assert(!"unsupported image format for raw blit op");
425 format.channelFormat = XGL_CH_FMT_UNDEFINED;
426 format.numericFormat = XGL_NUM_FMT_UNDEFINED;
427 break;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800428 }
429
430 return format;
431}
432
Chia-I Wu714df452015-01-01 07:55:04 +0800433ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800434 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800435 XGL_BUFFER srcBuffer,
436 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800437 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800438 const XGL_BUFFER_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800439{
440 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800441 struct intel_buf *src = intel_buf(srcBuffer);
442 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800443 struct intel_cmd_meta meta;
444 XGL_FORMAT format;
445 XGL_UINT i;
446
447 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800448 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800449
Chia-I Wuc14d1562014-10-17 09:49:22 +0800450 meta.height = 1;
451 meta.samples = 1;
452
453 format.channelFormat = XGL_CH_FMT_UNDEFINED;
454 format.numericFormat = XGL_NUM_FMT_UINT;
455
456 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800457 const XGL_BUFFER_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800458 XGL_CHANNEL_FORMAT ch;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800459
Chia-I Wuf3a27252014-11-24 15:27:01 +0800460 meta.src.x = region->srcOffset;
461 meta.dst.x = region->destOffset;
462 meta.width = region->copySize;
463
464 if (cmd_meta_mem_dword_aligned(cmd, region->srcOffset,
465 region->destOffset, region->copySize)) {
466 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
467 meta.src.x /= 4;
468 meta.dst.x /= 4;
469 meta.width /= 4;
470
471 /*
472 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to
473 * be 16
474 */
475 ch = XGL_CH_FMT_R32G32B32A32;
476 } else {
477 if (cmd_gen(cmd) == INTEL_GEN(6)) {
478 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
479 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
Chia-I Wu714df452015-01-01 07:55:04 +0800480 "unaligned xglCmdCopyBuffer unsupported");
Chia-I Wuf3a27252014-11-24 15:27:01 +0800481 cmd->result = XGL_ERROR_UNKNOWN;
482 continue;
483 }
484
485 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM_UNALIGNED;
486
487 /*
488 * INTEL_DEV_META_VS_COPY_MEM_UNALIGNED is untyped but expects the
489 * stride to be 4
490 */
491 ch = XGL_CH_FMT_R8G8B8A8;
492 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800493
494 if (format.channelFormat != ch) {
495 format.channelFormat = ch;
496
Chia-I Wu714df452015-01-01 07:55:04 +0800497 cmd_meta_set_src_for_buf(cmd, src, format, &meta);
498 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800499 }
500
Chia-I Wuc14d1562014-10-17 09:49:22 +0800501 cmd_draw_meta(cmd, &meta);
502 }
503}
504
Chia-I Wu96177272015-01-03 15:27:41 +0800505ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800506 XGL_CMD_BUFFER cmdBuffer,
507 XGL_IMAGE srcImage,
508 XGL_IMAGE destImage,
509 XGL_UINT regionCount,
510 const XGL_IMAGE_COPY* pRegions)
511{
512 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
513 struct intel_img *src = intel_img(srcImage);
514 struct intel_img *dst = intel_img(destImage);
515 struct intel_cmd_meta meta;
516 XGL_FORMAT raw_format;
517 bool raw_copy;
518 XGL_UINT i;
519
520 if (src->type != dst->type) {
521 cmd->result = XGL_ERROR_UNKNOWN;
522 return;
523 }
524
525 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
526 raw_copy = true;
527 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
528 } else if (icd_format_is_compressed(src->layout.format) ||
529 icd_format_is_compressed(dst->layout.format)) {
530 cmd->result = XGL_ERROR_UNKNOWN;
531 return;
532 }
533
534 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800535 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800536
537 cmd_meta_set_src_for_img(cmd, src,
538 (raw_copy) ? raw_format : src->layout.format,
539 XGL_IMAGE_ASPECT_COLOR, &meta);
540
541 meta.samples = dst->samples;
542
543 for (i = 0; i < regionCount; i++) {
544 const XGL_IMAGE_COPY *region = &pRegions[i];
545 XGL_UINT j;
546
547 meta.shader_id = get_shader_id(cmd->dev, src,
548 (region->extent.depth > 1));
549
550 meta.src.lod = region->srcSubresource.mipLevel;
551 meta.src.layer = region->srcSubresource.arraySlice +
552 region->srcOffset.z;
553 meta.src.x = region->srcOffset.x;
554 meta.src.y = region->srcOffset.y;
555
556 meta.dst.lod = region->destSubresource.mipLevel;
557 meta.dst.layer = region->destSubresource.arraySlice +
558 region->destOffset.z;
559 meta.dst.x = region->destOffset.x;
560 meta.dst.y = region->destOffset.y;
561
562 meta.width = region->extent.width;
563 meta.height = region->extent.height;
564
565 for (j = 0; j < region->extent.depth; j++) {
566 cmd_meta_set_dst_for_img(cmd, dst,
567 (raw_copy) ? raw_format : dst->layout.format,
568 meta.dst.lod, meta.dst.layer, &meta);
569
570 cmd_draw_meta(cmd, &meta);
571
572 meta.src.layer++;
573 meta.dst.layer++;
574 }
575 }
576}
577
Chia-I Wu714df452015-01-01 07:55:04 +0800578ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyBufferToImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800579 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800580 XGL_BUFFER srcBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800581 XGL_IMAGE destImage,
582 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800583 const XGL_BUFFER_IMAGE_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800584{
585 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800586 struct intel_buf *buf = intel_buf(srcBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800587 struct intel_img *img = intel_img(destImage);
588 struct intel_cmd_meta meta;
589 XGL_FORMAT format;
590 XGL_UINT i;
591
592 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800593 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800594
595 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
596 meta.samples = img->samples;
597
598 format = cmd_meta_img_raw_format(cmd, img->layout.format);
Chia-I Wu714df452015-01-01 07:55:04 +0800599 cmd_meta_set_src_for_buf(cmd, buf, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800600
601 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800602 const XGL_BUFFER_IMAGE_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800603 XGL_UINT j;
604
Chia-I Wu714df452015-01-01 07:55:04 +0800605 meta.src.x = region->bufferOffset / icd_format_get_size(format);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800606
607 meta.dst.lod = region->imageSubresource.mipLevel;
608 meta.dst.layer = region->imageSubresource.arraySlice +
609 region->imageOffset.z;
610 meta.dst.x = region->imageOffset.x;
611 meta.dst.y = region->imageOffset.y;
612
613 meta.width = region->imageExtent.width;
614 meta.height = region->imageExtent.height;
615
616 for (j = 0; j < region->imageExtent.depth; j++) {
617 cmd_meta_set_dst_for_img(cmd, img, format,
618 meta.dst.lod, meta.dst.layer, &meta);
619
620 cmd_draw_meta(cmd, &meta);
621
622 meta.src.x += meta.width * meta.height;
623 meta.dst.layer++;
624 }
625 }
626}
627
Chia-I Wu714df452015-01-01 07:55:04 +0800628ICD_EXPORT XGL_VOID XGLAPI xglCmdCopyImageToBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800629 XGL_CMD_BUFFER cmdBuffer,
630 XGL_IMAGE srcImage,
Chia-I Wu714df452015-01-01 07:55:04 +0800631 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800632 XGL_UINT regionCount,
Chia-I Wu714df452015-01-01 07:55:04 +0800633 const XGL_BUFFER_IMAGE_COPY* pRegions)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800634{
635 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
636 struct intel_img *img = intel_img(srcImage);
Chia-I Wu714df452015-01-01 07:55:04 +0800637 struct intel_buf *buf = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800638 struct intel_cmd_meta meta;
Chia-I Wu714df452015-01-01 07:55:04 +0800639 XGL_FORMAT img_format, buf_format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800640 XGL_UINT i;
641
642 memset(&meta, 0, sizeof(meta));
Chia-I Wua44b6482014-12-20 14:58:01 +0800643 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800644
Chia-I Wua44b6482014-12-20 14:58:01 +0800645 img_format = cmd_meta_img_raw_format(cmd, img->layout.format);
Chia-I Wu714df452015-01-01 07:55:04 +0800646 buf_format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800647
Chia-I Wu714df452015-01-01 07:55:04 +0800648 /* buf_format is ignored by hw, but we derive stride from it */
Chia-I Wua44b6482014-12-20 14:58:01 +0800649 switch (img_format.channelFormat) {
650 case XGL_CH_FMT_R8:
651 meta.shader_id = INTEL_DEV_META_VS_COPY_R8_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800652 buf_format.channelFormat = XGL_CH_FMT_R8G8B8A8;
Chia-I Wua44b6482014-12-20 14:58:01 +0800653 break;
654 case XGL_CH_FMT_R16:
655 meta.shader_id = INTEL_DEV_META_VS_COPY_R16_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800656 buf_format.channelFormat = XGL_CH_FMT_R8G8B8A8;
Chia-I Wua44b6482014-12-20 14:58:01 +0800657 break;
658 case XGL_CH_FMT_R32:
659 meta.shader_id = INTEL_DEV_META_VS_COPY_R32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800660 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800661 break;
662 case XGL_CH_FMT_R32G32:
663 meta.shader_id = INTEL_DEV_META_VS_COPY_R32G32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800664 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800665 break;
666 case XGL_CH_FMT_R32G32B32A32:
667 meta.shader_id = INTEL_DEV_META_VS_COPY_R32G32B32A32_TO_MEM;
Chia-I Wu714df452015-01-01 07:55:04 +0800668 buf_format.channelFormat = XGL_CH_FMT_R32G32B32A32;
Chia-I Wua44b6482014-12-20 14:58:01 +0800669 break;
670 default:
671 break;
672 }
673
674 if (img_format.channelFormat == XGL_CH_FMT_UNDEFINED ||
675 (cmd_gen(cmd) == INTEL_GEN(6) &&
676 icd_format_get_size(img_format) < 4)) {
677 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
678 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
Chia-I Wu714df452015-01-01 07:55:04 +0800679 "xglCmdCopyImageToBuffer with bpp %d unsupported",
Chia-I Wua44b6482014-12-20 14:58:01 +0800680 icd_format_get_size(img->layout.format));
681 cmd->result = XGL_ERROR_UNKNOWN;
682 return;
683 }
684
685 cmd_meta_set_src_for_img(cmd, img, img_format,
686 XGL_IMAGE_ASPECT_COLOR, &meta);
Chia-I Wu714df452015-01-01 07:55:04 +0800687 cmd_meta_set_dst_for_buf(cmd, buf, buf_format, &meta);
Chia-I Wua44b6482014-12-20 14:58:01 +0800688
Chia-I Wuc14d1562014-10-17 09:49:22 +0800689 meta.samples = 1;
690
691 for (i = 0; i < regionCount; i++) {
Chia-I Wu714df452015-01-01 07:55:04 +0800692 const XGL_BUFFER_IMAGE_COPY *region = &pRegions[i];
Chia-I Wuc14d1562014-10-17 09:49:22 +0800693 XGL_UINT j;
694
Chia-I Wuc14d1562014-10-17 09:49:22 +0800695 meta.src.lod = region->imageSubresource.mipLevel;
696 meta.src.layer = region->imageSubresource.arraySlice +
697 region->imageOffset.z;
698 meta.src.x = region->imageOffset.x;
699 meta.src.y = region->imageOffset.y;
700
Chia-I Wu714df452015-01-01 07:55:04 +0800701 meta.dst.x = region->bufferOffset / icd_format_get_size(img_format);
Chia-I Wua44b6482014-12-20 14:58:01 +0800702 meta.width = region->imageExtent.width;
703 meta.height = region->imageExtent.height;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800704
705 for (j = 0; j < region->imageExtent.depth; j++) {
706 cmd_draw_meta(cmd, &meta);
707
708 meta.src.layer++;
Chia-I Wua44b6482014-12-20 14:58:01 +0800709 meta.dst.x += meta.width * meta.height;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800710 }
711 }
712}
713
Chia-I Wu96177272015-01-03 15:27:41 +0800714ICD_EXPORT XGL_VOID XGLAPI xglCmdCloneImageData(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800715 XGL_CMD_BUFFER cmdBuffer,
716 XGL_IMAGE srcImage,
717 XGL_IMAGE_STATE srcImageState,
718 XGL_IMAGE destImage,
719 XGL_IMAGE_STATE destImageState)
720{
Chia-I Wud788fc62014-12-22 14:24:11 +0800721 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
722 struct intel_img *src = intel_img(srcImage);
723 struct intel_img *dst = intel_img(destImage);
Chia-I Wu714df452015-01-01 07:55:04 +0800724 struct intel_buf *src_buf, *dst_buf;
725 XGL_BUFFER_CREATE_INFO buf_info;
726 XGL_BUFFER_COPY buf_region;
727 XGL_RESULT res;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800728
Chia-I Wu714df452015-01-01 07:55:04 +0800729 memset(&buf_info, 0, sizeof(buf_info));
730 buf_info.sType = XGL_STRUCTURE_TYPE_BUFFER_CREATE_INFO;
731 buf_info.size = src->obj.mem->size;
732
733 memset(&buf_region, 0, sizeof(buf_region));
734 buf_region.copySize = src->obj.mem->size;
735
736 res = intel_buf_create(cmd->dev, &buf_info, &src_buf);
737 if (res != XGL_SUCCESS) {
738 cmd->result = res;
739 return;
740 }
741
742 res = intel_buf_create(cmd->dev, &buf_info, &dst_buf);
743 if (res != XGL_SUCCESS) {
744 intel_buf_destroy(src_buf);
745 cmd->result = res;
746 return;
747 }
748
749 intel_obj_bind_mem(&src_buf->obj, src->obj.mem, 0);
750 intel_obj_bind_mem(&dst_buf->obj, dst->obj.mem, 0);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800751
Chia-I Wud788fc62014-12-22 14:24:11 +0800752 cmd_batch_flush(cmd, GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
Chia-I Wu714df452015-01-01 07:55:04 +0800753 xglCmdCopyBuffer(cmdBuffer, (XGL_BUFFER) src_buf,
754 (XGL_BUFFER) dst_buf, 1, &buf_region);
755
756 intel_buf_destroy(src_buf);
757 intel_buf_destroy(dst_buf);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800758}
759
Chia-I Wu714df452015-01-01 07:55:04 +0800760ICD_EXPORT XGL_VOID XGLAPI xglCmdUpdateBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800761 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800762 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800763 XGL_GPU_SIZE destOffset,
764 XGL_GPU_SIZE dataSize,
765 const XGL_UINT32* pData)
766{
767 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800768 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800769 struct intel_cmd_meta meta;
770 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800771 uint32_t *ptr;
772 uint32_t offset;
773
Chia-I Wuf3a27252014-11-24 15:27:01 +0800774 /* must be 4-byte aligned */
775 if ((destOffset | dataSize) & 3) {
776 cmd->result = XGL_ERROR_UNKNOWN;
777 return;
778 }
779
Chia-I Wuc14d1562014-10-17 09:49:22 +0800780 /* write to dynamic state writer first */
781 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
782 (dataSize + 3) / 4, &ptr);
783 memcpy(ptr, pData, dataSize);
784
Chia-I Wuc14d1562014-10-17 09:49:22 +0800785 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800786 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800787
Chia-I Wuf3a27252014-11-24 15:27:01 +0800788 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
789
790 meta.src.x = offset / 4;
791 meta.dst.x = destOffset / 4;
792 meta.width = dataSize / 4;
793 meta.height = 1;
794 meta.samples = 1;
795
796 /*
797 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to be 16
798 */
799 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
800 format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800801
802 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
803 offset + dataSize, format, &meta);
Chia-I Wu714df452015-01-01 07:55:04 +0800804 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800805
Chia-I Wuc14d1562014-10-17 09:49:22 +0800806 cmd_draw_meta(cmd, &meta);
807}
808
Chia-I Wu714df452015-01-01 07:55:04 +0800809ICD_EXPORT XGL_VOID XGLAPI xglCmdFillBuffer(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800810 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +0800811 XGL_BUFFER destBuffer,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800812 XGL_GPU_SIZE destOffset,
813 XGL_GPU_SIZE fillSize,
814 XGL_UINT32 data)
815{
816 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +0800817 struct intel_buf *dst = intel_buf(destBuffer);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800818 struct intel_cmd_meta meta;
819 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800820
821 /* must be 4-byte aligned */
822 if ((destOffset | fillSize) & 3) {
823 cmd->result = XGL_ERROR_UNKNOWN;
824 return;
825 }
826
827 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800828 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800829
Chia-I Wuf3a27252014-11-24 15:27:01 +0800830 meta.shader_id = INTEL_DEV_META_VS_FILL_MEM;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800831
832 meta.clear_val[0] = data;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800833
Chia-I Wuf3a27252014-11-24 15:27:01 +0800834 meta.dst.x = destOffset / 4;
835 meta.width = fillSize / 4;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800836 meta.height = 1;
837 meta.samples = 1;
838
Chia-I Wuf3a27252014-11-24 15:27:01 +0800839 /*
840 * INTEL_DEV_META_VS_FILL_MEM is untyped but expects the stride to be 16
841 */
842 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
843 format.numericFormat = XGL_NUM_FMT_UINT;
844
Chia-I Wu714df452015-01-01 07:55:04 +0800845 cmd_meta_set_dst_for_buf(cmd, dst, format, &meta);
Chia-I Wuf3a27252014-11-24 15:27:01 +0800846
Chia-I Wuc14d1562014-10-17 09:49:22 +0800847 cmd_draw_meta(cmd, &meta);
848}
849
850static void cmd_meta_clear_image(struct intel_cmd *cmd,
851 struct intel_img *img,
852 XGL_FORMAT format,
853 struct intel_cmd_meta *meta,
854 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
855{
856 XGL_UINT mip_levels, array_size;
857 XGL_UINT i, j;
858
859 if (range->baseMipLevel >= img->mip_levels ||
860 range->baseArraySlice >= img->array_size)
861 return;
862
863 mip_levels = img->mip_levels - range->baseMipLevel;
864 if (mip_levels > range->mipLevels)
865 mip_levels = range->mipLevels;
866
867 array_size = img->array_size - range->baseArraySlice;
868 if (array_size > range->arraySize)
869 array_size = range->arraySize;
870
Chia-I Wuc14d1562014-10-17 09:49:22 +0800871 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800872 meta->dst.lod = range->baseMipLevel + i;
873 meta->dst.layer = range->baseArraySlice;
874
Chia-I Wuc14d1562014-10-17 09:49:22 +0800875 meta->width = u_minify(img->layout.width0, meta->dst.lod);
876 meta->height = u_minify(img->layout.height0, meta->dst.lod);
877
878 for (j = 0; j < array_size; j++) {
879 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
880 cmd_meta_set_dst_for_img(cmd, img, format,
881 meta->dst.lod, meta->dst.layer, meta);
882
883 cmd_draw_meta(cmd, meta);
884 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800885 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800886 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800887 cmd_meta_set_ds_state(cmd, range->aspect,
888 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800889
890 cmd_draw_meta(cmd, meta);
891
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800892 intel_ds_view_destroy(meta->ds.view);
893 intel_ds_state_destroy(meta->ds.state);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800894 }
895
896 meta->dst.layer++;
897 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800898 }
899}
900
Chia-I Wu96177272015-01-03 15:27:41 +0800901ICD_EXPORT XGL_VOID XGLAPI xglCmdClearColorImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800902 XGL_CMD_BUFFER cmdBuffer,
903 XGL_IMAGE image,
904 const XGL_FLOAT color[4],
905 XGL_UINT rangeCount,
906 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
907{
908 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
909 struct intel_img *img = intel_img(image);
910 struct intel_cmd_meta meta;
911 XGL_UINT i;
912
913 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800914 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800915
916 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
917 meta.samples = img->samples;
918
919 meta.clear_val[0] = u_fui(color[0]);
920 meta.clear_val[1] = u_fui(color[1]);
921 meta.clear_val[2] = u_fui(color[2]);
922 meta.clear_val[3] = u_fui(color[3]);
923
924 for (i = 0; i < rangeCount; i++) {
925 cmd_meta_clear_image(cmd, img, img->layout.format,
926 &meta, &pRanges[i]);
927 }
928}
929
Chia-I Wu96177272015-01-03 15:27:41 +0800930ICD_EXPORT XGL_VOID XGLAPI xglCmdClearColorImageRaw(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800931 XGL_CMD_BUFFER cmdBuffer,
932 XGL_IMAGE image,
933 const XGL_UINT32 color[4],
934 XGL_UINT rangeCount,
935 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
936{
937 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
938 struct intel_img *img = intel_img(image);
939 struct intel_cmd_meta meta;
940 XGL_FORMAT format;
941 XGL_UINT i;
942
943 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800944 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800945
946 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
947 meta.samples = img->samples;
948
Chia-I Wuffdde352014-12-20 15:12:16 +0800949 icd_format_get_raw_value(img->layout.format, color, meta.clear_val);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800950 format = cmd_meta_img_raw_format(cmd, img->layout.format);
951
952 for (i = 0; i < rangeCount; i++)
953 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
954}
955
Chia-I Wu96177272015-01-03 15:27:41 +0800956ICD_EXPORT XGL_VOID XGLAPI xglCmdClearDepthStencil(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800957 XGL_CMD_BUFFER cmdBuffer,
958 XGL_IMAGE image,
959 XGL_FLOAT depth,
960 XGL_UINT32 stencil,
961 XGL_UINT rangeCount,
962 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
963{
964 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
965 struct intel_img *img = intel_img(image);
966 struct intel_cmd_meta meta;
967 XGL_UINT i;
968
969 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800970 meta.mode = INTEL_CMD_META_DEPTH_STENCIL_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800971
972 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
973 meta.samples = img->samples;
974
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800975 meta.clear_val[0] = u_fui(depth);
976 meta.clear_val[1] = stencil;
977
Chia-I Wuc14d1562014-10-17 09:49:22 +0800978 for (i = 0; i < rangeCount; i++) {
979 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
980
Chia-I Wuc14d1562014-10-17 09:49:22 +0800981 cmd_meta_clear_image(cmd, img, img->layout.format,
982 &meta, range);
983 }
984}
985
Chia-I Wu96177272015-01-03 15:27:41 +0800986ICD_EXPORT XGL_VOID XGLAPI xglCmdResolveImage(
Chia-I Wuc14d1562014-10-17 09:49:22 +0800987 XGL_CMD_BUFFER cmdBuffer,
988 XGL_IMAGE srcImage,
989 XGL_IMAGE destImage,
990 XGL_UINT rectCount,
991 const XGL_IMAGE_RESOLVE* pRects)
992{
993 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
994 struct intel_img *src = intel_img(srcImage);
995 struct intel_img *dst = intel_img(destImage);
996 struct intel_cmd_meta meta;
997 XGL_FORMAT format;
998 XGL_UINT i;
999
1000 if (src->samples <= 1 || dst->samples > 1 ||
1001 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
1002 cmd->result = XGL_ERROR_UNKNOWN;
1003 return;
1004 }
1005
1006 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +08001007 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +08001008
1009 switch (src->samples) {
1010 case 2:
1011 default:
1012 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
1013 break;
1014 case 4:
1015 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
1016 break;
1017 case 8:
1018 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
1019 break;
1020 case 16:
1021 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
1022 break;
1023 }
1024
1025 meta.samples = 1;
1026
1027 format = cmd_meta_img_raw_format(cmd, src->layout.format);
1028 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
1029
1030 for (i = 0; i < rectCount; i++) {
1031 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
1032
1033 meta.src.lod = rect->srcSubresource.mipLevel;
1034 meta.src.layer = rect->srcSubresource.arraySlice;
1035 meta.src.x = rect->srcOffset.x;
1036 meta.src.y = rect->srcOffset.y;
1037
1038 meta.dst.lod = rect->destSubresource.mipLevel;
1039 meta.dst.layer = rect->destSubresource.arraySlice;
1040 meta.dst.x = rect->destOffset.x;
1041 meta.dst.y = rect->destOffset.y;
1042
1043 meta.width = rect->extent.width;
1044 meta.height = rect->extent.height;
1045
1046 cmd_meta_set_dst_for_img(cmd, dst, format,
1047 meta.dst.lod, meta.dst.layer, &meta);
1048
1049 cmd_draw_meta(cmd, &meta);
1050 }
1051}