blob: 3977a0daaee16e11bdbf9801dd02500404ae509b [file] [log] [blame]
Chia-I Wu82f50aa2014-08-05 10:43:03 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "dispatch_tables.h"
26#include "gpu.h"
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060027#include "dev.h"
Chia-I Wu82f50aa2014-08-05 10:43:03 +080028#include "obj.h"
29
30/**
31 * Return true if an (not so) arbitrary pointer casted to intel_base points to
32 * a valid intel_base. This assumes at least the first sizeof(void*) bytes of
33 * the address are accessible, and they does not happen to be our magic
34 * values.
35 */
36bool intel_base_is_valid(const struct intel_base *base)
37{
38 if (base->dispatch != &intel_normal_dispatch_table &&
39 base->dispatch != &intel_debug_dispatch_table)
40 return false;
41
42 return !intel_gpu_is_valid((const struct intel_gpu *) base);
43}
44
Chia-I Wu26f0bd02014-08-07 10:38:40 +080045XGL_RESULT intel_base_get_info(struct intel_base *base, int type,
46 XGL_SIZE *size, XGL_VOID *data)
47{
48 XGL_RESULT ret = XGL_SUCCESS;
49 XGL_SIZE s;
50
51 switch (type) {
52 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
53 s = sizeof(XGL_MEMORY_REQUIREMENTS);
54 memset(data, 0, s);
55 *size = s;
56 break;
57 default:
58 ret = XGL_ERROR_INVALID_VALUE;
59 break;
60 }
61
62 return ret;
63}
64
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080065static bool base_dbg_copy_create_info(struct intel_base_dbg *dbg,
66 const void *create_info)
67{
68 const union {
69 const void *ptr;
70 const struct {
71 XGL_STRUCTURE_TYPE struct_type;
72 XGL_VOID *next;
73 } *header;
74 } info = { .ptr = create_info };
75 XGL_SIZE shallow_copy = 0;
76
77 if (!create_info)
78 return true;
79
Chia-I Wub1076d72014-08-18 16:10:20 +080080 switch (dbg->type) {
81 case XGL_DBG_OBJECT_DEVICE:
82 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080083 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080084 case XGL_DBG_OBJECT_GPU_MEMORY:
85 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MEMORY_ALLOC_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080086 shallow_copy = sizeof(XGL_MEMORY_ALLOC_INFO);
87 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080088 case XGL_DBG_OBJECT_EVENT:
89 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_EVENT_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080090 shallow_copy = sizeof(XGL_EVENT_CREATE_INFO);
91 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080092 case XGL_DBG_OBJECT_FENCE:
93 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_FENCE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080094 shallow_copy = sizeof(XGL_FENCE_CREATE_INFO);
95 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080096 case XGL_DBG_OBJECT_QUERY_POOL:
97 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
Courtney Goeltzenleuchter850d12c2014-08-07 18:13:10 -060098 shallow_copy = sizeof(XGL_QUERY_POOL_CREATE_INFO);
99 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800100 case XGL_DBG_OBJECT_IMAGE:
101 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800102 shallow_copy = sizeof(XGL_IMAGE_CREATE_INFO);
103 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800104 case XGL_DBG_OBJECT_IMAGE_VIEW:
105 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800106 shallow_copy = sizeof(XGL_IMAGE_VIEW_CREATE_INFO);
107 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800108 case XGL_DBG_OBJECT_COLOR_TARGET_VIEW:
109 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800110 shallow_copy = sizeof(XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
111 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800112 case XGL_DBG_OBJECT_DEPTH_STENCIL_VIEW:
113 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800114 shallow_copy = sizeof(XGL_DEPTH_STENCIL_VIEW_CREATE_INFO);
115 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800116 case XGL_DBG_OBJECT_SAMPLER:
117 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
Chia-I Wu28b89962014-08-18 14:40:49 +0800118 shallow_copy = sizeof(XGL_SAMPLER_CREATE_INFO);
119 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800120 case XGL_DBG_OBJECT_DESCRIPTOR_SET:
121 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DESCRIPTOR_SET_CREATE_INFO);
Chia-I Wub8d04c82014-08-18 15:51:10 +0800122 shallow_copy = sizeof(XGL_DESCRIPTOR_SET_CREATE_INFO);
123 break;
Chia-I Wua5714e82014-08-11 15:33:42 +0800124 case XGL_DBG_OBJECT_VIEWPORT_STATE:
125 /* no struct header! */
126 shallow_copy = sizeof(XGL_VIEWPORT_STATE_CREATE_INFO);
127 break;
128 case XGL_DBG_OBJECT_RASTER_STATE:
129 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_RASTER_STATE_CREATE_INFO);
130 shallow_copy = sizeof(XGL_RASTER_STATE_CREATE_INFO);
131 break;
132 case XGL_DBG_OBJECT_MSAA_STATE:
133 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MSAA_STATE_CREATE_INFO);
134 shallow_copy = sizeof(XGL_MSAA_STATE_CREATE_INFO);
135 break;
136 case XGL_DBG_OBJECT_COLOR_BLEND_STATE:
137 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_BLEND_STATE_CREATE_INFO);
138 shallow_copy = sizeof(XGL_COLOR_BLEND_STATE_CREATE_INFO);
139 break;
140 case XGL_DBG_OBJECT_DEPTH_STENCIL_STATE:
141 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO);
142 shallow_copy = sizeof(XGL_DEPTH_STENCIL_STATE_CREATE_INFO);
143 break;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800144 default:
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600145 // log debug message regarding invalid struct_type?
146 intel_dev_log(dbg->dev, XGL_DBG_MSG_ERROR,
147 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
148 "Invalid Create Info type: 0x%x", info.header->struct_type);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800149 return false;
150 break;
151 }
152
153 if (shallow_copy) {
154 assert(!info.header->next);
155
156 dbg->create_info = icd_alloc(shallow_copy, 0, XGL_SYSTEM_ALLOC_DEBUG);
157 if (!dbg->create_info)
158 return false;
159
160 memcpy(dbg->create_info, create_info, shallow_copy);
Chia-I Wue2934f92014-08-16 13:17:22 +0800161 dbg->create_info_size = shallow_copy;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800162 } else if (info.header->struct_type ==
163 XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO) {
164 const XGL_DEVICE_CREATE_INFO *src = info.ptr;
165 XGL_DEVICE_CREATE_INFO *dst;
166 uint8_t *d;
167 XGL_SIZE size;
168 XGL_UINT i;
169
170 size = sizeof(*src);
Chia-I Wue2934f92014-08-16 13:17:22 +0800171 dbg->create_info_size = size;
172
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800173 size += sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
174 size += sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
175 for (i = 0; i < src->extensionCount; i++) {
176 size += 1 +
177 strlen((const char *) src->ppEnabledExtensionNames[i]);
178 }
179
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800180 dst = icd_alloc(size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800181 if (!dst)
182 return false;
183
184 memcpy(dst, src, sizeof(*src));
185
186 d = (uint8_t *) dst;
187 d += sizeof(*src);
188
189 size = sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
190 memcpy(d, src->pRequestedQueues, size);
191 dst->pRequestedQueues = (const XGL_DEVICE_QUEUE_CREATE_INFO *) d;
192 d += size;
193
194 size = sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
195 dst->ppEnabledExtensionNames = (const XGL_CHAR * const *) d;
196
197 for (i = 0; i < src->extensionCount; i++) {
198 const XGL_SIZE len =
199 strlen((const char *) src->ppEnabledExtensionNames[i]);
200
201 memcpy(d + size, src->ppEnabledExtensionNames[i], len + 1);
202 ((const XGL_CHAR **) d)[i] = (const XGL_CHAR *) (d + size);
203
204 size += len + 1;
205 }
206 }
207
208 return true;
209}
210
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800211/**
Chia-I Wubbf2c932014-08-07 12:20:08 +0800212 * Create an intel_base_dbg. When dbg_size is non-zero, a buffer of that
Chia-I Wu660caf82014-08-07 10:54:26 +0800213 * size is allocated and zeroed.
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800214 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600215struct intel_base_dbg *intel_base_dbg_create(struct intel_dev *dev,
216 XGL_DBG_OBJECT_TYPE type,
Chia-I Wu660caf82014-08-07 10:54:26 +0800217 const void *create_info,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800218 XGL_SIZE dbg_size)
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800219{
Chia-I Wu660caf82014-08-07 10:54:26 +0800220 struct intel_base_dbg *dbg;
221
Chia-I Wubbf2c932014-08-07 12:20:08 +0800222 if (!dbg_size)
223 dbg_size = sizeof(*dbg);
Chia-I Wu660caf82014-08-07 10:54:26 +0800224
Chia-I Wubbf2c932014-08-07 12:20:08 +0800225 assert(dbg_size >= sizeof(*dbg));
Chia-I Wu660caf82014-08-07 10:54:26 +0800226
Chia-I Wubbf2c932014-08-07 12:20:08 +0800227 dbg = icd_alloc(dbg_size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu660caf82014-08-07 10:54:26 +0800228 if (!dbg)
229 return NULL;
230
Chia-I Wubbf2c932014-08-07 12:20:08 +0800231 memset(dbg, 0, dbg_size);
Chia-I Wu660caf82014-08-07 10:54:26 +0800232
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800233 dbg->alloc_id = icd_get_allocator_id();
234 dbg->type = type;
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600235 dbg->dev = dev;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800236
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800237 if (!base_dbg_copy_create_info(dbg, create_info)) {
238 icd_free(dbg);
239 return NULL;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800240 }
241
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800242 return dbg;
243}
244
245void intel_base_dbg_destroy(struct intel_base_dbg *dbg)
246{
Chia-I Wu660caf82014-08-07 10:54:26 +0800247 if (dbg->tag)
248 icd_free(dbg->tag);
249
250 if (dbg->create_info)
251 icd_free(dbg->create_info);
252
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800253 icd_free(dbg);
254}
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800255
Chia-I Wubbf2c932014-08-07 12:20:08 +0800256/**
257 * Create an intel_base. obj_size and dbg_size specify the real sizes of the
258 * object and the debug metadata. Memories are zeroed.
259 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600260struct intel_base *intel_base_create(struct intel_dev *dev,
261 XGL_SIZE obj_size, bool debug,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800262 XGL_DBG_OBJECT_TYPE type,
263 const void *create_info,
264 XGL_SIZE dbg_size)
265{
266 struct intel_base *base;
267
268 if (!obj_size)
269 obj_size = sizeof(*base);
270
271 assert(obj_size >= sizeof(*base));
272
273 base = icd_alloc(obj_size, 0, XGL_SYSTEM_ALLOC_API_OBJECT);
274 if (!base)
275 return NULL;
276
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600277 if (dev == NULL) {
278 /*
279 * dev is NULL when we are creating the base device object
280 * Set dev now so that debug setup happens correctly
281 */
282 dev = (struct intel_dev *) base;
283 }
284
Chia-I Wubbf2c932014-08-07 12:20:08 +0800285 memset(base, 0, obj_size);
286
287 if (debug) {
288 base->dispatch = &intel_debug_dispatch_table;
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600289 base->dbg = intel_base_dbg_create(dev, type, create_info, dbg_size);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800290 if (!base->dbg) {
291 icd_free(base);
292 return NULL;
293 }
294 }
295 else {
296 base->dispatch = &intel_normal_dispatch_table;
297 }
298 base->get_info = intel_base_get_info;
299
300 return base;
301}
302
303void intel_base_destroy(struct intel_base *base)
304{
305 if (base->dbg)
306 intel_base_dbg_destroy(base->dbg);
307 icd_free(base);
308}
309
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800310XGL_RESULT XGLAPI intelDestroyObject(
311 XGL_OBJECT object)
312{
313 struct intel_obj *obj = intel_obj(object);
314
315 obj->destroy(obj);
316
317 return XGL_SUCCESS;
318}
319
320XGL_RESULT XGLAPI intelGetObjectInfo(
321 XGL_BASE_OBJECT object,
322 XGL_OBJECT_INFO_TYPE infoType,
323 XGL_SIZE* pDataSize,
324 XGL_VOID* pData)
325{
326 struct intel_base *base = intel_base(object);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800327
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800328 return base->get_info(base, infoType, pDataSize, pData);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800329}
330
331XGL_RESULT XGLAPI intelBindObjectMemory(
332 XGL_OBJECT object,
333 XGL_GPU_MEMORY mem,
334 XGL_GPU_SIZE offset)
335{
336 struct intel_obj *obj = intel_obj(object);
337
338 obj->mem = mem;
339 obj->offset = offset;
340
341 return XGL_SUCCESS;
342}
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800343
344XGL_RESULT XGLAPI intelDbgSetObjectTag(
345 XGL_BASE_OBJECT object,
346 XGL_SIZE tagSize,
347 const XGL_VOID* pTag)
348{
349 struct intel_base *base = intel_base(object);
350 struct intel_base_dbg *dbg = base->dbg;
351 void *tag;
352
353 if (!dbg)
354 return XGL_SUCCESS;
355
356 tag = icd_alloc(tagSize, 0, XGL_SYSTEM_ALLOC_DEBUG);
357 if (!tag)
358 return XGL_ERROR_OUT_OF_MEMORY;
359
360 memcpy(tag, pTag, tagSize);
361
362 if (dbg->tag)
363 icd_free(dbg->tag);
364
365 dbg->tag = tag;
366 dbg->tag_size = tagSize;
367
368 return XGL_SUCCESS;
369}