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Chia-I Wue54854a2014-08-05 10:23:50 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef DEV_H
26#define DEV_H
27
Chia-I Wue09b5362014-08-07 09:25:14 +080028#include "intel.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080029#include "gpu.h"
Chia-I Wua2161db2014-08-15 16:34:34 +080030#include "obj.h"
Chia-I Wue54854a2014-08-05 10:23:50 +080031
Chia-I Wue54854a2014-08-05 10:23:50 +080032struct intel_queue;
33struct intel_winsys;
34
35struct intel_dev_dbg_msg_filter {
36 XGL_INT msg_code;
37 XGL_DBG_MSG_FILTER filter;
38 bool triggered;
39
40 struct intel_dev_dbg_msg_filter *next;
41};
42
43struct intel_dev_dbg {
44 struct intel_base_dbg base;
45
46 struct intel_dev_dbg_msg_filter *filters;
47};
48
49struct intel_dev {
50 struct intel_base base;
51
52 struct intel_gpu *gpu;
53 struct intel_winsys *winsys;
54 struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT];
55};
56
Chia-I Wue54854a2014-08-05 10:23:50 +080057static inline struct intel_dev *intel_dev(XGL_DEVICE dev)
58{
59 return (struct intel_dev *) dev;
60}
61
62static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev)
63{
64 return (struct intel_dev_dbg *) dev->base.dbg;
65}
66
Chia-I Wue54854a2014-08-05 10:23:50 +080067XGL_RESULT intel_dev_create(struct intel_gpu *gpu,
68 const XGL_DEVICE_CREATE_INFO *info,
69 struct intel_dev **dev_ret);
70void intel_dev_destroy(struct intel_dev *dev);
71
72void intel_dev_get_heap_props(const struct intel_dev *dev,
73 XGL_MEMORY_HEAP_PROPERTIES *props);
74
75XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev,
76 XGL_INT msg_code,
77 XGL_DBG_MSG_FILTER filter);
78
79void intel_dev_remove_msg_filter(struct intel_dev *dev,
80 XGL_INT msg_code);
81
Chia-I Wu82d3d8b2014-08-09 13:07:44 +080082void intel_dev_log(struct intel_dev *dev,
83 XGL_DBG_MSG_TYPE msg_type,
84 XGL_VALIDATION_LEVEL validation_level,
85 XGL_BASE_OBJECT src_object,
86 XGL_SIZE location,
87 XGL_INT msg_code,
88 const char *format, ...);
89
Chia-I Wua207aba2014-08-05 15:13:37 +080090XGL_RESULT XGLAPI intelCreateDevice(
91 XGL_PHYSICAL_GPU gpu,
92 const XGL_DEVICE_CREATE_INFO* pCreateInfo,
93 XGL_DEVICE* pDevice);
94
95XGL_RESULT XGLAPI intelDestroyDevice(
96 XGL_DEVICE device);
97
98XGL_RESULT XGLAPI intelGetMemoryHeapCount(
99 XGL_DEVICE device,
100 XGL_UINT* pCount);
101
102XGL_RESULT XGLAPI intelGetMemoryHeapInfo(
103 XGL_DEVICE device,
104 XGL_UINT heapId,
105 XGL_MEMORY_HEAP_INFO_TYPE infoType,
106 XGL_SIZE* pDataSize,
107 XGL_VOID* pData);
108
Chia-I Wu49dbee82014-08-06 12:48:47 +0800109XGL_RESULT XGLAPI intelGetDeviceQueue(
110 XGL_DEVICE device,
111 XGL_QUEUE_TYPE queueType,
112 XGL_UINT queueIndex,
113 XGL_QUEUE* pQueue);
114
Chia-I Wu49dbee82014-08-06 12:48:47 +0800115XGL_RESULT XGLAPI intelDeviceWaitIdle(
116 XGL_DEVICE device);
117
Chia-I Wue54854a2014-08-05 10:23:50 +0800118#endif /* DEV_H */