blob: a5a2712db36e60af7aeb59644ace506884804273 [file] [log] [blame]
Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu9f039862014-08-20 15:39:56 +080025#include "genhw/genhw.h"
Chia-I Wub2755562014-08-20 13:38:52 +080026#include "dset.h"
Chia-I Wu7fae4e32014-08-21 11:39:44 +080027#include "img.h"
Chia-I Wub2755562014-08-20 13:38:52 +080028#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080029#include "pipeline.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "state.h"
31#include "view.h"
32#include "cmd_priv.h"
33
Chia-I Wu59c097e2014-08-21 10:51:07 +080034static void gen6_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080035 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080036 uint32_t vertex_count,
37 uint32_t vertex_start,
38 uint32_t instance_count,
39 uint32_t instance_start,
40 uint32_t vertex_base)
41{
42 const uint8_t cmd_len = 6;
43 uint32_t dw0;
44
45 CMD_ASSERT(cmd, 6, 6);
46
Chia-I Wub0b9f692014-08-21 11:33:29 +080047 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) |
Chia-I Wu254db422014-08-21 11:54:29 +080048 prim_type << GEN6_3DPRIM_DW0_TYPE__SHIFT |
Chia-I Wu59c097e2014-08-21 10:51:07 +080049 (cmd_len - 2);
50
51 if (indexed)
52 dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
53
Chia-I Wue24c3292014-08-21 14:05:23 +080054 cmd_batch_reserve(cmd, cmd_len);
55 cmd_batch_write(cmd, dw0);
56 cmd_batch_write(cmd, vertex_count);
57 cmd_batch_write(cmd, vertex_start);
58 cmd_batch_write(cmd, instance_count);
59 cmd_batch_write(cmd, instance_start);
60 cmd_batch_write(cmd, vertex_base);
Chia-I Wu59c097e2014-08-21 10:51:07 +080061}
62
63static void gen7_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080064 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080065 uint32_t vertex_count,
66 uint32_t vertex_start,
67 uint32_t instance_count,
68 uint32_t instance_start,
69 uint32_t vertex_base)
70{
71 const uint8_t cmd_len = 7;
72 uint32_t dw0, dw1;
73
74 CMD_ASSERT(cmd, 7, 7.5);
75
Chia-I Wub0b9f692014-08-21 11:33:29 +080076 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) | (cmd_len - 2);
Chia-I Wu254db422014-08-21 11:54:29 +080077 dw1 = prim_type << GEN7_3DPRIM_DW1_TYPE__SHIFT;
Chia-I Wu59c097e2014-08-21 10:51:07 +080078
79 if (indexed)
80 dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
81
Chia-I Wue24c3292014-08-21 14:05:23 +080082 cmd_batch_reserve(cmd, cmd_len);
83 cmd_batch_write(cmd, dw0);
84 cmd_batch_write(cmd, dw1);
85 cmd_batch_write(cmd, vertex_count);
86 cmd_batch_write(cmd, vertex_start);
87 cmd_batch_write(cmd, instance_count);
88 cmd_batch_write(cmd, instance_start);
89 cmd_batch_write(cmd, vertex_base);
Chia-I Wu59c097e2014-08-21 10:51:07 +080090}
91
Chia-I Wu254db422014-08-21 11:54:29 +080092static bool gen6_can_primitive_restart(const struct intel_cmd *cmd)
93{
94 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
95 bool supported;
96
97 CMD_ASSERT(cmd, 6, 7.5);
98
99 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
100 return (p->prim_type != GEN6_3DPRIM_RECTLIST);
101
102 switch (p->prim_type) {
103 case GEN6_3DPRIM_POINTLIST:
104 case GEN6_3DPRIM_LINELIST:
105 case GEN6_3DPRIM_LINESTRIP:
106 case GEN6_3DPRIM_TRILIST:
107 case GEN6_3DPRIM_TRISTRIP:
108 supported = true;
109 break;
110 default:
111 supported = false;
112 break;
113 }
114
115 if (!supported)
116 return false;
117
118 switch (cmd->bind.index.type) {
119 case XGL_INDEX_8:
120 supported = (p->primitive_restart_index != 0xffu);
121 break;
122 case XGL_INDEX_16:
123 supported = (p->primitive_restart_index != 0xffffu);
124 break;
125 case XGL_INDEX_32:
126 supported = (p->primitive_restart_index != 0xffffffffu);
127 break;
128 default:
129 supported = false;
130 break;
131 }
132
133 return supported;
134}
135
Chia-I Wu59c097e2014-08-21 10:51:07 +0800136static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
Chia-I Wu958d1b72014-08-21 11:28:11 +0800137 const struct intel_mem *mem,
Chia-I Wu59c097e2014-08-21 10:51:07 +0800138 XGL_GPU_SIZE offset,
139 XGL_INDEX_TYPE type,
140 bool enable_cut_index)
141{
142 const uint8_t cmd_len = 3;
143 uint32_t dw0, end_offset;
144 unsigned offset_align;
145
146 CMD_ASSERT(cmd, 6, 7.5);
147
Chia-I Wub0b9f692014-08-21 11:33:29 +0800148 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800149
150 /* the bit is moved to 3DSTATE_VF */
151 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
152 assert(!enable_cut_index);
153 if (enable_cut_index)
154 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
155
156 switch (type) {
157 case XGL_INDEX_8:
158 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
159 offset_align = 1;
160 break;
161 case XGL_INDEX_16:
162 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
163 offset_align = 2;
164 break;
165 case XGL_INDEX_32:
166 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
167 offset_align = 4;
168 break;
169 default:
170 cmd->result = XGL_ERROR_INVALID_VALUE;
171 return;
172 break;
173 }
174
175 if (offset % offset_align) {
176 cmd->result = XGL_ERROR_INVALID_VALUE;
177 return;
178 }
179
180 /* aligned and inclusive */
181 end_offset = mem->size - (mem->size % offset_align) - 1;
182
Chia-I Wue24c3292014-08-21 14:05:23 +0800183 cmd_batch_reserve(cmd, cmd_len);
184 cmd_batch_write(cmd, dw0);
185 cmd_batch_reloc(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
186 cmd_batch_reloc(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800187}
188
Chia-I Wu254db422014-08-21 11:54:29 +0800189static inline void
190gen75_3DSTATE_VF(struct intel_cmd *cmd,
191 bool enable_cut_index,
192 uint32_t cut_index)
193{
194 const uint8_t cmd_len = 2;
195 uint32_t dw0;
196
197 CMD_ASSERT(cmd, 7.5, 7.5);
198
199 dw0 = GEN_RENDER_CMD(3D, GEN75, 3DSTATE_VF) | (cmd_len - 2);
200 if (enable_cut_index)
201 dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
202
Chia-I Wue24c3292014-08-21 14:05:23 +0800203 cmd_batch_reserve(cmd, cmd_len);
204 cmd_batch_write(cmd, dw0);
205 cmd_batch_write(cmd, cut_index);
Chia-I Wu254db422014-08-21 11:54:29 +0800206}
207
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800208static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd,
209 const struct intel_ds_view *view)
210{
211 const uint8_t cmd_len = 7;
212 uint32_t dw0;
213
214 CMD_ASSERT(cmd, 6, 7.5);
215
216 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
217 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_DEPTH_BUFFER) :
218 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_DEPTH_BUFFER);
219 dw0 |= (cmd_len - 2);
220
Chia-I Wue24c3292014-08-21 14:05:23 +0800221 cmd_batch_reserve(cmd, cmd_len);
222 cmd_batch_write(cmd, dw0);
223 cmd_batch_write(cmd, view->cmd[0]);
224 cmd_batch_reloc(cmd, view->cmd[1], view->img->obj.mem,
225 INTEL_DOMAIN_RENDER,
226 INTEL_DOMAIN_RENDER);
227 cmd_batch_write(cmd, view->cmd[2]);
228 cmd_batch_write(cmd, view->cmd[3]);
229 cmd_batch_write(cmd, view->cmd[4]);
230 cmd_batch_write(cmd, view->cmd[5]);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800231}
232
233static void gen6_3DSTATE_STENCIL_BUFFER(struct intel_cmd *cmd,
234 const struct intel_ds_view *view)
235{
236 const uint8_t cmd_len = 3;
237 uint32_t dw0;
238
239 CMD_ASSERT(cmd, 6, 7.5);
240
241 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
242 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_STENCIL_BUFFER) :
243 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_STENCIL_BUFFER);
244 dw0 |= (cmd_len - 2);
245
Chia-I Wue24c3292014-08-21 14:05:23 +0800246 cmd_batch_reserve(cmd, cmd_len);
247 cmd_batch_write(cmd, dw0);
248 cmd_batch_write(cmd, view->cmd[6]);
249 cmd_batch_reloc(cmd, view->cmd[7], view->img->obj.mem,
250 INTEL_DOMAIN_RENDER,
251 INTEL_DOMAIN_RENDER);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800252}
253
254static void gen6_3DSTATE_HIER_DEPTH_BUFFER(struct intel_cmd *cmd,
255 const struct intel_ds_view *view)
256{
257 const uint8_t cmd_len = 3;
258 uint32_t dw0;
259
260 CMD_ASSERT(cmd, 6, 7.5);
261
262 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
263 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_HIER_DEPTH_BUFFER) :
264 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_HIER_DEPTH_BUFFER);
265 dw0 |= (cmd_len - 2);
266
Chia-I Wue24c3292014-08-21 14:05:23 +0800267 cmd_batch_reserve(cmd, cmd_len);
268 cmd_batch_write(cmd, dw0);
269 cmd_batch_write(cmd, view->cmd[8]);
270 cmd_batch_reloc(cmd, view->cmd[9], view->img->obj.mem,
271 INTEL_DOMAIN_RENDER,
272 INTEL_DOMAIN_RENDER);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800273}
274
Chia-I Wu302742d2014-08-22 10:28:29 +0800275static void gen6_3DSTATE_CC_STATE_POINTERS(struct intel_cmd *cmd,
276 XGL_UINT blend_pos,
277 XGL_UINT ds_pos,
278 XGL_UINT cc_pos)
279{
280 const uint8_t cmd_len = 4;
281 uint32_t dw0;
282
283 CMD_ASSERT(cmd, 6, 6);
284
285 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_CC_STATE_POINTERS) |
286 (cmd_len - 2);
287
288 cmd_batch_reserve(cmd, cmd_len);
289 cmd_batch_write(cmd, dw0);
290 cmd_batch_write(cmd, (blend_pos << 2) | 1);
291 cmd_batch_write(cmd, (ds_pos << 2) | 1);
292 cmd_batch_write(cmd, (cc_pos << 2) | 1);
293}
294
295static void gen7_3dstate_pointer(struct intel_cmd *cmd,
296 int subop, XGL_UINT pos)
297{
298 const uint8_t cmd_len = 2;
299 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
300 GEN6_RENDER_SUBTYPE_3D |
301 subop | (cmd_len - 2);
302
303 cmd_batch_reserve(cmd, cmd_len);
304 cmd_batch_write(cmd, dw0);
305 cmd_batch_write(cmd, pos << 2);
306}
307
308static XGL_UINT gen6_BLEND_STATE(struct intel_cmd *cmd,
309 const struct intel_blend_state *state)
310{
311 const uint8_t cmd_align = GEN6_ALIGNMENT_BLEND_STATE;
312 const uint8_t cmd_len = XGL_MAX_COLOR_ATTACHMENTS * 2;
313
314 CMD_ASSERT(cmd, 6, 7.5);
315 STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len);
316
317 return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align);
318}
319
320static XGL_UINT gen6_DEPTH_STENCIL_STATE(struct intel_cmd *cmd,
321 const struct intel_ds_state *state)
322{
323 const uint8_t cmd_align = GEN6_ALIGNMENT_DEPTH_STENCIL_STATE;
324 const uint8_t cmd_len = 3;
325
326 CMD_ASSERT(cmd, 6, 7.5);
327 STATIC_ASSERT(ARRAY_SIZE(state->cmd) >= cmd_len);
328
329 return cmd_state_copy(cmd, state->cmd, cmd_len, cmd_align);
330}
331
332static XGL_UINT gen6_COLOR_CALC_STATE(struct intel_cmd *cmd,
333 uint32_t stencil_ref,
334 const uint32_t blend_color[4])
335{
336 const uint8_t cmd_align = GEN6_ALIGNMENT_COLOR_CALC_STATE;
337 const uint8_t cmd_len = 6;
338 XGL_UINT pos;
339 uint32_t *dw;
340
341 CMD_ASSERT(cmd, 6, 7.5);
342
343 dw = cmd_state_reserve(cmd, cmd_len, cmd_align, &pos);
344 dw[0] = stencil_ref;
345 dw[1] = 0;
346 dw[2] = blend_color[0];
347 dw[3] = blend_color[1];
348 dw[4] = blend_color[2];
349 dw[5] = blend_color[3];
350 cmd_state_advance(cmd, cmd_len);
351
352 return pos;
353}
354
355static void gen6_cc_states(struct intel_cmd *cmd)
356{
357 const struct intel_blend_state *blend = cmd->bind.state.blend;
358 const struct intel_ds_state *ds = cmd->bind.state.ds;
359 XGL_UINT blend_pos, ds_pos, cc_pos;
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800360 uint32_t stencil_ref;
361 uint32_t blend_color[4];
Chia-I Wu302742d2014-08-22 10:28:29 +0800362
363 CMD_ASSERT(cmd, 6, 6);
364
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800365 if (blend) {
366 blend_pos = gen6_BLEND_STATE(cmd, blend);
367 memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color));
368 } else {
369 blend_pos = 0;
370 memset(blend_color, 0, sizeof(blend_color));
371 }
372
373 if (ds) {
374 ds_pos = gen6_DEPTH_STENCIL_STATE(cmd, ds);
375 stencil_ref = ds->cmd_stencil_ref;
376 } else {
377 ds_pos = 0;
378 stencil_ref = 0;
379 }
380
381 cc_pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +0800382
383 gen6_3DSTATE_CC_STATE_POINTERS(cmd, blend_pos, ds_pos, cc_pos);
384}
385
386static void gen7_cc_states(struct intel_cmd *cmd)
387{
388 const struct intel_blend_state *blend = cmd->bind.state.blend;
389 const struct intel_ds_state *ds = cmd->bind.state.ds;
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800390 uint32_t stencil_ref;
391 uint32_t blend_color[4];
Chia-I Wu302742d2014-08-22 10:28:29 +0800392 XGL_UINT pos;
393
394 CMD_ASSERT(cmd, 7, 7.5);
395
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800396 if (!blend && !ds)
397 return;
Chia-I Wu302742d2014-08-22 10:28:29 +0800398
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800399 if (blend) {
400 pos = gen6_BLEND_STATE(cmd, blend);
401 gen7_3dstate_pointer(cmd,
402 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS, pos);
Chia-I Wu302742d2014-08-22 10:28:29 +0800403
Chia-I Wuce9f11f2014-08-22 10:38:51 +0800404 memcpy(blend_color, blend->cmd_blend_color, sizeof(blend_color));
405 } else {
406 memset(blend_color, 0, sizeof(blend_color));
407 }
408
409 if (ds) {
410 pos = gen6_DEPTH_STENCIL_STATE(cmd, ds);
411 gen7_3dstate_pointer(cmd,
412 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS, pos);
413 } else {
414 stencil_ref = 0;
415 }
416
417 pos = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +0800418 gen7_3dstate_pointer(cmd,
419 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, pos);
420}
421
Chia-I Wu52500102014-08-22 00:46:04 +0800422static void emit_bounded_states(struct intel_cmd *cmd)
423{
424 const struct intel_msaa_state *msaa = cmd->bind.state.msaa;
425
426 /* TODO more states */
427
Chia-I Wu302742d2014-08-22 10:28:29 +0800428 if (cmd_gen(cmd) >= INTEL_GEN(7))
429 gen7_cc_states(cmd);
430 else
431 gen6_cc_states(cmd);
432
Chia-I Wu52500102014-08-22 00:46:04 +0800433 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
434 cmd_batch_reserve(cmd, msaa->cmd_len);
435 cmd_batch_write_n(cmd, msaa->cmd, msaa->cmd_len);
436}
437
Chia-I Wub2755562014-08-20 13:38:52 +0800438XGL_VOID XGLAPI intelCmdBindPipeline(
439 XGL_CMD_BUFFER cmdBuffer,
440 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
441 XGL_PIPELINE pipeline)
442{
443 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
444
445 switch (pipelineBindPoint) {
446 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu018a3962014-08-21 10:37:52 +0800447 cmd->bind.pipeline.compute = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800448 break;
449 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu018a3962014-08-21 10:37:52 +0800450 cmd->bind.pipeline.graphics = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800451 break;
452 default:
453 break;
454 }
455}
456
457XGL_VOID XGLAPI intelCmdBindPipelineDelta(
458 XGL_CMD_BUFFER cmdBuffer,
459 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
460 XGL_PIPELINE_DELTA delta)
461{
462 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
463
464 switch (pipelineBindPoint) {
465 case XGL_PIPELINE_BIND_POINT_COMPUTE:
466 cmd->bind.pipeline.compute_delta = delta;
467 break;
468 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
469 cmd->bind.pipeline.graphics_delta = delta;
470 break;
471 default:
472 break;
473 }
474}
475
476XGL_VOID XGLAPI intelCmdBindStateObject(
477 XGL_CMD_BUFFER cmdBuffer,
478 XGL_STATE_BIND_POINT stateBindPoint,
479 XGL_STATE_OBJECT state)
480{
481 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
482
483 switch (stateBindPoint) {
484 case XGL_STATE_BIND_VIEWPORT:
485 cmd->bind.state.viewport =
486 intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state);
487 break;
488 case XGL_STATE_BIND_RASTER:
489 cmd->bind.state.raster =
490 intel_raster_state((XGL_RASTER_STATE_OBJECT) state);
491 break;
492 case XGL_STATE_BIND_DEPTH_STENCIL:
493 cmd->bind.state.ds =
494 intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state);
495 break;
496 case XGL_STATE_BIND_COLOR_BLEND:
497 cmd->bind.state.blend =
498 intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state);
499 break;
500 case XGL_STATE_BIND_MSAA:
501 cmd->bind.state.msaa =
502 intel_msaa_state((XGL_MSAA_STATE_OBJECT) state);
503 break;
504 default:
505 break;
506 }
507}
508
509XGL_VOID XGLAPI intelCmdBindDescriptorSet(
510 XGL_CMD_BUFFER cmdBuffer,
511 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
512 XGL_UINT index,
513 XGL_DESCRIPTOR_SET descriptorSet,
514 XGL_UINT slotOffset)
515{
516 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
517 struct intel_dset *dset = intel_dset(descriptorSet);
518
519 assert(!index);
520
521 switch (pipelineBindPoint) {
522 case XGL_PIPELINE_BIND_POINT_COMPUTE:
523 cmd->bind.dset.compute = dset;
524 cmd->bind.dset.compute_offset = slotOffset;
525 break;
526 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
527 cmd->bind.dset.graphics = dset;
528 cmd->bind.dset.graphics_offset = slotOffset;
529 break;
530 default:
531 break;
532 }
533}
534
535XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
536 XGL_CMD_BUFFER cmdBuffer,
537 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
538 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView)
539{
540 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
541
542 switch (pipelineBindPoint) {
543 case XGL_PIPELINE_BIND_POINT_COMPUTE:
544 intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView);
545 break;
546 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
547 intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView);
548 break;
549 default:
550 break;
551 }
552}
553
554XGL_VOID XGLAPI intelCmdBindIndexData(
555 XGL_CMD_BUFFER cmdBuffer,
556 XGL_GPU_MEMORY mem_,
557 XGL_GPU_SIZE offset,
558 XGL_INDEX_TYPE indexType)
559{
560 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
561 struct intel_mem *mem = intel_mem(mem_);
562
Chia-I Wu9f039862014-08-20 15:39:56 +0800563 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
564 gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
565 } else {
566 cmd->bind.index.mem = mem;
567 cmd->bind.index.offset = offset;
568 cmd->bind.index.type = indexType;
569 }
Chia-I Wub2755562014-08-20 13:38:52 +0800570}
571
572XGL_VOID XGLAPI intelCmdBindAttachments(
573 XGL_CMD_BUFFER cmdBuffer,
574 XGL_UINT colorAttachmentCount,
575 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
576 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment)
577{
578 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800579 const struct intel_ds_view *ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800580 XGL_UINT i;
581
582 for (i = 0; i < colorAttachmentCount; i++) {
583 const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i];
584 struct intel_rt_view *rt = intel_rt_view(att->view);
585
586 cmd->bind.att.rt[i] = rt;
587 }
588
589 cmd->bind.att.rt_count = colorAttachmentCount;
590
591 if (pDepthStencilAttachment) {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800592 cmd->bind.att.ds = intel_ds_view(pDepthStencilAttachment->view);
593 ds = cmd->bind.att.ds;
594
Chia-I Wub2755562014-08-20 13:38:52 +0800595 } else {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800596 /* all zeros */
597 static const struct intel_ds_view null_ds;
598 ds = &null_ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800599 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800600
Chia-I Wu254db422014-08-21 11:54:29 +0800601 /* TODO workarounds */
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800602 gen6_3DSTATE_DEPTH_BUFFER(cmd, ds);
603 gen6_3DSTATE_STENCIL_BUFFER(cmd, ds);
604 gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds);
Chia-I Wub2755562014-08-20 13:38:52 +0800605}
606
607XGL_VOID XGLAPI intelCmdDraw(
608 XGL_CMD_BUFFER cmdBuffer,
609 XGL_UINT firstVertex,
610 XGL_UINT vertexCount,
611 XGL_UINT firstInstance,
612 XGL_UINT instanceCount)
613{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800614 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu254db422014-08-21 11:54:29 +0800615 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800616
Chia-I Wu52500102014-08-22 00:46:04 +0800617 emit_bounded_states(cmd);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800618
619 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu254db422014-08-21 11:54:29 +0800620 gen7_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount,
621 firstVertex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800622 } else {
Chia-I Wu254db422014-08-21 11:54:29 +0800623 gen6_3DPRIMITIVE(cmd, p->prim_type, false, vertexCount,
624 firstVertex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800625 }
Chia-I Wub2755562014-08-20 13:38:52 +0800626}
627
628XGL_VOID XGLAPI intelCmdDrawIndexed(
629 XGL_CMD_BUFFER cmdBuffer,
630 XGL_UINT firstIndex,
631 XGL_UINT indexCount,
632 XGL_INT vertexOffset,
633 XGL_UINT firstInstance,
634 XGL_UINT instanceCount)
635{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800636 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu254db422014-08-21 11:54:29 +0800637 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800638
Chia-I Wu52500102014-08-22 00:46:04 +0800639 emit_bounded_states(cmd);
Chia-I Wu254db422014-08-21 11:54:29 +0800640
641 if (p->primitive_restart && !gen6_can_primitive_restart(cmd))
642 cmd->result = XGL_ERROR_UNKNOWN;
643
644 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
645 gen75_3DSTATE_VF(cmd, p->primitive_restart,
646 p->primitive_restart_index);
647 } else {
648 gen6_3DSTATE_INDEX_BUFFER(cmd, cmd->bind.index.mem,
649 cmd->bind.index.offset, cmd->bind.index.type,
650 p->primitive_restart);
651 }
Chia-I Wu59c097e2014-08-21 10:51:07 +0800652
653 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu254db422014-08-21 11:54:29 +0800654 gen7_3DPRIMITIVE(cmd, p->prim_type, true, indexCount,
655 firstIndex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800656 } else {
Chia-I Wu254db422014-08-21 11:54:29 +0800657 gen6_3DPRIMITIVE(cmd, p->prim_type, true, indexCount,
658 firstIndex, instanceCount, firstInstance, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800659 }
Chia-I Wub2755562014-08-20 13:38:52 +0800660}
661
662XGL_VOID XGLAPI intelCmdDrawIndirect(
663 XGL_CMD_BUFFER cmdBuffer,
664 XGL_GPU_MEMORY mem,
665 XGL_GPU_SIZE offset,
666 XGL_UINT32 count,
667 XGL_UINT32 stride)
668{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800669 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
670
671 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800672}
673
674XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
675 XGL_CMD_BUFFER cmdBuffer,
676 XGL_GPU_MEMORY mem,
677 XGL_GPU_SIZE offset,
678 XGL_UINT32 count,
679 XGL_UINT32 stride)
680{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800681 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
682
683 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800684}
685
686XGL_VOID XGLAPI intelCmdDispatch(
687 XGL_CMD_BUFFER cmdBuffer,
688 XGL_UINT x,
689 XGL_UINT y,
690 XGL_UINT z)
691{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800692 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
693
694 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800695}
696
697XGL_VOID XGLAPI intelCmdDispatchIndirect(
698 XGL_CMD_BUFFER cmdBuffer,
699 XGL_GPU_MEMORY mem,
700 XGL_GPU_SIZE offset)
701{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800702 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
703
704 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800705}