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Chia-I Wu214dac62014-08-05 11:07:40 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu214dac62014-08-05 11:07:40 +080026 */
27
28#ifndef GPU_H
29#define GPU_H
30
31#include "intel.h"
32
Chia-I Wu9269d1c2014-08-16 12:47:47 +080033#define INTEL_GPU_ASSERT(gpu, min_gen, max_gen) \
34 assert(intel_gpu_gen(gpu) >= INTEL_GEN(min_gen) && \
35 intel_gpu_gen(gpu) <= INTEL_GEN(max_gen))
36
Chia-I Wu1db76e02014-09-15 14:21:14 +080037enum intel_ext_type {
38 INTEL_EXT_WSI_X11,
39
40 INTEL_EXT_COUNT,
41 INTEL_EXT_INVALID = INTEL_EXT_COUNT,
42};
43
Chia-I Wu214dac62014-08-05 11:07:40 +080044enum intel_gpu_engine_type {
45 /* TODO BLT support */
46 INTEL_GPU_ENGINE_3D,
47
48 INTEL_GPU_ENGINE_COUNT
49};
50
Chia-I Wud71ff552015-02-20 12:50:12 -070051struct intel_instance;
Chia-I Wud8965932014-10-13 13:32:37 +080052struct intel_winsys;
Chia-I Wu1db76e02014-09-15 14:21:14 +080053struct intel_wsi_x11;
54
Chia-I Wu214dac62014-08-05 11:07:40 +080055/*
56 * intel_gpu is the only object that does not inherit from intel_base.
57 */
58struct intel_gpu {
Chia-I Wu778a80c2015-01-03 22:45:10 +080059 /* the loader expects a "void *" at the beginning */
60 void *loader_data;
Chia-I Wu214dac62014-08-05 11:07:40 +080061
62 struct intel_gpu *next;
63
64 int devid; /* PCI device ID */
Chia-I Wuf07865e2014-09-15 13:52:21 +080065 char *primary_node; /* path to the primary node */
66 char *render_node; /* path to the render node */
67 int gen_opaque; /* always read this with intel_gpu_gen() */
Chia-I Wu960f1952014-08-28 23:27:10 +080068 int gt;
Chia-I Wu214dac62014-08-05 11:07:40 +080069
Chia-I Wubd657942014-08-21 14:37:35 +080070 XGL_GPU_SIZE max_batch_buffer_size;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -060071 uint32_t batch_buffer_reloc_count;
Chia-I Wu214dac62014-08-05 11:07:40 +080072
73 /*
Chia-I Wuf07865e2014-09-15 13:52:21 +080074 * The enabled hardware features could be limited by the kernel. These
75 * mutable fds allows us to talk to the kernel before the device is
76 * created.
Chia-I Wu214dac62014-08-05 11:07:40 +080077 */
Chia-I Wuf07865e2014-09-15 13:52:21 +080078 int primary_fd_internal;
79 int render_fd_internal;
Chia-I Wu214dac62014-08-05 11:07:40 +080080
Chia-I Wu1db76e02014-09-15 14:21:14 +080081#ifdef ENABLE_WSI_X11
82 struct intel_wsi_x11 *x11;
83#endif
84
Chia-I Wud8965932014-10-13 13:32:37 +080085 struct intel_winsys *winsys;
Chia-I Wu214dac62014-08-05 11:07:40 +080086};
87
88static inline struct intel_gpu *intel_gpu(XGL_PHYSICAL_GPU gpu)
89{
90 return (struct intel_gpu *) gpu;
91}
92
93static inline int intel_gpu_gen(const struct intel_gpu *gpu)
94{
95#ifdef INTEL_GEN_SPECIALIZED
96 return INTEL_GEN(INTEL_GEN_SPECIALIZED);
97#else
98 return gpu->gen_opaque;
99#endif
100}
101
Chia-I Wud71ff552015-02-20 12:50:12 -0700102XGL_RESULT intel_gpu_create(const struct intel_instance *instance, int devid,
103 const char *primary_node, const char *render_node,
104 struct intel_gpu **gpu_ret);
105void intel_gpu_destroy(struct intel_gpu *gpu);
Chia-I Wu214dac62014-08-05 11:07:40 +0800106
107void intel_gpu_get_props(const struct intel_gpu *gpu,
108 XGL_PHYSICAL_GPU_PROPERTIES *props);
109void intel_gpu_get_perf(const struct intel_gpu *gpu,
110 XGL_PHYSICAL_GPU_PERFORMANCE *perf);
111void intel_gpu_get_queue_props(const struct intel_gpu *gpu,
112 enum intel_gpu_engine_type engine,
113 XGL_PHYSICAL_GPU_QUEUE_PROPERTIES *props);
114void intel_gpu_get_memory_props(const struct intel_gpu *gpu,
115 XGL_PHYSICAL_GPU_MEMORY_PROPERTIES *props);
116
Chia-I Wu3f4bd102014-12-19 13:14:42 +0800117int intel_gpu_get_max_threads(const struct intel_gpu *gpu,
118 XGL_PIPELINE_SHADER_STAGE stage);
119
Chia-I Wu1db76e02014-09-15 14:21:14 +0800120void intel_gpu_associate_x11(struct intel_gpu *gpu,
121 struct intel_wsi_x11 *x11,
122 int fd);
Chia-I Wu214dac62014-08-05 11:07:40 +0800123XGL_RESULT intel_gpu_open(struct intel_gpu *gpu);
124void intel_gpu_close(struct intel_gpu *gpu);
125
Chia-I Wu1db76e02014-09-15 14:21:14 +0800126enum intel_ext_type intel_gpu_lookup_extension(const struct intel_gpu *gpu,
127 const char *ext);
Chia-I Wu214dac62014-08-05 11:07:40 +0800128
Chia-I Wu214dac62014-08-05 11:07:40 +0800129#endif /* GPU_H */