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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
40
Chia-I Wu958d1b72014-08-21 11:28:11 +080041struct intel_cmd_reloc;
42
Chia-I Wub2755562014-08-20 13:38:52 +080043/*
44 * States bounded to the command buffer. We want to write states directly to
45 * the command buffer when possible, and reduce this struct.
46 */
47struct intel_cmd_bind {
48 struct {
49 const struct intel_pipeline *graphics;
50 const struct intel_pipeline *compute;
51 const struct intel_pipeline_delta *graphics_delta;
52 const struct intel_pipeline_delta *compute_delta;
53 } pipeline;
54
55 struct {
56 const struct intel_viewport_state *viewport;
57 const struct intel_raster_state *raster;
58 const struct intel_msaa_state *msaa;
59 const struct intel_blend_state *blend;
60 const struct intel_ds_state *ds;
61 } state;
62
63 struct {
64 const struct intel_dset *graphics;
65 XGL_UINT graphics_offset;
66 const struct intel_dset *compute;
67 XGL_UINT compute_offset;
68 } dset;
69
70 struct {
71 struct intel_mem_view graphics;
72 struct intel_mem_view compute;
73 } mem_view;
74
75 struct {
76 const struct intel_mem *mem;
77 XGL_GPU_SIZE offset;
78 XGL_INDEX_TYPE type;
79 } index;
80
81 struct {
82 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
83 XGL_UINT rt_count;
84
85 const struct intel_ds_view *ds;
86 } att;
87};
Chia-I Wu09142132014-08-11 15:42:55 +080088
Chia-I Wue24c3292014-08-21 14:05:23 +080089struct intel_cmd_writer {
90 struct intel_bo *bo;
91 void *ptr_opaque;
92
93 /* in DWords */
94 XGL_UINT size;
95 XGL_UINT used;
96};
97
Chia-I Wu730e5362014-08-19 12:15:09 +080098struct intel_cmd {
99 struct intel_obj obj;
100
101 struct intel_dev *dev;
102
Chia-I Wu343b1372014-08-20 16:39:20 +0800103 struct intel_cmd_reloc *relocs;
104 XGL_UINT reloc_count;
105
Chia-I Wu730e5362014-08-19 12:15:09 +0800106 XGL_FLAGS flags;
107
Chia-I Wue24c3292014-08-21 14:05:23 +0800108 struct intel_cmd_writer batch;
Chia-I Wu730e5362014-08-19 12:15:09 +0800109
Chia-I Wu343b1372014-08-20 16:39:20 +0800110 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800111 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800112
113 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800114};
115
116static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
117{
118 return (struct intel_cmd *) cmd;
119}
120
121static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
122{
123 return (struct intel_cmd *) obj;
124}
125
126XGL_RESULT intel_cmd_create(struct intel_dev *dev,
127 const XGL_CMD_BUFFER_CREATE_INFO *info,
128 struct intel_cmd **cmd_ret);
129void intel_cmd_destroy(struct intel_cmd *cmd);
130
131XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
132XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
133
Chia-I Wue24c3292014-08-21 14:05:23 +0800134static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
135 XGL_GPU_SIZE *used)
136{
137 const struct intel_cmd_writer *writer = &cmd->batch;
138
139 if (used)
140 *used = sizeof(uint32_t) * writer->used;
141
142 return writer->bo;
143}
144
Chia-I Wu09142132014-08-11 15:42:55 +0800145XGL_RESULT XGLAPI intelCreateCommandBuffer(
146 XGL_DEVICE device,
147 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
148 XGL_CMD_BUFFER* pCmdBuffer);
149
150XGL_RESULT XGLAPI intelBeginCommandBuffer(
151 XGL_CMD_BUFFER cmdBuffer,
152 XGL_FLAGS flags);
153
154XGL_RESULT XGLAPI intelEndCommandBuffer(
155 XGL_CMD_BUFFER cmdBuffer);
156
157XGL_RESULT XGLAPI intelResetCommandBuffer(
158 XGL_CMD_BUFFER cmdBuffer);
159
160XGL_VOID XGLAPI intelCmdBindPipeline(
161 XGL_CMD_BUFFER cmdBuffer,
162 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
163 XGL_PIPELINE pipeline);
164
165XGL_VOID XGLAPI intelCmdBindPipelineDelta(
166 XGL_CMD_BUFFER cmdBuffer,
167 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
168 XGL_PIPELINE_DELTA delta);
169
170XGL_VOID XGLAPI intelCmdBindStateObject(
171 XGL_CMD_BUFFER cmdBuffer,
172 XGL_STATE_BIND_POINT stateBindPoint,
173 XGL_STATE_OBJECT state);
174
175XGL_VOID XGLAPI intelCmdBindDescriptorSet(
176 XGL_CMD_BUFFER cmdBuffer,
177 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
178 XGL_UINT index,
179 XGL_DESCRIPTOR_SET descriptorSet,
180 XGL_UINT slotOffset);
181
182XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
183 XGL_CMD_BUFFER cmdBuffer,
184 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
185 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
186
187XGL_VOID XGLAPI intelCmdBindIndexData(
188 XGL_CMD_BUFFER cmdBuffer,
189 XGL_GPU_MEMORY mem,
190 XGL_GPU_SIZE offset,
191 XGL_INDEX_TYPE indexType);
192
193XGL_VOID XGLAPI intelCmdBindAttachments(
194 XGL_CMD_BUFFER cmdBuffer,
195 XGL_UINT colorAttachmentCount,
196 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
197 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
198
199XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
200 XGL_CMD_BUFFER cmdBuffer,
201 XGL_UINT transitionCount,
202 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
203
204XGL_VOID XGLAPI intelCmdPrepareImages(
205 XGL_CMD_BUFFER cmdBuffer,
206 XGL_UINT transitionCount,
207 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
208
209XGL_VOID XGLAPI intelCmdDraw(
210 XGL_CMD_BUFFER cmdBuffer,
211 XGL_UINT firstVertex,
212 XGL_UINT vertexCount,
213 XGL_UINT firstInstance,
214 XGL_UINT instanceCount);
215
216XGL_VOID XGLAPI intelCmdDrawIndexed(
217 XGL_CMD_BUFFER cmdBuffer,
218 XGL_UINT firstIndex,
219 XGL_UINT indexCount,
220 XGL_INT vertexOffset,
221 XGL_UINT firstInstance,
222 XGL_UINT instanceCount);
223
224XGL_VOID XGLAPI intelCmdDrawIndirect(
225 XGL_CMD_BUFFER cmdBuffer,
226 XGL_GPU_MEMORY mem,
227 XGL_GPU_SIZE offset,
228 XGL_UINT32 count,
229 XGL_UINT32 stride);
230
231XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
232 XGL_CMD_BUFFER cmdBuffer,
233 XGL_GPU_MEMORY mem,
234 XGL_GPU_SIZE offset,
235 XGL_UINT32 count,
236 XGL_UINT32 stride);
237
238XGL_VOID XGLAPI intelCmdDispatch(
239 XGL_CMD_BUFFER cmdBuffer,
240 XGL_UINT x,
241 XGL_UINT y,
242 XGL_UINT z);
243
244XGL_VOID XGLAPI intelCmdDispatchIndirect(
245 XGL_CMD_BUFFER cmdBuffer,
246 XGL_GPU_MEMORY mem,
247 XGL_GPU_SIZE offset);
248
249XGL_VOID XGLAPI intelCmdCopyMemory(
250 XGL_CMD_BUFFER cmdBuffer,
251 XGL_GPU_MEMORY srcMem,
252 XGL_GPU_MEMORY destMem,
253 XGL_UINT regionCount,
254 const XGL_MEMORY_COPY* pRegions);
255
256XGL_VOID XGLAPI intelCmdCopyImage(
257 XGL_CMD_BUFFER cmdBuffer,
258 XGL_IMAGE srcImage,
259 XGL_IMAGE destImage,
260 XGL_UINT regionCount,
261 const XGL_IMAGE_COPY* pRegions);
262
263XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
264 XGL_CMD_BUFFER cmdBuffer,
265 XGL_GPU_MEMORY srcMem,
266 XGL_IMAGE destImage,
267 XGL_UINT regionCount,
268 const XGL_MEMORY_IMAGE_COPY* pRegions);
269
270XGL_VOID XGLAPI intelCmdCopyImageToMemory(
271 XGL_CMD_BUFFER cmdBuffer,
272 XGL_IMAGE srcImage,
273 XGL_GPU_MEMORY destMem,
274 XGL_UINT regionCount,
275 const XGL_MEMORY_IMAGE_COPY* pRegions);
276
277XGL_VOID XGLAPI intelCmdCloneImageData(
278 XGL_CMD_BUFFER cmdBuffer,
279 XGL_IMAGE srcImage,
280 XGL_IMAGE_STATE srcImageState,
281 XGL_IMAGE destImage,
282 XGL_IMAGE_STATE destImageState);
283
284XGL_VOID XGLAPI intelCmdUpdateMemory(
285 XGL_CMD_BUFFER cmdBuffer,
286 XGL_GPU_MEMORY destMem,
287 XGL_GPU_SIZE destOffset,
288 XGL_GPU_SIZE dataSize,
289 const XGL_UINT32* pData);
290
291XGL_VOID XGLAPI intelCmdFillMemory(
292 XGL_CMD_BUFFER cmdBuffer,
293 XGL_GPU_MEMORY destMem,
294 XGL_GPU_SIZE destOffset,
295 XGL_GPU_SIZE fillSize,
296 XGL_UINT32 data);
297
298XGL_VOID XGLAPI intelCmdClearColorImage(
299 XGL_CMD_BUFFER cmdBuffer,
300 XGL_IMAGE image,
301 const XGL_FLOAT color[4],
302 XGL_UINT rangeCount,
303 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
304
305XGL_VOID XGLAPI intelCmdClearColorImageRaw(
306 XGL_CMD_BUFFER cmdBuffer,
307 XGL_IMAGE image,
308 const XGL_UINT32 color[4],
309 XGL_UINT rangeCount,
310 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
311
312XGL_VOID XGLAPI intelCmdClearDepthStencil(
313 XGL_CMD_BUFFER cmdBuffer,
314 XGL_IMAGE image,
315 XGL_FLOAT depth,
316 XGL_UINT32 stencil,
317 XGL_UINT rangeCount,
318 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
319
320XGL_VOID XGLAPI intelCmdResolveImage(
321 XGL_CMD_BUFFER cmdBuffer,
322 XGL_IMAGE srcImage,
323 XGL_IMAGE destImage,
324 XGL_UINT rectCount,
325 const XGL_IMAGE_RESOLVE* pRects);
326
327XGL_VOID XGLAPI intelCmdSetEvent(
328 XGL_CMD_BUFFER cmdBuffer,
329 XGL_EVENT event);
330
331XGL_VOID XGLAPI intelCmdResetEvent(
332 XGL_CMD_BUFFER cmdBuffer,
333 XGL_EVENT event);
334
335XGL_VOID XGLAPI intelCmdMemoryAtomic(
336 XGL_CMD_BUFFER cmdBuffer,
337 XGL_GPU_MEMORY destMem,
338 XGL_GPU_SIZE destOffset,
339 XGL_UINT64 srcData,
340 XGL_ATOMIC_OP atomicOp);
341
342XGL_VOID XGLAPI intelCmdBeginQuery(
343 XGL_CMD_BUFFER cmdBuffer,
344 XGL_QUERY_POOL queryPool,
345 XGL_UINT slot,
346 XGL_FLAGS flags);
347
348XGL_VOID XGLAPI intelCmdEndQuery(
349 XGL_CMD_BUFFER cmdBuffer,
350 XGL_QUERY_POOL queryPool,
351 XGL_UINT slot);
352
353XGL_VOID XGLAPI intelCmdResetQueryPool(
354 XGL_CMD_BUFFER cmdBuffer,
355 XGL_QUERY_POOL queryPool,
356 XGL_UINT startQuery,
357 XGL_UINT queryCount);
358
359XGL_VOID XGLAPI intelCmdWriteTimestamp(
360 XGL_CMD_BUFFER cmdBuffer,
361 XGL_TIMESTAMP_TYPE timestampType,
362 XGL_GPU_MEMORY destMem,
363 XGL_GPU_SIZE destOffset);
364
365XGL_VOID XGLAPI intelCmdInitAtomicCounters(
366 XGL_CMD_BUFFER cmdBuffer,
367 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
368 XGL_UINT startCounter,
369 XGL_UINT counterCount,
370 const XGL_UINT32* pData);
371
372XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
373 XGL_CMD_BUFFER cmdBuffer,
374 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
375 XGL_UINT startCounter,
376 XGL_UINT counterCount,
377 XGL_GPU_MEMORY srcMem,
378 XGL_GPU_SIZE srcOffset);
379
380XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
381 XGL_CMD_BUFFER cmdBuffer,
382 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
383 XGL_UINT startCounter,
384 XGL_UINT counterCount,
385 XGL_GPU_MEMORY destMem,
386 XGL_GPU_SIZE destOffset);
387
388XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
389 XGL_CMD_BUFFER cmdBuffer,
390 const XGL_CHAR* pMarker);
391
392XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
393 XGL_CMD_BUFFER cmdBuffer);
394
395#endif /* CMD_H */