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Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -06001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Courtney Goeltzenleuchter <courtney@lunarg.com>
26 * Chia-I Wu <olv@lunarg.com>
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -060027 */
28
29#ifndef PIPELINE_H
30#define PIPELINE_H
31
32#include "intel.h"
33#include "obj.h"
34#include "dev.h"
35
Chia-I Wu1f7540b2014-08-22 13:56:18 +080036#define INTEL_RMAP_SLOT_RT ((XGL_UINT) -1)
37#define INTEL_RMAP_SLOT_DYN ((XGL_UINT) -2)
38struct intel_rmap_slot {
39 /*
40 *
41 * When path_len is 0, the slot is unused.
42 * When path_len is 1, the slot uses descriptor "index".
43 * When path_len is INTEL_RMAP_SLOT_RT, the slot uses RT "index".
44 * When path_len is INTEL_RMAP_SLOT_DYN, the slot uses the dynamic view.
45 * Otherwise, the slot uses "path" to find the descriptor.
46 */
47 XGL_UINT path_len;
48
49 union {
50 XGL_UINT index;
51 XGL_UINT *path;
52 } u;
53};
54
55/**
56 * Shader resource mapping.
57 */
58struct intel_rmap {
59 /* this is not an intel_obj */
60
61 XGL_UINT rt_count;
62 XGL_UINT resource_count;
63 XGL_UINT uav_count;
64 XGL_UINT sampler_count;
65
66 /*
67 * rt_count slots +
68 * resource_count slots +
69 * uav_count slots +
70 * sampler_count slots
71 */
72 struct intel_rmap_slot *slots;
73 XGL_UINT slot_count;
74};
75
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -060076#define SHADER_VERTEX_FLAG (1 << XGL_SHADER_STAGE_VERTEX)
77#define SHADER_TESS_CONTROL_FLAG (1 << XGL_SHADER_STAGE_TESS_CONTROL)
78#define SHADER_TESS_EVAL_FLAG (1 << XGL_SHADER_STAGE_TESS_EVALUATION)
79#define SHADER_GEOMETRY_FLAG (1 << XGL_SHADER_STAGE_GEOMETRY)
80#define SHADER_FRAGMENT_FLAG (1 << XGL_SHADER_STAGE_FRAGMENT)
81#define SHADER_COMPUTE_FLAG (1 << XGL_SHADER_STAGE_COMPUTE)
82
Chia-I Wue3467672014-09-02 13:06:11 +080083struct intel_pipe_shader {
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060084 void *pCode;
85 uint32_t codeSize;
Courtney Goeltzenleuchterc4ef6142014-08-29 16:25:30 -060086
87 /*
88 * must grab everything we need from shader object as that
89 * can go away after the pipeline is created
90 */
91 XGL_FLAGS uses;
92
93 XGL_UINT in_count;
94 XGL_UINT out_count;
95
96 XGL_UINT sampler_count;
97 XGL_UINT surface_count;
98
99 /*
100 * Used by 3DSTATE_VS command
101 */
102 XGL_UINT urb_grf_start;
103 XGL_UINT urb_read_length;
104
105 XGL_FLAGS barycentric_interps;
Chia-I Wu39026c92014-09-02 10:03:19 +0800106
107 struct intel_rmap *rmap;
Chia-I Wuc3ddee62014-09-02 10:53:20 +0800108
109 void *pcb;
110 XGL_SIZE pcb_size;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -0600111};
112
Chia-I Wu1638c1c2014-08-29 14:01:16 +0800113/*
114 * On GEN6, there are
115 *
116 * - 3DSTATE_URB (3)
Chia-I Wu4f3612b2014-08-29 15:40:39 +0800117 * - 3DSTATE_VERTEX_ELEMENTS (3)
Chia-I Wu1638c1c2014-08-29 14:01:16 +0800118 *
119 * On GEN7, there are
120 *
121 * - 3DSTATE_URB_x (2*4)
122 * - 3DSTATE_PUSH_CONSTANT_ALLOC_x (2*5)
Chia-I Wu4f3612b2014-08-29 15:40:39 +0800123 * - 3DSTATE_VERTEX_ELEMENTS (3)
Chia-I Wu1638c1c2014-08-29 14:01:16 +0800124 * - 3DSTATE_HS (7)
125 * - 3DSTATE_TE (4)
126 * - 3DSTATE_DS (6)
127 */
Courtney Goeltzenleuchterdee81a62014-08-28 18:05:24 -0600128#define INTEL_PSO_CMD_ENTRIES 64
Courtney Goeltzenleuchter814cd292014-08-28 13:16:27 -0600129
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600130/**
131 * 3D pipeline.
132 */
133struct intel_pipeline {
134 struct intel_obj obj;
135
136 struct intel_dev *dev;
137
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600138 /* XGL IA_STATE */
Courtney Goeltzenleuchter42509992014-08-21 17:33:46 -0600139 XGL_PIPELINE_IA_STATE_CREATE_INFO ia_state;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600140 int prim_type;
141 bool primitive_restart;
142 uint32_t primitive_restart_index;
143
144 /* Index of provoking vertex for each prim type */
145 int provoking_vertex_tri;
146 int provoking_vertex_trifan;
147 int provoking_vertex_line;
148
149 // TODO: This should probably be Intel HW state, not XGL state.
150 /* Depth Buffer format */
151 XGL_FORMAT db_format;
152
153 XGL_PIPELINE_CB_STATE cb_state;
154
155 // XGL_PIPELINE_RS_STATE_CREATE_INFO rs_state;
156 bool depthClipEnable;
157 bool rasterizerDiscardEnable;
158 float pointSize;
159
160 XGL_PIPELINE_TESS_STATE_CREATE_INFO tess_state;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600161
162 uint32_t active_shaders;
Chia-I Wuc3ddee62014-09-02 10:53:20 +0800163 struct intel_pipe_shader vs;
Chia-I Wue3467672014-09-02 13:06:11 +0800164 struct intel_pipe_shader tess_control;
165 struct intel_pipe_shader tess_eval;
Chia-I Wuc3ddee62014-09-02 10:53:20 +0800166 struct intel_pipe_shader gs;
167 struct intel_pipe_shader fs;
Chia-I Wue3467672014-09-02 13:06:11 +0800168 struct intel_pipe_shader compute;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600169
Chia-I Wu8370b402014-08-29 12:28:37 +0800170 uint32_t wa_flags;
171
Courtney Goeltzenleuchter814cd292014-08-28 13:16:27 -0600172 uint32_t cmds[INTEL_PSO_CMD_ENTRIES];
173 XGL_UINT cmd_len;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600174};
175
176static inline struct intel_pipeline *intel_pipeline(XGL_PIPELINE pipeline)
177{
178 return (struct intel_pipeline *) pipeline;
179}
180
Courtney Goeltzenleuchter42509992014-08-21 17:33:46 -0600181static inline struct intel_pipeline *intel_pipeline_from_base(struct intel_base *base)
182{
183 return (struct intel_pipeline *) base;
184}
185
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600186static inline struct intel_pipeline *intel_pipeline_from_obj(struct intel_obj *obj)
187{
Courtney Goeltzenleuchter42509992014-08-21 17:33:46 -0600188 return intel_pipeline_from_base(&obj->base);
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600189}
190
191XGL_RESULT XGLAPI intelCreateGraphicsPipeline(
192 XGL_DEVICE device,
193 const XGL_GRAPHICS_PIPELINE_CREATE_INFO* pCreateInfo,
194 XGL_PIPELINE* pPipeline);
195
196XGL_RESULT XGLAPI intelCreateComputePipeline(
197 XGL_DEVICE device,
198 const XGL_COMPUTE_PIPELINE_CREATE_INFO* pCreateInfo,
199 XGL_PIPELINE* pPipeline);
200
201XGL_RESULT XGLAPI intelStorePipeline(
202 XGL_PIPELINE pipeline,
203 XGL_SIZE* pDataSize,
204 XGL_VOID* pData);
205
206XGL_RESULT XGLAPI intelLoadPipeline(
207 XGL_DEVICE device,
208 XGL_SIZE dataSize,
209 const XGL_VOID* pData,
210 XGL_PIPELINE* pPipeline);
211
212XGL_RESULT XGLAPI intelCreatePipelineDelta(
213 XGL_DEVICE device,
214 XGL_PIPELINE p1,
215 XGL_PIPELINE p2,
216 XGL_PIPELINE_DELTA* delta);
217#endif // PIPELINE_H