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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / 26803c88f685d8ae32976d28301f0b4a33bbb3ef / . / asoc / sa6155.c
blob: 3f32c8869c350f8e5044dcbc4e91dad93f849d31 [file] [log] [blame]
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12/*
13 * Copyright 2011, The Android Open Source Project
14
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 * Redistributions of source code must retain the above copyright
18 notice, this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in the
21 documentation and/or other materials provided with the distribution.
22 * Neither the name of The Android Open Source Project nor the names of
23 its contributors may be used to endorse or promote products derived
24 from this software without specific prior written permission.
25
26 * THIS SOFTWARE IS PROVIDED BY The Android Open Source Project ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL The Android Open Source Project BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36 * DAMAGE.
37 */
38
39#include <linux/clk.h>
40#include <linux/delay.h>
41#include <linux/gpio.h>
42#include <linux/of_gpio.h>
43#include <linux/platform_device.h>
44#include <linux/slab.h>
45#include <linux/io.h>
46#include <linux/module.h>
47#include <linux/input.h>
48#include <linux/of_device.h>
49#include <linux/pm_qos.h>
50#include <sound/core.h>
51#include <sound/soc.h>
52#include <sound/soc-dapm.h>
53#include <sound/pcm.h>
54#include <sound/pcm_params.h>
55#include <sound/info.h>
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]56#include <soc/snd_event.h>
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]57#include <dsp/audio_notifier.h>
58#include <dsp/q6afe-v2.h>
59#include <dsp/q6core.h>
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]60#include <soc/qcom/boot_stats.h>
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]61#include "device_event.h"
62#include "msm-pcm-routing-v2.h"
63
64#define DRV_NAME "sa6155-asoc-snd"
65
66#define __CHIPSET__ "SA6155 "
67#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
68
69#define DEV_NAME_STR_LEN 32
70
71#define SAMPLING_RATE_8KHZ 8000
72#define SAMPLING_RATE_11P025KHZ 11025
73#define SAMPLING_RATE_16KHZ 16000
74#define SAMPLING_RATE_22P05KHZ 22050
75#define SAMPLING_RATE_32KHZ 32000
76#define SAMPLING_RATE_44P1KHZ 44100
77#define SAMPLING_RATE_48KHZ 48000
78#define SAMPLING_RATE_88P2KHZ 88200
79#define SAMPLING_RATE_96KHZ 96000
80#define SAMPLING_RATE_176P4KHZ 176400
81#define SAMPLING_RATE_192KHZ 192000
82#define SAMPLING_RATE_352P8KHZ 352800
83#define SAMPLING_RATE_384KHZ 384000
84
85#define ADSP_STATE_READY_TIMEOUT_MS 3000
86#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
87
88enum {
89 PRIM_MI2S = 0,
90 SEC_MI2S,
91 TERT_MI2S,
92 QUAT_MI2S,
93 QUIN_MI2S,
94 MI2S_MAX,
95};
96
97enum {
98 PRIM_AUX_PCM = 0,
99 SEC_AUX_PCM,
100 TERT_AUX_PCM,
101 QUAT_AUX_PCM,
102 QUIN_AUX_PCM,
103 AUX_PCM_MAX,
104};
105
106struct mi2s_conf {
107 struct mutex lock;
108 u32 ref_cnt;
109 u32 msm_is_mi2s_master;
110};
111
112static u32 mi2s_ebit_clk[MI2S_MAX] = {
113 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
114 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
115 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
116 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
117 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
118};
119
120struct dev_config {
121 u32 sample_rate;
122 u32 bit_format;
123 u32 channels;
124};
125
126enum {
127 DP_RX_IDX = 0,
128 EXT_DISP_RX_IDX_MAX,
129};
130
131enum pinctrl_pin_state {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]132 STATE_SLEEP = 0, /* All pins are in sleep state */
133 STATE_ACTIVE, /* TDM = active */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]134};
135
136struct msm_pinctrl_info {
137 struct pinctrl *pinctrl;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]138 struct pinctrl_state *sleep;
139 struct pinctrl_state *active;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]140 enum pinctrl_pin_state curr_state;
141};
142
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]143static const char *const pin_states[] = {"sleep", "active"};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]144
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]145static const char *const tdm_gpio_phandle[] = {"qcom,pri-tdm-gpios",
146 "qcom,sec-tdm-gpios",
147 "qcom,tert-tdm-gpios",
148 "qcom,quat-tdm-gpios",
149 "qcom,quin-tdm-gpios"};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]150
151enum {
152 TDM_0 = 0,
153 TDM_1,
154 TDM_2,
155 TDM_3,
156 TDM_4,
157 TDM_5,
158 TDM_6,
159 TDM_7,
160 TDM_PORT_MAX,
161};
162
163enum {
164 TDM_PRI = 0,
165 TDM_SEC,
166 TDM_TERT,
167 TDM_QUAT,
168 TDM_QUIN,
169 TDM_INTERFACE_MAX,
170};
171
172struct tdm_port {
173 u32 mode;
174 u32 channel;
175};
176
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]177struct tdm_conf {
178 struct mutex lock;
179 u32 ref_cnt;
180};
181
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]182/* TDM default config */
183static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
184 { /* PRI TDM */
185 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
186 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
187 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
188 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
189 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
190 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
191 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
192 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
193 },
194 { /* SEC TDM */
195 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
196 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
197 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
198 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
199 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
200 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
201 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
202 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
203 },
204 { /* TERT TDM */
205 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
206 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
207 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
208 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
209 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
210 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
211 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
212 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
213 },
214 { /* QUAT TDM */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]215 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8}, /* RX_0 */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]216 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8}, /* RX_1 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]217 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
218 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
219 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
220 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
221 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
222 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
223 },
224 { /* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]225 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
226 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
227 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
228 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]229 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
230 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
231 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
232 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
233 }
234};
235
236/* TDM default config */
237static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
238 { /* PRI TDM */
239 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_0 */
240 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
241 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
242 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_3 */
243 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
244 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
245 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
246 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
247 },
248 { /* SEC TDM */
249 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* TX_0 */
250 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
251 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
252 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
253 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
254 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
255 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
256 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
257 },
258 { /* TERT TDM */
259 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
260 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
261 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
262 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
263 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
264 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
265 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
266 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
267 },
268 { /* QUAT TDM */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]269 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 16}, /* TX_0 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]270 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
271 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
272 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
273 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
274 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
275 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
276 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
277 },
278 { /* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]279 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
280 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
281 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]282 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
283 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
284 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
285 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
286 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
287 }
288};
289
290/* Default configuration of external display BE */
291static struct dev_config ext_disp_rx_cfg[] = {
292 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
293};
294
295static struct dev_config usb_rx_cfg = {
296 .sample_rate = SAMPLING_RATE_48KHZ,
297 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
298 .channels = 2,
299};
300
301static struct dev_config usb_tx_cfg = {
302 .sample_rate = SAMPLING_RATE_48KHZ,
303 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
304 .channels = 1,
305};
306
307static struct dev_config proxy_rx_cfg = {
308 .sample_rate = SAMPLING_RATE_48KHZ,
309 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
310 .channels = 2,
311};
312
313/* Default configuration of MI2S channels */
314static struct dev_config mi2s_rx_cfg[] = {
315 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
316 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
317 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
318 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
319 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
320};
321
322static struct dev_config mi2s_tx_cfg[] = {
323 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
324 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
325 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
326 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
327 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
328};
329
330static struct dev_config aux_pcm_rx_cfg[] = {
331 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
332 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
333 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
334 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
335 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
336};
337
338static struct dev_config aux_pcm_tx_cfg[] = {
339 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
340 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
341 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
342 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
343 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
344};
345
346/* TDM default slot config */
347struct tdm_slot_cfg {
348 u32 width;
349 u32 num;
350};
351
352static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
353 /* PRI TDM */
354 {32, 8},
355 /* SEC TDM */
356 {32, 8},
357 /* TERT TDM */
358 {32, 8},
359 /* QUAT TDM */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]360 {32, 16},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]361 /* QUIN TDM */
362 {32, 8}
363};
364
365/*****************************************************************************
366* TO BE UPDATED: Codec/Platform specific tdm slot table
367*****************************************************************************/
368static struct tdm_slot_cfg tdm_slot_custom[TDM_INTERFACE_MAX] = {
369 /* PRI TDM */
370 {16, 16},
371 /* SEC TDM */
372 {16, 16},
373 /* TERT TDM */
374 {16, 16},
375 /* QUAT TDM */
376 {16, 16},
377 /* QUIN TDM */
378 {16, 16}
379};
380
381
382/* TDM default slot offset config */
383#define TDM_SLOT_OFFSET_MAX 32
384
385static unsigned int tdm_rx_slot_offset
386 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
387 {/* PRI TDM */
388 {0, 4, 0xFFFF},
389 {8, 12, 0xFFFF},
390 {16, 20, 0xFFFF},
391 {24, 28, 0xFFFF},
392 {0xFFFF}, /* not used */
393 {0xFFFF}, /* not used */
394 {0xFFFF}, /* not used */
395 {0xFFFF}, /* not used */
396 },
397 {/* SEC TDM */
398 {0, 4, 0xFFFF},
399 {8, 12, 0xFFFF},
400 {16, 20, 0xFFFF},
401 {24, 28, 0xFFFF},
402 {0xFFFF}, /* not used */
403 {0xFFFF}, /* not used */
404 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]405 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]406 },
407 {/* TERT TDM */
408 {0, 4, 8, 12, 16, 20, 0xFFFF},
409 {24, 0xFFFF},
410 {28, 0xFFFF},
411 {0xFFFF}, /* not used */
412 {0xFFFF}, /* not used */
413 {0xFFFF}, /* not used */
414 {0xFFFF}, /* not used */
415 {0xFFFF}, /* not used */
416 },
417 {/* QUAT TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]418 {0, 8, 16, 24, 32, 40, 48, 56, 0xFFFF}, /*8 CH SPKR*/
419 {4, 12, 20, 28, 36, 44, 52, 60, 0xFFFF}, /*8 CH SPKR*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]420 {0xFFFF}, /* not used */
421 {0xFFFF}, /* not used */
422 {0xFFFF}, /* not used */
423 {0xFFFF}, /* not used */
424 {0xFFFF}, /* not used */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]425 {60,0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]426 },
427 {/* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]428 {0, 4, 8, 12, 16, 20, 0xFFFF},
429 {24, 0xFFFF},
430 {28, 0xFFFF},
431 {0xFFFF}, /* not used */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]432 {0xFFFF}, /* not used */
433 {0xFFFF}, /* not used */
434 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]435 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]436 }
437};
438
439static unsigned int tdm_tx_slot_offset
440 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
441 {/* PRI TDM */
442 {0, 4, 0xFFFF},
443 {8, 12, 0xFFFF},
444 {16, 20, 0xFFFF},
445 {24, 28, 0xFFFF},
446 {0xFFFF}, /* not used */
447 {0xFFFF}, /* not used */
448 {0xFFFF}, /* not used */
449 {0xFFFF}, /* not used */
450 },
451 {/* SEC TDM */
452 {0, 4, 8, 12, 16, 20, 0xFFFF},
453 {24, 0xFFFF},
454 {28, 0xFFFF},
455 {0xFFFF}, /* not used */
456 {0xFFFF}, /* not used */
457 {0xFFFF}, /* not used */
458 {0xFFFF}, /* not used */
459 {0xFFFF}, /* not used */
460 },
461 {/* TERT TDM */
462 {0, 4, 8, 12, 0xFFFF},
463 {16, 20, 0xFFFF},
464 {24, 28, 0xFFFF},
465 {0xFFFF}, /* not used */
466 {0xFFFF}, /* not used */
467 {0xFFFF}, /* not used */
468 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]469 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]470 },
471 {/* QUAT TDM */
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]472 {0, 4, 8, 12, 16, 20, 24, 28,
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]473 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},/*MIC ARR*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]474 {0xFFFF}, /* not used */
475 {0xFFFF}, /* not used */
476 {0xFFFF}, /* not used */
477 {0xFFFF}, /* not used */
478 {0xFFFF}, /* not used */
479 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]480 {60,0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]481 },
482 {/* QUIN TDM */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]483 {0, 4, 8, 12, 0xFFFF},
484 {16, 20, 0xFFFF},
485 {24, 28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]486 {0xFFFF}, /* not used */
487 {0xFFFF}, /* not used */
488 {0xFFFF}, /* not used */
489 {0xFFFF}, /* not used */
Derek Chen26803c82019-12-11 15:40:03 -0800[diff] [blame^]490 {28, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]491 }
492};
493
494/*****************************************************************************
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]495* TO BE UPDATED: Codec/Platform specific tdm slot offset table
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]496* NOTE:
497* Each entry represents the slot offset array of one backend tdm device
498* valid offset represents the starting offset in byte for the channel
499* use 0xFFFF for end or unused slot offset entry.
500*****************************************************************************/
501static unsigned int tdm_rx_slot_offset_custom
502 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
503 {/* PRI TDM */
504 {0xFFFF}, /* not used */
505 {0xFFFF}, /* not used */
506 {0xFFFF}, /* not used */
507 {0xFFFF}, /* not used */
508 {0xFFFF}, /* not used */
509 {0xFFFF}, /* not used */
510 {0xFFFF}, /* not used */
511 {0xFFFF}, /* not used */
512 },
513 {/* SEC TDM */
514 {0, 2, 0xFFFF},
515 {4, 0xFFFF},
516 {6, 0xFFFF},
517 {8, 0xFFFF},
518 {10, 0xFFFF},
519 {12, 14, 16, 18, 20, 22, 24, 26, 0xFFFF},
520 {28, 30, 0xFFFF},
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]521 {30, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]522 },
523 {/* TERT TDM */
524 {0, 2, 0xFFFF},
525 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
526 {20, 22, 24, 26, 28, 30, 0xFFFF},
527 {0xFFFF}, /* not used */
528 {0xFFFF}, /* not used */
529 {0xFFFF}, /* not used */
530 {0xFFFF}, /* not used */
531 {0xFFFF}, /* not used */
532 },
533 {/* QUAT TDM */
534 {0xFFFF}, /* not used */
535 {0xFFFF}, /* not used */
536 {0xFFFF}, /* not used */
537 {0xFFFF}, /* not used */
538 {0xFFFF}, /* not used */
539 {0xFFFF}, /* not used */
540 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]541 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]542 },
543 {/* QUIN TDM */
544 {0xFFFF}, /* not used */
545 {0xFFFF}, /* not used */
546 {0xFFFF}, /* not used */
547 {0xFFFF}, /* not used */
548 {0xFFFF}, /* not used */
549 {0xFFFF}, /* not used */
550 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]551 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]552 }
553};
554
555static unsigned int tdm_tx_slot_offset_custom
556 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
557 {/* PRI TDM */
558 {0xFFFF}, /* not used */
559 {0xFFFF}, /* not used */
560 {0xFFFF}, /* not used */
561 {0xFFFF}, /* not used */
562 {0xFFFF}, /* not used */
563 {0xFFFF}, /* not used */
564 {0xFFFF}, /* not used */
565 {0xFFFF}, /* not used */
566 },
567 {/* SEC TDM */
568 {0, 2, 0xFFFF},
569 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
570 {20, 22, 24, 26, 28, 30, 0xFFFF},
571 {0xFFFF}, /* not used */
572 {0xFFFF}, /* not used */
573 {0xFFFF}, /* not used */
574 {0xFFFF}, /* not used */
575 {0xFFFF}, /* not used */
576 },
577 {/* TERT TDM */
578 {0, 2, 4, 6, 8, 10, 12, 0xFFFF},
579 {14, 16, 0xFFFF},
580 {18, 20, 22, 24, 26, 28, 30, 0xFFFF},
581 {0xFFFF}, /* not used */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
584 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]585 {30, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]586 },
587 {/* QUAT TDM */
588 {0xFFFF}, /* not used */
589 {0xFFFF}, /* not used */
590 {0xFFFF}, /* not used */
591 {0xFFFF}, /* not used */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
594 {0xFFFF}, /* not used */
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]595 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]596 },
597 {/* QUIN TDM */
598 {0xFFFF}, /* not used */
599 {0xFFFF}, /* not used */
600 {0xFFFF}, /* not used */
601 {0xFFFF}, /* not used */
602 {0xFFFF}, /* not used */
603 {0xFFFF}, /* not used */
604 {0xFFFF}, /* not used */
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]605 {0, 0xFFFF},
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]606 }
607};
608
609
610static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
611 "S32_LE"};
612static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
613 "S24_3LE"};
614static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
615 "Five", "Six", "Seven",
616 "Eight"};
617static char const *ch_text[] = {"Two", "Three", "Four", "Five",
618 "Six", "Seven", "Eight"};
619static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
620 "KHZ_16", "KHZ_22P05",
621 "KHZ_32", "KHZ_44P1", "KHZ_48",
622 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
623 "KHZ_192", "KHZ_352P8", "KHZ_384"};
624static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
625 "KHZ_192", "KHZ_32", "KHZ_44P1",
626 "KHZ_88P2", "KHZ_176P4"};
627static char const *tdm_ch_text[] = {
628 "One", "Two", "Three", "Four",
629 "Five", "Six", "Seven", "Eight",
630 "Nine", "Ten", "Eleven", "Twelve",
631 "Thirteen", "Fourteen", "Fifteen", "Sixteen",
632 "Seventeen", "Eighteen", "Nineteen", "Twenty",
633 "TwentyOne", "TwentyTwo", "TwentyThree", "TwentyFour",
634 "TwentyFive", "TwentySix", "TwentySeven", "TwentyEight",
635 "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"};
636static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
637static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
638 "KHZ_48", "KHZ_176P4",
639 "KHZ_352P8"};
640static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
641 "Eight", "Sixteen", "ThirtyTwo"};
642static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
643static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
644static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
645 "KHZ_22P05", "KHZ_32", "KHZ_44P1",
646 "KHZ_48", "KHZ_96", "KHZ_192"};
647static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
648 "Five", "Six", "Seven",
649 "Eight"};
650static const char *const qos_text[] = {"Disable", "Enable"};
651
652static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
653static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
654static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
655static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
656static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
657static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
658static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
659static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
660static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
661static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
662 ext_disp_sample_rate_text);
663static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
664static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
665static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
666static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
667static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
668static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
669static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
670static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
671static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
672static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
673static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
674static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
675static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
676static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
677static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
678static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
679static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
680static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
681static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
682static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
683static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
684static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
685static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
686static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
687static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
688static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
689static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
690static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
691static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
692static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
693static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
694static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
695static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
696static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
697static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
698static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
699static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
700static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
701static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
702static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
703static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
704static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
705
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]706static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
707 {
708 AFE_API_VERSION_I2S_CONFIG,
709 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
710 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
711 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
712 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
713 0,
714 },
715 {
716 AFE_API_VERSION_I2S_CONFIG,
717 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
718 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
719 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
720 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
721 0,
722 },
723 {
724 AFE_API_VERSION_I2S_CONFIG,
725 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
726 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
727 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
728 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
729 0,
730 },
731 {
732 AFE_API_VERSION_I2S_CONFIG,
733 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
734 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
735 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
736 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
737 0,
738 },
739 {
740 AFE_API_VERSION_I2S_CONFIG,
741 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
742 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
743 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
744 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
745 0,
746 }
747
748};
749
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]750struct msm_asoc_mach_data {
751 struct msm_pinctrl_info pinctrl_info[TDM_INTERFACE_MAX];
752 struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
753 struct tdm_conf tdm_intf_conf[TDM_INTERFACE_MAX];
754};
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]755
756static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_value *ucontrol)
758{
759 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
760 usb_rx_cfg.channels);
761 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
762 return 0;
763}
764
765static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
766 struct snd_ctl_elem_value *ucontrol)
767{
768 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
769
770 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
771 return 1;
772}
773
774static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
775 struct snd_ctl_elem_value *ucontrol)
776{
777 int sample_rate_val;
778
779 switch (usb_rx_cfg.sample_rate) {
780 case SAMPLING_RATE_384KHZ:
781 sample_rate_val = 12;
782 break;
783 case SAMPLING_RATE_352P8KHZ:
784 sample_rate_val = 11;
785 break;
786 case SAMPLING_RATE_192KHZ:
787 sample_rate_val = 10;
788 break;
789 case SAMPLING_RATE_176P4KHZ:
790 sample_rate_val = 9;
791 break;
792 case SAMPLING_RATE_96KHZ:
793 sample_rate_val = 8;
794 break;
795 case SAMPLING_RATE_88P2KHZ:
796 sample_rate_val = 7;
797 break;
798 case SAMPLING_RATE_48KHZ:
799 sample_rate_val = 6;
800 break;
801 case SAMPLING_RATE_44P1KHZ:
802 sample_rate_val = 5;
803 break;
804 case SAMPLING_RATE_32KHZ:
805 sample_rate_val = 4;
806 break;
807 case SAMPLING_RATE_22P05KHZ:
808 sample_rate_val = 3;
809 break;
810 case SAMPLING_RATE_16KHZ:
811 sample_rate_val = 2;
812 break;
813 case SAMPLING_RATE_11P025KHZ:
814 sample_rate_val = 1;
815 break;
816 case SAMPLING_RATE_8KHZ:
817 default:
818 sample_rate_val = 0;
819 break;
820 }
821
822 ucontrol->value.integer.value[0] = sample_rate_val;
823 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
824 usb_rx_cfg.sample_rate);
825 return 0;
826}
827
828static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
829 struct snd_ctl_elem_value *ucontrol)
830{
831 switch (ucontrol->value.integer.value[0]) {
832 case 12:
833 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
834 break;
835 case 11:
836 usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
837 break;
838 case 10:
839 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
840 break;
841 case 9:
842 usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
843 break;
844 case 8:
845 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
846 break;
847 case 7:
848 usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
849 break;
850 case 6:
851 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
852 break;
853 case 5:
854 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
855 break;
856 case 4:
857 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
858 break;
859 case 3:
860 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
861 break;
862 case 2:
863 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
864 break;
865 case 1:
866 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
867 break;
868 case 0:
869 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
870 break;
871 default:
872 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
873 break;
874 }
875
876 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
877 __func__, ucontrol->value.integer.value[0],
878 usb_rx_cfg.sample_rate);
879 return 0;
880}
881
882static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_value *ucontrol)
884{
885 switch (usb_rx_cfg.bit_format) {
886 case SNDRV_PCM_FORMAT_S32_LE:
887 ucontrol->value.integer.value[0] = 3;
888 break;
889 case SNDRV_PCM_FORMAT_S24_3LE:
890 ucontrol->value.integer.value[0] = 2;
891 break;
892 case SNDRV_PCM_FORMAT_S24_LE:
893 ucontrol->value.integer.value[0] = 1;
894 break;
895 case SNDRV_PCM_FORMAT_S16_LE:
896 default:
897 ucontrol->value.integer.value[0] = 0;
898 break;
899 }
900
901 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
902 __func__, usb_rx_cfg.bit_format,
903 ucontrol->value.integer.value[0]);
904 return 0;
905}
906
907static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
908 struct snd_ctl_elem_value *ucontrol)
909{
910 int rc = 0;
911
912 switch (ucontrol->value.integer.value[0]) {
913 case 3:
914 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
915 break;
916 case 2:
917 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
918 break;
919 case 1:
920 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
921 break;
922 case 0:
923 default:
924 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
925 break;
926 }
927 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
928 __func__, usb_rx_cfg.bit_format,
929 ucontrol->value.integer.value[0]);
930
931 return rc;
932}
933
934static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936{
937 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
938 usb_tx_cfg.channels);
939 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
940 return 0;
941}
942
943static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
944 struct snd_ctl_elem_value *ucontrol)
945{
946 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
947
948 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
949 return 1;
950}
951
952static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
953 struct snd_ctl_elem_value *ucontrol)
954{
955 int sample_rate_val;
956
957 switch (usb_tx_cfg.sample_rate) {
958 case SAMPLING_RATE_384KHZ:
959 sample_rate_val = 12;
960 break;
961 case SAMPLING_RATE_352P8KHZ:
962 sample_rate_val = 11;
963 break;
964 case SAMPLING_RATE_192KHZ:
965 sample_rate_val = 10;
966 break;
967 case SAMPLING_RATE_176P4KHZ:
968 sample_rate_val = 9;
969 break;
970 case SAMPLING_RATE_96KHZ:
971 sample_rate_val = 8;
972 break;
973 case SAMPLING_RATE_88P2KHZ:
974 sample_rate_val = 7;
975 break;
976 case SAMPLING_RATE_48KHZ:
977 sample_rate_val = 6;
978 break;
979 case SAMPLING_RATE_44P1KHZ:
980 sample_rate_val = 5;
981 break;
982 case SAMPLING_RATE_32KHZ:
983 sample_rate_val = 4;
984 break;
985 case SAMPLING_RATE_22P05KHZ:
986 sample_rate_val = 3;
987 break;
988 case SAMPLING_RATE_16KHZ:
989 sample_rate_val = 2;
990 break;
991 case SAMPLING_RATE_11P025KHZ:
992 sample_rate_val = 1;
993 break;
994 case SAMPLING_RATE_8KHZ:
995 sample_rate_val = 0;
996 break;
997 default:
998 sample_rate_val = 6;
999 break;
1000 }
1001
1002 ucontrol->value.integer.value[0] = sample_rate_val;
1003 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
1004 usb_tx_cfg.sample_rate);
1005 return 0;
1006}
1007
1008static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1009 struct snd_ctl_elem_value *ucontrol)
1010{
1011 switch (ucontrol->value.integer.value[0]) {
1012 case 12:
1013 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
1014 break;
1015 case 11:
1016 usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
1017 break;
1018 case 10:
1019 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
1020 break;
1021 case 9:
1022 usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
1023 break;
1024 case 8:
1025 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
1026 break;
1027 case 7:
1028 usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
1029 break;
1030 case 6:
1031 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1032 break;
1033 case 5:
1034 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
1035 break;
1036 case 4:
1037 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
1038 break;
1039 case 3:
1040 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
1041 break;
1042 case 2:
1043 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
1044 break;
1045 case 1:
1046 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
1047 break;
1048 case 0:
1049 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
1050 break;
1051 default:
1052 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1053 break;
1054 }
1055
1056 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
1057 __func__, ucontrol->value.integer.value[0],
1058 usb_tx_cfg.sample_rate);
1059 return 0;
1060}
1061
1062static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
1063 struct snd_ctl_elem_value *ucontrol)
1064{
1065 switch (usb_tx_cfg.bit_format) {
1066 case SNDRV_PCM_FORMAT_S32_LE:
1067 ucontrol->value.integer.value[0] = 3;
1068 break;
1069 case SNDRV_PCM_FORMAT_S24_3LE:
1070 ucontrol->value.integer.value[0] = 2;
1071 break;
1072 case SNDRV_PCM_FORMAT_S24_LE:
1073 ucontrol->value.integer.value[0] = 1;
1074 break;
1075 case SNDRV_PCM_FORMAT_S16_LE:
1076 default:
1077 ucontrol->value.integer.value[0] = 0;
1078 break;
1079 }
1080
1081 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1082 __func__, usb_tx_cfg.bit_format,
1083 ucontrol->value.integer.value[0]);
1084 return 0;
1085}
1086
1087static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
1088 struct snd_ctl_elem_value *ucontrol)
1089{
1090 int rc = 0;
1091
1092 switch (ucontrol->value.integer.value[0]) {
1093 case 3:
1094 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
1095 break;
1096 case 2:
1097 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1098 break;
1099 case 1:
1100 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
1101 break;
1102 case 0:
1103 default:
1104 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
1105 break;
1106 }
1107 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1108 __func__, usb_tx_cfg.bit_format,
1109 ucontrol->value.integer.value[0]);
1110
1111 return rc;
1112}
1113
1114static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
1115{
1116 int idx = 0;
1117
1118 if (strnstr(kcontrol->id.name, "Display Port RX",
1119 sizeof("Display Port RX"))) {
1120 idx = DP_RX_IDX;
1121 } else {
1122 pr_err("%s: unsupported BE: %s\n",
1123 __func__, kcontrol->id.name);
1124 idx = -EINVAL;
1125 }
1126
1127 return idx;
1128}
1129
1130static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
1131 struct snd_ctl_elem_value *ucontrol)
1132{
1133 int idx = ext_disp_get_port_idx(kcontrol);
1134
1135 if (idx < 0)
1136 return idx;
1137
1138 switch (ext_disp_rx_cfg[idx].bit_format) {
1139 case SNDRV_PCM_FORMAT_S24_3LE:
1140 ucontrol->value.integer.value[0] = 2;
1141 break;
1142 case SNDRV_PCM_FORMAT_S24_LE:
1143 ucontrol->value.integer.value[0] = 1;
1144 break;
1145 case SNDRV_PCM_FORMAT_S16_LE:
1146 default:
1147 ucontrol->value.integer.value[0] = 0;
1148 break;
1149 }
1150
1151 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1152 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1153 ucontrol->value.integer.value[0]);
1154 return 0;
1155}
1156
1157static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
1158 struct snd_ctl_elem_value *ucontrol)
1159{
1160 int idx = ext_disp_get_port_idx(kcontrol);
1161
1162 if (idx < 0)
1163 return idx;
1164
1165 switch (ucontrol->value.integer.value[0]) {
1166 case 2:
1167 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1168 break;
1169 case 1:
1170 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1171 break;
1172 case 0:
1173 default:
1174 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1175 break;
1176 }
1177 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1178 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1179 ucontrol->value.integer.value[0]);
1180
1181 return 0;
1182}
1183
1184static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
1185 struct snd_ctl_elem_value *ucontrol)
1186{
1187 int idx = ext_disp_get_port_idx(kcontrol);
1188
1189 if (idx < 0)
1190 return idx;
1191
1192 ucontrol->value.integer.value[0] =
1193 ext_disp_rx_cfg[idx].channels - 2;
1194
1195 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1196 idx, ext_disp_rx_cfg[idx].channels);
1197
1198 return 0;
1199}
1200
1201static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
1202 struct snd_ctl_elem_value *ucontrol)
1203{
1204 int idx = ext_disp_get_port_idx(kcontrol);
1205
1206 if (idx < 0)
1207 return idx;
1208
1209 ext_disp_rx_cfg[idx].channels =
1210 ucontrol->value.integer.value[0] + 2;
1211
1212 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1213 idx, ext_disp_rx_cfg[idx].channels);
1214 return 1;
1215}
1216
1217static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1218 struct snd_ctl_elem_value *ucontrol)
1219{
1220 int sample_rate_val;
1221 int idx = ext_disp_get_port_idx(kcontrol);
1222
1223 if (idx < 0)
1224 return idx;
1225
1226 switch (ext_disp_rx_cfg[idx].sample_rate) {
1227 case SAMPLING_RATE_176P4KHZ:
1228 sample_rate_val = 6;
1229 break;
1230
1231 case SAMPLING_RATE_88P2KHZ:
1232 sample_rate_val = 5;
1233 break;
1234
1235 case SAMPLING_RATE_44P1KHZ:
1236 sample_rate_val = 4;
1237 break;
1238
1239 case SAMPLING_RATE_32KHZ:
1240 sample_rate_val = 3;
1241 break;
1242
1243 case SAMPLING_RATE_192KHZ:
1244 sample_rate_val = 2;
1245 break;
1246
1247 case SAMPLING_RATE_96KHZ:
1248 sample_rate_val = 1;
1249 break;
1250
1251 case SAMPLING_RATE_48KHZ:
1252 default:
1253 sample_rate_val = 0;
1254 break;
1255 }
1256
1257 ucontrol->value.integer.value[0] = sample_rate_val;
1258 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
1259 idx, ext_disp_rx_cfg[idx].sample_rate);
1260
1261 return 0;
1262}
1263
1264static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1265 struct snd_ctl_elem_value *ucontrol)
1266{
1267 int idx = ext_disp_get_port_idx(kcontrol);
1268
1269 if (idx < 0)
1270 return idx;
1271
1272 switch (ucontrol->value.integer.value[0]) {
1273 case 6:
1274 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
1275 break;
1276 case 5:
1277 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
1278 break;
1279 case 4:
1280 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
1281 break;
1282 case 3:
1283 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
1284 break;
1285 case 2:
1286 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
1287 break;
1288 case 1:
1289 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
1290 break;
1291 case 0:
1292 default:
1293 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
1294 break;
1295 }
1296
1297 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
1298 __func__, ucontrol->value.integer.value[0], idx,
1299 ext_disp_rx_cfg[idx].sample_rate);
1300 return 0;
1301}
1302
1303static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1304 struct snd_ctl_elem_value *ucontrol)
1305{
1306 pr_debug("%s: proxy_rx channels = %d\n",
1307 __func__, proxy_rx_cfg.channels);
1308 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1309
1310 return 0;
1311}
1312
1313static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1314 struct snd_ctl_elem_value *ucontrol)
1315{
1316 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1317 pr_debug("%s: proxy_rx channels = %d\n",
1318 __func__, proxy_rx_cfg.channels);
1319
1320 return 1;
1321}
1322
1323static int tdm_get_sample_rate(int value)
1324{
1325 int sample_rate = 0;
1326
1327 switch (value) {
1328 case 0:
1329 sample_rate = SAMPLING_RATE_8KHZ;
1330 break;
1331 case 1:
1332 sample_rate = SAMPLING_RATE_16KHZ;
1333 break;
1334 case 2:
1335 sample_rate = SAMPLING_RATE_32KHZ;
1336 break;
1337 case 3:
1338 sample_rate = SAMPLING_RATE_48KHZ;
1339 break;
1340 case 4:
1341 sample_rate = SAMPLING_RATE_176P4KHZ;
1342 break;
1343 case 5:
1344 sample_rate = SAMPLING_RATE_352P8KHZ;
1345 break;
1346 default:
1347 sample_rate = SAMPLING_RATE_48KHZ;
1348 break;
1349 }
1350 return sample_rate;
1351}
1352
1353static int aux_pcm_get_sample_rate(int value)
1354{
1355 int sample_rate;
1356
1357 switch (value) {
1358 case 1:
1359 sample_rate = SAMPLING_RATE_16KHZ;
1360 break;
1361 case 0:
1362 default:
1363 sample_rate = SAMPLING_RATE_8KHZ;
1364 break;
1365 }
1366 return sample_rate;
1367}
1368
1369static int tdm_get_sample_rate_val(int sample_rate)
1370{
1371 int sample_rate_val = 0;
1372
1373 switch (sample_rate) {
1374 case SAMPLING_RATE_8KHZ:
1375 sample_rate_val = 0;
1376 break;
1377 case SAMPLING_RATE_16KHZ:
1378 sample_rate_val = 1;
1379 break;
1380 case SAMPLING_RATE_32KHZ:
1381 sample_rate_val = 2;
1382 break;
1383 case SAMPLING_RATE_48KHZ:
1384 sample_rate_val = 3;
1385 break;
1386 case SAMPLING_RATE_176P4KHZ:
1387 sample_rate_val = 4;
1388 break;
1389 case SAMPLING_RATE_352P8KHZ:
1390 sample_rate_val = 5;
1391 break;
1392 default:
1393 sample_rate_val = 3;
1394 break;
1395 }
1396 return sample_rate_val;
1397}
1398
1399static int aux_pcm_get_sample_rate_val(int sample_rate)
1400{
1401 int sample_rate_val = 0;
1402
1403 switch (sample_rate) {
1404 case SAMPLING_RATE_16KHZ:
1405 sample_rate_val = 1;
1406 break;
1407 case SAMPLING_RATE_8KHZ:
1408 default:
1409 sample_rate_val = 0;
1410 break;
1411 }
1412 return sample_rate_val;
1413}
1414
1415static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1416{
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1417 int mode = -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1418
1419 if (strnstr(kcontrol->id.name, "PRI",
1420 sizeof(kcontrol->id.name))) {
1421 mode = TDM_PRI;
1422 } else if (strnstr(kcontrol->id.name, "SEC",
1423 sizeof(kcontrol->id.name))) {
1424 mode = TDM_SEC;
1425 } else if (strnstr(kcontrol->id.name, "TERT",
1426 sizeof(kcontrol->id.name))) {
1427 mode = TDM_TERT;
1428 } else if (strnstr(kcontrol->id.name, "QUAT",
1429 sizeof(kcontrol->id.name))) {
1430 mode = TDM_QUAT;
1431 } else if (strnstr(kcontrol->id.name, "QUIN",
1432 sizeof(kcontrol->id.name))) {
1433 mode = TDM_QUIN;
1434 } else {
1435 pr_err("%s: unsupported mode in: %s",
1436 __func__, kcontrol->id.name);
1437 mode = -EINVAL;
1438 }
1439
1440 return mode;
1441}
1442
1443static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1444{
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1445 int channel = -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1446
1447 if (strnstr(kcontrol->id.name, "RX_0",
1448 sizeof(kcontrol->id.name)) ||
1449 strnstr(kcontrol->id.name, "TX_0",
1450 sizeof(kcontrol->id.name))) {
1451 channel = TDM_0;
1452 } else if (strnstr(kcontrol->id.name, "RX_1",
1453 sizeof(kcontrol->id.name)) ||
1454 strnstr(kcontrol->id.name, "TX_1",
1455 sizeof(kcontrol->id.name))) {
1456 channel = TDM_1;
1457 } else if (strnstr(kcontrol->id.name, "RX_2",
1458 sizeof(kcontrol->id.name)) ||
1459 strnstr(kcontrol->id.name, "TX_2",
1460 sizeof(kcontrol->id.name))) {
1461 channel = TDM_2;
1462 } else if (strnstr(kcontrol->id.name, "RX_3",
1463 sizeof(kcontrol->id.name)) ||
1464 strnstr(kcontrol->id.name, "TX_3",
1465 sizeof(kcontrol->id.name))) {
1466 channel = TDM_3;
1467 } else if (strnstr(kcontrol->id.name, "RX_4",
1468 sizeof(kcontrol->id.name)) ||
1469 strnstr(kcontrol->id.name, "TX_4",
1470 sizeof(kcontrol->id.name))) {
1471 channel = TDM_4;
1472 } else if (strnstr(kcontrol->id.name, "RX_5",
1473 sizeof(kcontrol->id.name)) ||
1474 strnstr(kcontrol->id.name, "TX_5",
1475 sizeof(kcontrol->id.name))) {
1476 channel = TDM_5;
1477 } else if (strnstr(kcontrol->id.name, "RX_6",
1478 sizeof(kcontrol->id.name)) ||
1479 strnstr(kcontrol->id.name, "TX_6",
1480 sizeof(kcontrol->id.name))) {
1481 channel = TDM_6;
1482 } else if (strnstr(kcontrol->id.name, "RX_7",
1483 sizeof(kcontrol->id.name)) ||
1484 strnstr(kcontrol->id.name, "TX_7",
1485 sizeof(kcontrol->id.name))) {
1486 channel = TDM_7;
1487 } else {
1488 pr_err("%s: unsupported channel in: %s",
1489 __func__, kcontrol->id.name);
1490 channel = -EINVAL;
1491 }
1492
1493 return channel;
1494}
1495
1496static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
1497 struct tdm_port *port)
1498{
1499 if (port) {
1500 port->mode = tdm_get_mode(kcontrol);
1501 if (port->mode < 0)
1502 return port->mode;
1503
1504 port->channel = tdm_get_channel(kcontrol);
1505 if (port->channel < 0)
1506 return port->channel;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]1507 } else
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1508 return -EINVAL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1509 return 0;
1510}
1511
1512static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1513 struct snd_ctl_elem_value *ucontrol)
1514{
1515 struct tdm_port port;
1516 int ret = tdm_get_port_idx(kcontrol, &port);
1517
1518 if (ret) {
1519 pr_err("%s: unsupported control: %s\n",
1520 __func__, kcontrol->id.name);
1521 } else {
1522 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1523 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1524
1525 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1526 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1527 ucontrol->value.enumerated.item[0]);
1528 }
1529 return ret;
1530}
1531
1532static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1533 struct snd_ctl_elem_value *ucontrol)
1534{
1535 struct tdm_port port;
1536 int ret = tdm_get_port_idx(kcontrol, &port);
1537
1538 if (ret) {
1539 pr_err("%s: unsupported control: %s\n",
1540 __func__, kcontrol->id.name);
1541 } else {
1542 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1543 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1544
1545 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1546 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1547 ucontrol->value.enumerated.item[0]);
1548 }
1549 return ret;
1550}
1551
1552static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1553 struct snd_ctl_elem_value *ucontrol)
1554{
1555 struct tdm_port port;
1556 int ret = tdm_get_port_idx(kcontrol, &port);
1557
1558 if (ret) {
1559 pr_err("%s: unsupported control: %s",
1560 __func__, kcontrol->id.name);
1561 } else {
1562 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1563 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1564
1565 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1566 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1567 ucontrol->value.enumerated.item[0]);
1568 }
1569 return ret;
1570}
1571
1572static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1573 struct snd_ctl_elem_value *ucontrol)
1574{
1575 struct tdm_port port;
1576 int ret = tdm_get_port_idx(kcontrol, &port);
1577
1578 if (ret) {
1579 pr_err("%s: unsupported control: %s\n",
1580 __func__, kcontrol->id.name);
1581 } else {
1582 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1583 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1584
1585 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1586 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1587 ucontrol->value.enumerated.item[0]);
1588 }
1589 return ret;
1590}
1591
1592static int tdm_get_format(int value)
1593{
1594 int format = 0;
1595
1596 switch (value) {
1597 case 0:
1598 format = SNDRV_PCM_FORMAT_S16_LE;
1599 break;
1600 case 1:
1601 format = SNDRV_PCM_FORMAT_S24_LE;
1602 break;
1603 case 2:
1604 format = SNDRV_PCM_FORMAT_S32_LE;
1605 break;
1606 default:
1607 format = SNDRV_PCM_FORMAT_S16_LE;
1608 break;
1609 }
1610 return format;
1611}
1612
1613static int tdm_get_format_val(int format)
1614{
1615 int value = 0;
1616
1617 switch (format) {
1618 case SNDRV_PCM_FORMAT_S16_LE:
1619 value = 0;
1620 break;
1621 case SNDRV_PCM_FORMAT_S24_LE:
1622 value = 1;
1623 break;
1624 case SNDRV_PCM_FORMAT_S32_LE:
1625 value = 2;
1626 break;
1627 default:
1628 value = 0;
1629 break;
1630 }
1631 return value;
1632}
1633
1634static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1635 struct snd_ctl_elem_value *ucontrol)
1636{
1637 struct tdm_port port;
1638 int ret = tdm_get_port_idx(kcontrol, &port);
1639
1640 if (ret) {
1641 pr_err("%s: unsupported control: %s\n",
1642 __func__, kcontrol->id.name);
1643 } else {
1644 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1645 tdm_rx_cfg[port.mode][port.channel].bit_format);
1646
1647 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1648 tdm_rx_cfg[port.mode][port.channel].bit_format,
1649 ucontrol->value.enumerated.item[0]);
1650 }
1651 return ret;
1652}
1653
1654static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1655 struct snd_ctl_elem_value *ucontrol)
1656{
1657 struct tdm_port port;
1658 int ret = tdm_get_port_idx(kcontrol, &port);
1659
1660 if (ret) {
1661 pr_err("%s: unsupported control: %s\n",
1662 __func__, kcontrol->id.name);
1663 } else {
1664 tdm_rx_cfg[port.mode][port.channel].bit_format =
1665 tdm_get_format(ucontrol->value.enumerated.item[0]);
1666
1667 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1668 tdm_rx_cfg[port.mode][port.channel].bit_format,
1669 ucontrol->value.enumerated.item[0]);
1670 }
1671 return ret;
1672}
1673
1674static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1675 struct snd_ctl_elem_value *ucontrol)
1676{
1677 struct tdm_port port;
1678 int ret = tdm_get_port_idx(kcontrol, &port);
1679
1680 if (ret) {
1681 pr_err("%s: unsupported control: %s\n",
1682 __func__, kcontrol->id.name);
1683 } else {
1684 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1685 tdm_tx_cfg[port.mode][port.channel].bit_format);
1686
1687 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1688 tdm_tx_cfg[port.mode][port.channel].bit_format,
1689 ucontrol->value.enumerated.item[0]);
1690 }
1691 return ret;
1692}
1693
1694static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1695 struct snd_ctl_elem_value *ucontrol)
1696{
1697 struct tdm_port port;
1698 int ret = tdm_get_port_idx(kcontrol, &port);
1699
1700 if (ret) {
1701 pr_err("%s: unsupported control: %s\n",
1702 __func__, kcontrol->id.name);
1703 } else {
1704 tdm_tx_cfg[port.mode][port.channel].bit_format =
1705 tdm_get_format(ucontrol->value.enumerated.item[0]);
1706
1707 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1708 tdm_tx_cfg[port.mode][port.channel].bit_format,
1709 ucontrol->value.enumerated.item[0]);
1710 }
1711 return ret;
1712}
1713
1714static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1715 struct snd_ctl_elem_value *ucontrol)
1716{
1717 struct tdm_port port;
1718 int ret = tdm_get_port_idx(kcontrol, &port);
1719
1720 if (ret) {
1721 pr_err("%s: unsupported control: %s\n",
1722 __func__, kcontrol->id.name);
1723 } else {
1724
1725 ucontrol->value.enumerated.item[0] =
1726 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1727
1728 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1729 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1730 ucontrol->value.enumerated.item[0]);
1731 }
1732 return ret;
1733}
1734
1735static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1736 struct snd_ctl_elem_value *ucontrol)
1737{
1738 struct tdm_port port;
1739 int ret = tdm_get_port_idx(kcontrol, &port);
1740
1741 if (ret) {
1742 pr_err("%s: unsupported control: %s\n",
1743 __func__, kcontrol->id.name);
1744 } else {
1745 tdm_rx_cfg[port.mode][port.channel].channels =
1746 ucontrol->value.enumerated.item[0] + 1;
1747
1748 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1749 tdm_rx_cfg[port.mode][port.channel].channels,
1750 ucontrol->value.enumerated.item[0] + 1);
1751 }
1752 return ret;
1753}
1754
1755static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1756 struct snd_ctl_elem_value *ucontrol)
1757{
1758 struct tdm_port port;
1759 int ret = tdm_get_port_idx(kcontrol, &port);
1760
1761 if (ret) {
1762 pr_err("%s: unsupported control: %s\n",
1763 __func__, kcontrol->id.name);
1764 } else {
1765 ucontrol->value.enumerated.item[0] =
1766 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1767
1768 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1769 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1770 ucontrol->value.enumerated.item[0]);
1771 }
1772 return ret;
1773}
1774
1775static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1776 struct snd_ctl_elem_value *ucontrol)
1777{
1778 struct tdm_port port;
1779 int ret = tdm_get_port_idx(kcontrol, &port);
1780
1781 if (ret) {
1782 pr_err("%s: unsupported control: %s\n",
1783 __func__, kcontrol->id.name);
1784 } else {
1785 tdm_tx_cfg[port.mode][port.channel].channels =
1786 ucontrol->value.enumerated.item[0] + 1;
1787
1788 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1789 tdm_tx_cfg[port.mode][port.channel].channels,
1790 ucontrol->value.enumerated.item[0] + 1);
1791 }
1792 return ret;
1793}
1794
1795static int tdm_get_slot_num_val(int slot_num)
1796{
1797 int slot_num_val = 0;
1798
1799 switch (slot_num) {
1800 case 1:
1801 slot_num_val = 0;
1802 break;
1803 case 2:
1804 slot_num_val = 1;
1805 break;
1806 case 4:
1807 slot_num_val = 2;
1808 break;
1809 case 8:
1810 slot_num_val = 3;
1811 break;
1812 case 16:
1813 slot_num_val = 4;
1814 break;
1815 case 32:
1816 slot_num_val = 5;
1817 break;
1818 default:
1819 slot_num_val = 5;
1820 break;
1821 }
1822 return slot_num_val;
1823}
1824
1825static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1826 struct snd_ctl_elem_value *ucontrol)
1827{
1828 int mode = tdm_get_mode(kcontrol);
1829
1830 if (mode < 0) {
1831 pr_err("%s: unsupported control: %s\n",
1832 __func__, kcontrol->id.name);
1833 return mode;
1834 }
1835
1836 ucontrol->value.enumerated.item[0] =
1837 tdm_get_slot_num_val(tdm_slot[mode].num);
1838
1839 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1840 mode, tdm_slot[mode].num,
1841 ucontrol->value.enumerated.item[0]);
1842
1843 return 0;
1844}
1845
1846static int tdm_get_slot_num(int value)
1847{
1848 int slot_num = 0;
1849
1850 switch (value) {
1851 case 0:
1852 slot_num = 1;
1853 break;
1854 case 1:
1855 slot_num = 2;
1856 break;
1857 case 2:
1858 slot_num = 4;
1859 break;
1860 case 3:
1861 slot_num = 8;
1862 break;
1863 case 4:
1864 slot_num = 16;
1865 break;
1866 case 5:
1867 slot_num = 32;
1868 break;
1869 default:
1870 slot_num = 8;
1871 break;
1872 }
1873 return slot_num;
1874}
1875
1876static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1877 struct snd_ctl_elem_value *ucontrol)
1878{
1879 int mode = tdm_get_mode(kcontrol);
1880
1881 if (mode < 0) {
1882 pr_err("%s: unsupported control: %s\n",
1883 __func__, kcontrol->id.name);
1884 return mode;
1885 }
1886
1887 tdm_slot[mode].num =
1888 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1889
1890 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1891 mode, tdm_slot[mode].num,
1892 ucontrol->value.enumerated.item[0]);
1893
1894 return 0;
1895}
1896
1897static int tdm_get_slot_width_val(int slot_width)
1898{
1899 int slot_width_val = 2;
1900
1901 switch (slot_width) {
1902 case 16:
1903 slot_width_val = 0;
1904 break;
1905 case 24:
1906 slot_width_val = 1;
1907 break;
1908 case 32:
1909 slot_width_val = 2;
1910 break;
1911 default:
1912 slot_width_val = 2;
1913 break;
1914 }
1915 return slot_width_val;
1916}
1917
1918static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1919 struct snd_ctl_elem_value *ucontrol)
1920{
1921 int mode = tdm_get_mode(kcontrol);
1922
1923 if (mode < 0) {
1924 pr_err("%s: unsupported control: %s\n",
1925 __func__, kcontrol->id.name);
1926 return mode;
1927 }
1928
1929 ucontrol->value.enumerated.item[0] =
1930 tdm_get_slot_width_val(tdm_slot[mode].width);
1931
1932 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1933 mode, tdm_slot[mode].width,
1934 ucontrol->value.enumerated.item[0]);
1935
1936 return 0;
1937}
1938
1939static int tdm_get_slot_width(int value)
1940{
1941 int slot_width = 32;
1942
1943 switch (value) {
1944 case 0:
1945 slot_width = 16;
1946 break;
1947 case 1:
1948 slot_width = 24;
1949 break;
1950 case 2:
1951 slot_width = 32;
1952 break;
1953 default:
1954 slot_width = 32;
1955 break;
1956 }
1957 return slot_width;
1958}
1959
1960static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1961 struct snd_ctl_elem_value *ucontrol)
1962{
1963 int mode = tdm_get_mode(kcontrol);
1964
1965 if (mode < 0) {
1966 pr_err("%s: unsupported control: %s\n",
1967 __func__, kcontrol->id.name);
1968 return mode;
1969 }
1970
1971 tdm_slot[mode].width =
1972 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
1973
1974 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1975 mode, tdm_slot[mode].width,
1976 ucontrol->value.enumerated.item[0]);
1977
1978 return 0;
1979}
1980
1981static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1982 struct snd_ctl_elem_value *ucontrol)
1983{
1984 unsigned int *slot_offset;
1985 int i;
1986 struct tdm_port port;
1987 int ret = tdm_get_port_idx(kcontrol, &port);
1988
1989 if (ret) {
1990 pr_err("%s: unsupported control: %s\n",
1991 __func__, kcontrol->id.name);
1992 } else {
1993 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
1994 pr_debug("%s: mode = %d, channel = %d\n",
1995 __func__, port.mode, port.channel);
1996 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1997 ucontrol->value.integer.value[i] = slot_offset[i];
1998 pr_debug("%s: offset %d, value %d\n",
1999 __func__, i, slot_offset[i]);
2000 }
2001 }
2002 return ret;
2003}
2004
2005static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2006 struct snd_ctl_elem_value *ucontrol)
2007{
2008 unsigned int *slot_offset;
2009 int i;
2010 struct tdm_port port;
2011 int ret = tdm_get_port_idx(kcontrol, &port);
2012
2013 if (ret) {
2014 pr_err("%s: unsupported control: %s\n",
2015 __func__, kcontrol->id.name);
2016 } else {
2017 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
2018 pr_debug("%s: mode = %d, channel = %d\n",
2019 __func__, port.mode, port.channel);
2020 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2021 slot_offset[i] = ucontrol->value.integer.value[i];
2022 pr_debug("%s: offset %d, value %d\n",
2023 __func__, i, slot_offset[i]);
2024 }
2025 }
2026 return ret;
2027}
2028
2029static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2030 struct snd_ctl_elem_value *ucontrol)
2031{
2032 unsigned int *slot_offset;
2033 int i;
2034 struct tdm_port port;
2035 int ret = tdm_get_port_idx(kcontrol, &port);
2036
2037 if (ret) {
2038 pr_err("%s: unsupported control: %s\n",
2039 __func__, kcontrol->id.name);
2040 } else {
2041 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2042 pr_debug("%s: mode = %d, channel = %d\n",
2043 __func__, port.mode, port.channel);
2044 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2045 ucontrol->value.integer.value[i] = slot_offset[i];
2046 pr_debug("%s: offset %d, value %d\n",
2047 __func__, i, slot_offset[i]);
2048 }
2049 }
2050 return ret;
2051}
2052
2053static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2054 struct snd_ctl_elem_value *ucontrol)
2055{
2056 unsigned int *slot_offset;
2057 int i;
2058 struct tdm_port port;
2059 int ret = tdm_get_port_idx(kcontrol, &port);
2060
2061 if (ret) {
2062 pr_err("%s: unsupported control: %s\n",
2063 __func__, kcontrol->id.name);
2064 } else {
2065 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2066 pr_debug("%s: mode = %d, channel = %d\n",
2067 __func__, port.mode, port.channel);
2068 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2069 slot_offset[i] = ucontrol->value.integer.value[i];
2070 pr_debug("%s: offset %d, value %d\n",
2071 __func__, i, slot_offset[i]);
2072 }
2073 }
2074 return ret;
2075}
2076
2077static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2078{
2079 int idx;
2080
2081 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2082 sizeof("PRIM_AUX_PCM")))
2083 idx = PRIM_AUX_PCM;
2084 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2085 sizeof("SEC_AUX_PCM")))
2086 idx = SEC_AUX_PCM;
2087 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2088 sizeof("TERT_AUX_PCM")))
2089 idx = TERT_AUX_PCM;
2090 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2091 sizeof("QUAT_AUX_PCM")))
2092 idx = QUAT_AUX_PCM;
2093 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2094 sizeof("QUIN_AUX_PCM")))
2095 idx = QUIN_AUX_PCM;
2096 else {
2097 pr_err("%s: unsupported port: %s\n",
2098 __func__, kcontrol->id.name);
2099 idx = -EINVAL;
2100 }
2101
2102 return idx;
2103}
2104
2105static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2106 struct snd_ctl_elem_value *ucontrol)
2107{
2108 int idx = aux_pcm_get_port_idx(kcontrol);
2109
2110 if (idx < 0)
2111 return idx;
2112
2113 aux_pcm_rx_cfg[idx].sample_rate =
2114 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2115
2116 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2117 idx, aux_pcm_rx_cfg[idx].sample_rate,
2118 ucontrol->value.enumerated.item[0]);
2119
2120 return 0;
2121}
2122
2123static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2124 struct snd_ctl_elem_value *ucontrol)
2125{
2126 int idx = aux_pcm_get_port_idx(kcontrol);
2127
2128 if (idx < 0)
2129 return idx;
2130
2131 ucontrol->value.enumerated.item[0] =
2132 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2133
2134 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2135 idx, aux_pcm_rx_cfg[idx].sample_rate,
2136 ucontrol->value.enumerated.item[0]);
2137
2138 return 0;
2139}
2140
2141static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2142 struct snd_ctl_elem_value *ucontrol)
2143{
2144 int idx = aux_pcm_get_port_idx(kcontrol);
2145
2146 if (idx < 0)
2147 return idx;
2148
2149 aux_pcm_tx_cfg[idx].sample_rate =
2150 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2151
2152 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2153 idx, aux_pcm_tx_cfg[idx].sample_rate,
2154 ucontrol->value.enumerated.item[0]);
2155
2156 return 0;
2157}
2158
2159static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2160 struct snd_ctl_elem_value *ucontrol)
2161{
2162 int idx = aux_pcm_get_port_idx(kcontrol);
2163
2164 if (idx < 0)
2165 return idx;
2166
2167 ucontrol->value.enumerated.item[0] =
2168 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2169
2170 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2171 idx, aux_pcm_tx_cfg[idx].sample_rate,
2172 ucontrol->value.enumerated.item[0]);
2173
2174 return 0;
2175}
2176
2177static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2178{
2179 int idx;
2180
2181 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2182 sizeof("PRIM_MI2S_RX")))
2183 idx = PRIM_MI2S;
2184 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2185 sizeof("SEC_MI2S_RX")))
2186 idx = SEC_MI2S;
2187 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2188 sizeof("TERT_MI2S_RX")))
2189 idx = TERT_MI2S;
2190 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2191 sizeof("QUAT_MI2S_RX")))
2192 idx = QUAT_MI2S;
2193 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2194 sizeof("QUIN_MI2S_RX")))
2195 idx = QUIN_MI2S;
2196 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2197 sizeof("PRIM_MI2S_TX")))
2198 idx = PRIM_MI2S;
2199 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2200 sizeof("SEC_MI2S_TX")))
2201 idx = SEC_MI2S;
2202 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2203 sizeof("TERT_MI2S_TX")))
2204 idx = TERT_MI2S;
2205 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2206 sizeof("QUAT_MI2S_TX")))
2207 idx = QUAT_MI2S;
2208 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2209 sizeof("QUIN_MI2S_TX")))
2210 idx = QUIN_MI2S;
2211 else {
2212 pr_err("%s: unsupported channel: %s\n",
2213 __func__, kcontrol->id.name);
2214 idx = -EINVAL;
2215 }
2216
2217 return idx;
2218}
2219
2220static int mi2s_get_sample_rate_val(int sample_rate)
2221{
2222 int sample_rate_val;
2223
2224 switch (sample_rate) {
2225 case SAMPLING_RATE_8KHZ:
2226 sample_rate_val = 0;
2227 break;
2228 case SAMPLING_RATE_11P025KHZ:
2229 sample_rate_val = 1;
2230 break;
2231 case SAMPLING_RATE_16KHZ:
2232 sample_rate_val = 2;
2233 break;
2234 case SAMPLING_RATE_22P05KHZ:
2235 sample_rate_val = 3;
2236 break;
2237 case SAMPLING_RATE_32KHZ:
2238 sample_rate_val = 4;
2239 break;
2240 case SAMPLING_RATE_44P1KHZ:
2241 sample_rate_val = 5;
2242 break;
2243 case SAMPLING_RATE_48KHZ:
2244 sample_rate_val = 6;
2245 break;
2246 case SAMPLING_RATE_96KHZ:
2247 sample_rate_val = 7;
2248 break;
2249 case SAMPLING_RATE_192KHZ:
2250 sample_rate_val = 8;
2251 break;
2252 default:
2253 sample_rate_val = 6;
2254 break;
2255 }
2256 return sample_rate_val;
2257}
2258
2259static int mi2s_get_sample_rate(int value)
2260{
2261 int sample_rate;
2262
2263 switch (value) {
2264 case 0:
2265 sample_rate = SAMPLING_RATE_8KHZ;
2266 break;
2267 case 1:
2268 sample_rate = SAMPLING_RATE_11P025KHZ;
2269 break;
2270 case 2:
2271 sample_rate = SAMPLING_RATE_16KHZ;
2272 break;
2273 case 3:
2274 sample_rate = SAMPLING_RATE_22P05KHZ;
2275 break;
2276 case 4:
2277 sample_rate = SAMPLING_RATE_32KHZ;
2278 break;
2279 case 5:
2280 sample_rate = SAMPLING_RATE_44P1KHZ;
2281 break;
2282 case 6:
2283 sample_rate = SAMPLING_RATE_48KHZ;
2284 break;
2285 case 7:
2286 sample_rate = SAMPLING_RATE_96KHZ;
2287 break;
2288 case 8:
2289 sample_rate = SAMPLING_RATE_192KHZ;
2290 break;
2291 default:
2292 sample_rate = SAMPLING_RATE_48KHZ;
2293 break;
2294 }
2295 return sample_rate;
2296}
2297
2298static int mi2s_auxpcm_get_format(int value)
2299{
2300 int format;
2301
2302 switch (value) {
2303 case 0:
2304 format = SNDRV_PCM_FORMAT_S16_LE;
2305 break;
2306 case 1:
2307 format = SNDRV_PCM_FORMAT_S24_LE;
2308 break;
2309 case 2:
2310 format = SNDRV_PCM_FORMAT_S24_3LE;
2311 break;
2312 case 3:
2313 format = SNDRV_PCM_FORMAT_S32_LE;
2314 break;
2315 default:
2316 format = SNDRV_PCM_FORMAT_S16_LE;
2317 break;
2318 }
2319 return format;
2320}
2321
2322static int mi2s_auxpcm_get_format_value(int format)
2323{
2324 int value;
2325
2326 switch (format) {
2327 case SNDRV_PCM_FORMAT_S16_LE:
2328 value = 0;
2329 break;
2330 case SNDRV_PCM_FORMAT_S24_LE:
2331 value = 1;
2332 break;
2333 case SNDRV_PCM_FORMAT_S24_3LE:
2334 value = 2;
2335 break;
2336 case SNDRV_PCM_FORMAT_S32_LE:
2337 value = 3;
2338 break;
2339 default:
2340 value = 0;
2341 break;
2342 }
2343 return value;
2344}
2345
2346static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2347 struct snd_ctl_elem_value *ucontrol)
2348{
2349 int idx = mi2s_get_port_idx(kcontrol);
2350
2351 if (idx < 0)
2352 return idx;
2353
2354 mi2s_rx_cfg[idx].sample_rate =
2355 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2356
2357 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2358 idx, mi2s_rx_cfg[idx].sample_rate,
2359 ucontrol->value.enumerated.item[0]);
2360
2361 return 0;
2362}
2363
2364static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2365 struct snd_ctl_elem_value *ucontrol)
2366{
2367 int idx = mi2s_get_port_idx(kcontrol);
2368
2369 if (idx < 0)
2370 return idx;
2371
2372 ucontrol->value.enumerated.item[0] =
2373 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2374
2375 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2376 idx, mi2s_rx_cfg[idx].sample_rate,
2377 ucontrol->value.enumerated.item[0]);
2378
2379 return 0;
2380}
2381
2382static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2383 struct snd_ctl_elem_value *ucontrol)
2384{
2385 int idx = mi2s_get_port_idx(kcontrol);
2386
2387 if (idx < 0)
2388 return idx;
2389
2390 mi2s_tx_cfg[idx].sample_rate =
2391 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2392
2393 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2394 idx, mi2s_tx_cfg[idx].sample_rate,
2395 ucontrol->value.enumerated.item[0]);
2396
2397 return 0;
2398}
2399
2400static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2401 struct snd_ctl_elem_value *ucontrol)
2402{
2403 int idx = mi2s_get_port_idx(kcontrol);
2404
2405 if (idx < 0)
2406 return idx;
2407
2408 ucontrol->value.enumerated.item[0] =
2409 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2410
2411 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2412 idx, mi2s_tx_cfg[idx].sample_rate,
2413 ucontrol->value.enumerated.item[0]);
2414
2415 return 0;
2416}
2417
2418static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2419 struct snd_ctl_elem_value *ucontrol)
2420{
2421 int idx = mi2s_get_port_idx(kcontrol);
2422
2423 if (idx < 0)
2424 return idx;
2425
2426 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2427 idx, mi2s_rx_cfg[idx].channels);
2428 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2429
2430 return 0;
2431}
2432
2433static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2434 struct snd_ctl_elem_value *ucontrol)
2435{
2436 int idx = mi2s_get_port_idx(kcontrol);
2437
2438 if (idx < 0)
2439 return idx;
2440
2441 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2442 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2443 idx, mi2s_rx_cfg[idx].channels);
2444
2445 return 1;
2446}
2447
2448static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2449 struct snd_ctl_elem_value *ucontrol)
2450{
2451 int idx = mi2s_get_port_idx(kcontrol);
2452
2453 if (idx < 0)
2454 return idx;
2455
2456 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2457 idx, mi2s_tx_cfg[idx].channels);
2458 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2459
2460 return 0;
2461}
2462
2463static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2464 struct snd_ctl_elem_value *ucontrol)
2465{
2466 int idx = mi2s_get_port_idx(kcontrol);
2467
2468 if (idx < 0)
2469 return idx;
2470
2471 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2472 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2473 idx, mi2s_tx_cfg[idx].channels);
2474
2475 return 1;
2476}
2477
2478static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2479 struct snd_ctl_elem_value *ucontrol)
2480{
2481 int idx = mi2s_get_port_idx(kcontrol);
2482
2483 if (idx < 0)
2484 return idx;
2485
2486 ucontrol->value.enumerated.item[0] =
2487 mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
2488
2489 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2490 idx, mi2s_rx_cfg[idx].bit_format,
2491 ucontrol->value.enumerated.item[0]);
2492
2493 return 0;
2494}
2495
2496static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2497 struct snd_ctl_elem_value *ucontrol)
2498{
2499 int idx = mi2s_get_port_idx(kcontrol);
2500
2501 if (idx < 0)
2502 return idx;
2503
2504 mi2s_rx_cfg[idx].bit_format =
2505 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2506
2507 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2508 idx, mi2s_rx_cfg[idx].bit_format,
2509 ucontrol->value.enumerated.item[0]);
2510
2511 return 0;
2512}
2513
2514static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2515 struct snd_ctl_elem_value *ucontrol)
2516{
2517 int idx = mi2s_get_port_idx(kcontrol);
2518
2519 if (idx < 0)
2520 return idx;
2521
2522 ucontrol->value.enumerated.item[0] =
2523 mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
2524
2525 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2526 idx, mi2s_tx_cfg[idx].bit_format,
2527 ucontrol->value.enumerated.item[0]);
2528
2529 return 0;
2530}
2531
2532static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2533 struct snd_ctl_elem_value *ucontrol)
2534{
2535 int idx = mi2s_get_port_idx(kcontrol);
2536
2537 if (idx < 0)
2538 return idx;
2539
2540 mi2s_tx_cfg[idx].bit_format =
2541 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2542
2543 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2544 idx, mi2s_tx_cfg[idx].bit_format,
2545 ucontrol->value.enumerated.item[0]);
2546
2547 return 0;
2548}
2549
2550static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
2551 struct snd_ctl_elem_value *ucontrol)
2552{
2553 int idx = aux_pcm_get_port_idx(kcontrol);
2554
2555 if (idx < 0)
2556 return idx;
2557
2558 ucontrol->value.enumerated.item[0] =
2559 mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
2560
2561 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2562 idx, aux_pcm_rx_cfg[idx].bit_format,
2563 ucontrol->value.enumerated.item[0]);
2564
2565 return 0;
2566}
2567
2568static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
2569 struct snd_ctl_elem_value *ucontrol)
2570{
2571 int idx = aux_pcm_get_port_idx(kcontrol);
2572
2573 if (idx < 0)
2574 return idx;
2575
2576 aux_pcm_rx_cfg[idx].bit_format =
2577 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2578
2579 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2580 idx, aux_pcm_rx_cfg[idx].bit_format,
2581 ucontrol->value.enumerated.item[0]);
2582
2583 return 0;
2584}
2585
2586static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
2587 struct snd_ctl_elem_value *ucontrol)
2588{
2589 int idx = aux_pcm_get_port_idx(kcontrol);
2590
2591 if (idx < 0)
2592 return idx;
2593
2594 ucontrol->value.enumerated.item[0] =
2595 mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
2596
2597 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2598 idx, aux_pcm_tx_cfg[idx].bit_format,
2599 ucontrol->value.enumerated.item[0]);
2600
2601 return 0;
2602}
2603
2604static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
2605 struct snd_ctl_elem_value *ucontrol)
2606{
2607 int idx = aux_pcm_get_port_idx(kcontrol);
2608
2609 if (idx < 0)
2610 return idx;
2611
2612 aux_pcm_tx_cfg[idx].bit_format =
2613 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2614
2615 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2616 idx, aux_pcm_tx_cfg[idx].bit_format,
2617 ucontrol->value.enumerated.item[0]);
2618
2619 return 0;
2620}
2621
2622static const struct snd_kcontrol_new msm_snd_controls[] = {
2623 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
2624 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
2625 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
2626 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
2627 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
2628 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
2629 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
2630 proxy_rx_ch_get, proxy_rx_ch_put),
2631 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
2632 usb_audio_rx_format_get, usb_audio_rx_format_put),
2633 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
2634 usb_audio_tx_format_get, usb_audio_tx_format_put),
2635 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
2636 ext_disp_rx_format_get, ext_disp_rx_format_put),
2637 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
2638 usb_audio_rx_sample_rate_get,
2639 usb_audio_rx_sample_rate_put),
2640 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
2641 usb_audio_tx_sample_rate_get,
2642 usb_audio_tx_sample_rate_put),
2643 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
2644 ext_disp_rx_sample_rate_get,
2645 ext_disp_rx_sample_rate_put),
2646 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2647 tdm_rx_sample_rate_get,
2648 tdm_rx_sample_rate_put),
2649 SOC_ENUM_EXT("PRI_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2650 tdm_rx_sample_rate_get,
2651 tdm_rx_sample_rate_put),
2652 SOC_ENUM_EXT("PRI_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2653 tdm_rx_sample_rate_get,
2654 tdm_rx_sample_rate_put),
2655 SOC_ENUM_EXT("PRI_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2656 tdm_rx_sample_rate_get,
2657 tdm_rx_sample_rate_put),
2658 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2659 tdm_tx_sample_rate_get,
2660 tdm_tx_sample_rate_put),
2661 SOC_ENUM_EXT("PRI_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2662 tdm_tx_sample_rate_get,
2663 tdm_tx_sample_rate_put),
2664 SOC_ENUM_EXT("PRI_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2665 tdm_tx_sample_rate_get,
2666 tdm_tx_sample_rate_put),
2667 SOC_ENUM_EXT("PRI_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2668 tdm_tx_sample_rate_get,
2669 tdm_tx_sample_rate_put),
2670 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
2671 tdm_rx_format_get,
2672 tdm_rx_format_put),
2673 SOC_ENUM_EXT("PRI_TDM_RX_1 Format", tdm_rx_format,
2674 tdm_rx_format_get,
2675 tdm_rx_format_put),
2676 SOC_ENUM_EXT("PRI_TDM_RX_2 Format", tdm_rx_format,
2677 tdm_rx_format_get,
2678 tdm_rx_format_put),
2679 SOC_ENUM_EXT("PRI_TDM_RX_3 Format", tdm_rx_format,
2680 tdm_rx_format_get,
2681 tdm_rx_format_put),
2682 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
2683 tdm_tx_format_get,
2684 tdm_tx_format_put),
2685 SOC_ENUM_EXT("PRI_TDM_TX_1 Format", tdm_tx_format,
2686 tdm_tx_format_get,
2687 tdm_tx_format_put),
2688 SOC_ENUM_EXT("PRI_TDM_TX_2 Format", tdm_tx_format,
2689 tdm_tx_format_get,
2690 tdm_tx_format_put),
2691 SOC_ENUM_EXT("PRI_TDM_TX_3 Format", tdm_tx_format,
2692 tdm_tx_format_get,
2693 tdm_tx_format_put),
2694 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
2695 tdm_rx_ch_get,
2696 tdm_rx_ch_put),
2697 SOC_ENUM_EXT("PRI_TDM_RX_1 Channels", tdm_rx_chs,
2698 tdm_rx_ch_get,
2699 tdm_rx_ch_put),
2700 SOC_ENUM_EXT("PRI_TDM_RX_2 Channels", tdm_rx_chs,
2701 tdm_rx_ch_get,
2702 tdm_rx_ch_put),
2703 SOC_ENUM_EXT("PRI_TDM_RX_3 Channels", tdm_rx_chs,
2704 tdm_rx_ch_get,
2705 tdm_rx_ch_put),
2706 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
2707 tdm_tx_ch_get,
2708 tdm_tx_ch_put),
2709 SOC_ENUM_EXT("PRI_TDM_TX_1 Channels", tdm_tx_chs,
2710 tdm_tx_ch_get,
2711 tdm_tx_ch_put),
2712 SOC_ENUM_EXT("PRI_TDM_TX_2 Channels", tdm_tx_chs,
2713 tdm_tx_ch_get,
2714 tdm_tx_ch_put),
2715 SOC_ENUM_EXT("PRI_TDM_TX_3 Channels", tdm_tx_chs,
2716 tdm_tx_ch_get,
2717 tdm_tx_ch_put),
2718 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2719 tdm_rx_sample_rate_get,
2720 tdm_rx_sample_rate_put),
2721 SOC_ENUM_EXT("SEC_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2722 tdm_rx_sample_rate_get,
2723 tdm_rx_sample_rate_put),
2724 SOC_ENUM_EXT("SEC_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2725 tdm_rx_sample_rate_get,
2726 tdm_rx_sample_rate_put),
2727 SOC_ENUM_EXT("SEC_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2728 tdm_rx_sample_rate_get,
2729 tdm_rx_sample_rate_put),
2730 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2731 tdm_tx_sample_rate_get,
2732 tdm_tx_sample_rate_put),
2733 SOC_ENUM_EXT("SEC_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2734 tdm_tx_sample_rate_get,
2735 tdm_tx_sample_rate_put),
2736 SOC_ENUM_EXT("SEC_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2737 tdm_tx_sample_rate_get,
2738 tdm_tx_sample_rate_put),
2739 SOC_ENUM_EXT("SEC_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2740 tdm_tx_sample_rate_get,
2741 tdm_tx_sample_rate_put),
2742 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
2743 tdm_rx_format_get,
2744 tdm_rx_format_put),
2745 SOC_ENUM_EXT("SEC_TDM_RX_1 Format", tdm_rx_format,
2746 tdm_rx_format_get,
2747 tdm_rx_format_put),
2748 SOC_ENUM_EXT("SEC_TDM_RX_2 Format", tdm_rx_format,
2749 tdm_rx_format_get,
2750 tdm_rx_format_put),
2751 SOC_ENUM_EXT("SEC_TDM_RX_3 Format", tdm_rx_format,
2752 tdm_rx_format_get,
2753 tdm_rx_format_put),
2754 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
2755 tdm_tx_format_get,
2756 tdm_tx_format_put),
2757 SOC_ENUM_EXT("SEC_TDM_TX_1 Format", tdm_tx_format,
2758 tdm_tx_format_get,
2759 tdm_tx_format_put),
2760 SOC_ENUM_EXT("SEC_TDM_TX_2 Format", tdm_tx_format,
2761 tdm_tx_format_get,
2762 tdm_tx_format_put),
2763 SOC_ENUM_EXT("SEC_TDM_TX_3 Format", tdm_tx_format,
2764 tdm_tx_format_get,
2765 tdm_tx_format_put),
2766 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
2767 tdm_rx_ch_get,
2768 tdm_rx_ch_put),
2769 SOC_ENUM_EXT("SEC_TDM_RX_1 Channels", tdm_rx_chs,
2770 tdm_rx_ch_get,
2771 tdm_rx_ch_put),
2772 SOC_ENUM_EXT("SEC_TDM_RX_2 Channels", tdm_rx_chs,
2773 tdm_rx_ch_get,
2774 tdm_rx_ch_put),
2775 SOC_ENUM_EXT("SEC_TDM_RX_3 Channels", tdm_rx_chs,
2776 tdm_rx_ch_get,
2777 tdm_rx_ch_put),
2778 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
2779 tdm_tx_ch_get,
2780 tdm_tx_ch_put),
2781 SOC_ENUM_EXT("SEC_TDM_TX_1 Channels", tdm_tx_chs,
2782 tdm_tx_ch_get,
2783 tdm_tx_ch_put),
2784 SOC_ENUM_EXT("SEC_TDM_TX_2 Channels", tdm_tx_chs,
2785 tdm_tx_ch_get,
2786 tdm_tx_ch_put),
2787 SOC_ENUM_EXT("SEC_TDM_TX_3 Channels", tdm_tx_chs,
2788 tdm_tx_ch_get,
2789 tdm_tx_ch_put),
2790 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2791 tdm_rx_sample_rate_get,
2792 tdm_rx_sample_rate_put),
2793 SOC_ENUM_EXT("TERT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2794 tdm_rx_sample_rate_get,
2795 tdm_rx_sample_rate_put),
2796 SOC_ENUM_EXT("TERT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2797 tdm_rx_sample_rate_get,
2798 tdm_rx_sample_rate_put),
2799 SOC_ENUM_EXT("TERT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2800 tdm_rx_sample_rate_get,
2801 tdm_rx_sample_rate_put),
2802 SOC_ENUM_EXT("TERT_TDM_RX_4 SampleRate", tdm_rx_sample_rate,
2803 tdm_rx_sample_rate_get,
2804 tdm_rx_sample_rate_put),
2805 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2806 tdm_tx_sample_rate_get,
2807 tdm_tx_sample_rate_put),
2808 SOC_ENUM_EXT("TERT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2809 tdm_tx_sample_rate_get,
2810 tdm_tx_sample_rate_put),
2811 SOC_ENUM_EXT("TERT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2812 tdm_tx_sample_rate_get,
2813 tdm_tx_sample_rate_put),
2814 SOC_ENUM_EXT("TERT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2815 tdm_tx_sample_rate_get,
2816 tdm_tx_sample_rate_put),
2817 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
2818 tdm_rx_format_get,
2819 tdm_rx_format_put),
2820 SOC_ENUM_EXT("TERT_TDM_RX_1 Format", tdm_rx_format,
2821 tdm_rx_format_get,
2822 tdm_rx_format_put),
2823 SOC_ENUM_EXT("TERT_TDM_RX_2 Format", tdm_rx_format,
2824 tdm_rx_format_get,
2825 tdm_rx_format_put),
2826 SOC_ENUM_EXT("TERT_TDM_RX_3 Format", tdm_rx_format,
2827 tdm_rx_format_get,
2828 tdm_rx_format_put),
2829 SOC_ENUM_EXT("TERT_TDM_RX_4 Format", tdm_rx_format,
2830 tdm_rx_format_get,
2831 tdm_rx_format_put),
2832 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
2833 tdm_tx_format_get,
2834 tdm_tx_format_put),
2835 SOC_ENUM_EXT("TERT_TDM_TX_1 Format", tdm_tx_format,
2836 tdm_tx_format_get,
2837 tdm_tx_format_put),
2838 SOC_ENUM_EXT("TERT_TDM_TX_2 Format", tdm_tx_format,
2839 tdm_tx_format_get,
2840 tdm_tx_format_put),
2841 SOC_ENUM_EXT("TERT_TDM_TX_3 Format", tdm_tx_format,
2842 tdm_tx_format_get,
2843 tdm_tx_format_put),
2844 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
2845 tdm_rx_ch_get,
2846 tdm_rx_ch_put),
2847 SOC_ENUM_EXT("TERT_TDM_RX_1 Channels", tdm_rx_chs,
2848 tdm_rx_ch_get,
2849 tdm_rx_ch_put),
2850 SOC_ENUM_EXT("TERT_TDM_RX_2 Channels", tdm_rx_chs,
2851 tdm_rx_ch_get,
2852 tdm_rx_ch_put),
2853 SOC_ENUM_EXT("TERT_TDM_RX_3 Channels", tdm_rx_chs,
2854 tdm_rx_ch_get,
2855 tdm_rx_ch_put),
2856 SOC_ENUM_EXT("TERT_TDM_RX_4 Channels", tdm_rx_chs,
2857 tdm_rx_ch_get,
2858 tdm_rx_ch_put),
2859 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
2860 tdm_tx_ch_get,
2861 tdm_tx_ch_put),
2862 SOC_ENUM_EXT("TERT_TDM_TX_1 Channels", tdm_tx_chs,
2863 tdm_tx_ch_get,
2864 tdm_tx_ch_put),
2865 SOC_ENUM_EXT("TERT_TDM_TX_2 Channels", tdm_tx_chs,
2866 tdm_tx_ch_get,
2867 tdm_tx_ch_put),
2868 SOC_ENUM_EXT("TERT_TDM_TX_3 Channels", tdm_tx_chs,
2869 tdm_tx_ch_get,
2870 tdm_tx_ch_put),
2871 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2872 tdm_rx_sample_rate_get,
2873 tdm_rx_sample_rate_put),
2874 SOC_ENUM_EXT("QUAT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2875 tdm_rx_sample_rate_get,
2876 tdm_rx_sample_rate_put),
2877 SOC_ENUM_EXT("QUAT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2878 tdm_rx_sample_rate_get,
2879 tdm_rx_sample_rate_put),
2880 SOC_ENUM_EXT("QUAT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2881 tdm_rx_sample_rate_get,
2882 tdm_rx_sample_rate_put),
2883 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2884 tdm_tx_sample_rate_get,
2885 tdm_tx_sample_rate_put),
2886 SOC_ENUM_EXT("QUAT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2887 tdm_tx_sample_rate_get,
2888 tdm_tx_sample_rate_put),
2889 SOC_ENUM_EXT("QUAT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2890 tdm_tx_sample_rate_get,
2891 tdm_tx_sample_rate_put),
2892 SOC_ENUM_EXT("QUAT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2893 tdm_tx_sample_rate_get,
2894 tdm_tx_sample_rate_put),
2895 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
2896 tdm_rx_format_get,
2897 tdm_rx_format_put),
2898 SOC_ENUM_EXT("QUAT_TDM_RX_1 Format", tdm_rx_format,
2899 tdm_rx_format_get,
2900 tdm_rx_format_put),
2901 SOC_ENUM_EXT("QUAT_TDM_RX_2 Format", tdm_rx_format,
2902 tdm_rx_format_get,
2903 tdm_rx_format_put),
2904 SOC_ENUM_EXT("QUAT_TDM_RX_3 Format", tdm_rx_format,
2905 tdm_rx_format_get,
2906 tdm_rx_format_put),
2907 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
2908 tdm_tx_format_get,
2909 tdm_tx_format_put),
2910 SOC_ENUM_EXT("QUAT_TDM_TX_1 Format", tdm_tx_format,
2911 tdm_tx_format_get,
2912 tdm_tx_format_put),
2913 SOC_ENUM_EXT("QUAT_TDM_TX_2 Format", tdm_tx_format,
2914 tdm_tx_format_get,
2915 tdm_tx_format_put),
2916 SOC_ENUM_EXT("QUAT_TDM_TX_3 Format", tdm_tx_format,
2917 tdm_tx_format_get,
2918 tdm_tx_format_put),
2919 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
2920 tdm_rx_ch_get,
2921 tdm_rx_ch_put),
2922 SOC_ENUM_EXT("QUAT_TDM_RX_1 Channels", tdm_rx_chs,
2923 tdm_rx_ch_get,
2924 tdm_rx_ch_put),
2925 SOC_ENUM_EXT("QUAT_TDM_RX_2 Channels", tdm_rx_chs,
2926 tdm_rx_ch_get,
2927 tdm_rx_ch_put),
2928 SOC_ENUM_EXT("QUAT_TDM_RX_3 Channels", tdm_rx_chs,
2929 tdm_rx_ch_get,
2930 tdm_rx_ch_put),
2931 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
2932 tdm_tx_ch_get,
2933 tdm_tx_ch_put),
2934 SOC_ENUM_EXT("QUAT_TDM_TX_1 Channels", tdm_tx_chs,
2935 tdm_tx_ch_get,
2936 tdm_tx_ch_put),
2937 SOC_ENUM_EXT("QUAT_TDM_TX_2 Channels", tdm_tx_chs,
2938 tdm_tx_ch_get,
2939 tdm_tx_ch_put),
2940 SOC_ENUM_EXT("QUAT_TDM_TX_3 Channels", tdm_tx_chs,
2941 tdm_tx_ch_get,
2942 tdm_tx_ch_put),
2943 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2944 tdm_rx_sample_rate_get,
2945 tdm_rx_sample_rate_put),
2946 SOC_ENUM_EXT("QUIN_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2947 tdm_rx_sample_rate_get,
2948 tdm_rx_sample_rate_put),
2949 SOC_ENUM_EXT("QUIN_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2950 tdm_rx_sample_rate_get,
2951 tdm_rx_sample_rate_put),
2952 SOC_ENUM_EXT("QUIN_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2953 tdm_rx_sample_rate_get,
2954 tdm_rx_sample_rate_put),
2955 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2956 tdm_tx_sample_rate_get,
2957 tdm_tx_sample_rate_put),
2958 SOC_ENUM_EXT("QUIN_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2959 tdm_tx_sample_rate_get,
2960 tdm_tx_sample_rate_put),
2961 SOC_ENUM_EXT("QUIN_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2962 tdm_tx_sample_rate_get,
2963 tdm_tx_sample_rate_put),
2964 SOC_ENUM_EXT("QUIN_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2965 tdm_tx_sample_rate_get,
2966 tdm_tx_sample_rate_put),
2967 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
2968 tdm_rx_format_get,
2969 tdm_rx_format_put),
2970 SOC_ENUM_EXT("QUIN_TDM_RX_1 Format", tdm_rx_format,
2971 tdm_rx_format_get,
2972 tdm_rx_format_put),
2973 SOC_ENUM_EXT("QUIN_TDM_RX_2 Format", tdm_rx_format,
2974 tdm_rx_format_get,
2975 tdm_rx_format_put),
2976 SOC_ENUM_EXT("QUIN_TDM_RX_3 Format", tdm_rx_format,
2977 tdm_rx_format_get,
2978 tdm_rx_format_put),
2979 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
2980 tdm_tx_format_get,
2981 tdm_tx_format_put),
2982 SOC_ENUM_EXT("QUIN_TDM_TX_1 Format", tdm_tx_format,
2983 tdm_tx_format_get,
2984 tdm_tx_format_put),
2985 SOC_ENUM_EXT("QUIN_TDM_TX_2 Format", tdm_tx_format,
2986 tdm_tx_format_get,
2987 tdm_tx_format_put),
2988 SOC_ENUM_EXT("QUIN_TDM_TX_3 Format", tdm_tx_format,
2989 tdm_tx_format_get,
2990 tdm_tx_format_put),
2991 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
2992 tdm_rx_ch_get,
2993 tdm_rx_ch_put),
2994 SOC_ENUM_EXT("QUIN_TDM_RX_1 Channels", tdm_rx_chs,
2995 tdm_rx_ch_get,
2996 tdm_rx_ch_put),
2997 SOC_ENUM_EXT("QUIN_TDM_RX_2 Channels", tdm_rx_chs,
2998 tdm_rx_ch_get,
2999 tdm_rx_ch_put),
3000 SOC_ENUM_EXT("QUIN_TDM_RX_3 Channels", tdm_rx_chs,
3001 tdm_rx_ch_get,
3002 tdm_rx_ch_put),
3003 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
3004 tdm_tx_ch_get,
3005 tdm_tx_ch_put),
3006 SOC_ENUM_EXT("QUIN_TDM_TX_1 Channels", tdm_tx_chs,
3007 tdm_tx_ch_get,
3008 tdm_tx_ch_put),
3009 SOC_ENUM_EXT("QUIN_TDM_TX_2 Channels", tdm_tx_chs,
3010 tdm_tx_ch_get,
3011 tdm_tx_ch_put),
3012 SOC_ENUM_EXT("QUIN_TDM_TX_3 Channels", tdm_tx_chs,
3013 tdm_tx_ch_get,
3014 tdm_tx_ch_put),
3015 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3016 tdm_slot_num_get, tdm_slot_num_put),
3017 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3018 tdm_slot_width_get, tdm_slot_width_put),
3019 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3020 tdm_slot_num_get, tdm_slot_num_put),
3021 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3022 tdm_slot_width_get, tdm_slot_width_put),
3023 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3024 tdm_slot_num_get, tdm_slot_num_put),
3025 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3026 tdm_slot_width_get, tdm_slot_width_put),
3027 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3028 tdm_slot_num_get, tdm_slot_num_put),
3029 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3030 tdm_slot_width_get, tdm_slot_width_put),
3031 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3032 tdm_slot_num_get, tdm_slot_num_put),
3033 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3034 tdm_slot_width_get, tdm_slot_width_put),
3035 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3036 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3037 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3038 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3039 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3040 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3041 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3042 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3043 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3044 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3045 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3046 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3047 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3048 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3049 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3050 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3051 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3052 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3053 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3054 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3055 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3056 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3057 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3058 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3059 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3060 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3061 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3062 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3063 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3064 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3065 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3066 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3067 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3068 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3069 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3070 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3071 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3072 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3073 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3074 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3075 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3076 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3077 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3078 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3079 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3080 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3081 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3082 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3083 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3084 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3085 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3086 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3087 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3088 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3089 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3090 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3091 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3092 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3093 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3094 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3095 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3096 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3097 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3098 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3099 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3100 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3101 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3102 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3103 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3104 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3105 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3106 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3107 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3108 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3109 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3110 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3111 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3112 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3113 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3114 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3115 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3116 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3117 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3118 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3119 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3120 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3121 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3122 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3123 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3124 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3125 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3126 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3127 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3128 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3129 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3130 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3131 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3132 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3133 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3134 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3135 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3136 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3137 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3138 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3139 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3140 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3141 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3142 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3143 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3144 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3145 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3146 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3147 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3148 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3149 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3150 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3151 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3152 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3153 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3154 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3155 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3156 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3157 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3158 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3159 aux_pcm_rx_sample_rate_get,
3160 aux_pcm_rx_sample_rate_put),
3161 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3162 aux_pcm_rx_sample_rate_get,
3163 aux_pcm_rx_sample_rate_put),
3164 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3165 aux_pcm_rx_sample_rate_get,
3166 aux_pcm_rx_sample_rate_put),
3167 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3168 aux_pcm_rx_sample_rate_get,
3169 aux_pcm_rx_sample_rate_put),
3170 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3171 aux_pcm_rx_sample_rate_get,
3172 aux_pcm_rx_sample_rate_put),
3173 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3174 aux_pcm_tx_sample_rate_get,
3175 aux_pcm_tx_sample_rate_put),
3176 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3177 aux_pcm_tx_sample_rate_get,
3178 aux_pcm_tx_sample_rate_put),
3179 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3180 aux_pcm_tx_sample_rate_get,
3181 aux_pcm_tx_sample_rate_put),
3182 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3183 aux_pcm_tx_sample_rate_get,
3184 aux_pcm_tx_sample_rate_put),
3185 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3186 aux_pcm_tx_sample_rate_get,
3187 aux_pcm_tx_sample_rate_put),
3188 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3189 mi2s_rx_sample_rate_get,
3190 mi2s_rx_sample_rate_put),
3191 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3192 mi2s_rx_sample_rate_get,
3193 mi2s_rx_sample_rate_put),
3194 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3195 mi2s_rx_sample_rate_get,
3196 mi2s_rx_sample_rate_put),
3197 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3198 mi2s_rx_sample_rate_get,
3199 mi2s_rx_sample_rate_put),
3200 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3201 mi2s_rx_sample_rate_get,
3202 mi2s_rx_sample_rate_put),
3203 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3204 mi2s_tx_sample_rate_get,
3205 mi2s_tx_sample_rate_put),
3206 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3207 mi2s_tx_sample_rate_get,
3208 mi2s_tx_sample_rate_put),
3209 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3210 mi2s_tx_sample_rate_get,
3211 mi2s_tx_sample_rate_put),
3212 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3213 mi2s_tx_sample_rate_get,
3214 mi2s_tx_sample_rate_put),
3215 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3216 mi2s_tx_sample_rate_get,
3217 mi2s_tx_sample_rate_put),
3218 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3219 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3220 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3221 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3222 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3223 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3224 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3225 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3226 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3227 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3228 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3229 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3230 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3231 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3232 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3233 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3234 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3235 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3236 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3237 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3238 SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
3239 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3240 SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
3241 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3242 SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
3243 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3244 SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
3245 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3246 SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
3247 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3248 SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
3249 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3250 SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
3251 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3252 SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
3253 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3254 SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
3255 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3256 SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
3257 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3258 SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
3259 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3260 SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
3261 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3262 SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
3263 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3264 SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
3265 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3266 SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
3267 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3268 SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
3269 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3270 SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
3271 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3272 SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
3273 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3274 SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
3275 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3276 SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
3277 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3278};
3279
3280static inline int param_is_mask(int p)
3281{
3282 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3283 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3284}
3285
3286static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3287 int n)
3288{
3289 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3290}
3291
3292static void param_set_mask(struct snd_pcm_hw_params *p, int n,
3293 unsigned int bit)
3294{
3295 if (bit >= SNDRV_MASK_MAX)
3296 return;
3297 if (param_is_mask(n)) {
3298 struct snd_mask *m = param_to_mask(p, n);
3299
3300 m->bits[0] = 0;
3301 m->bits[1] = 0;
3302 m->bits[bit >> 5] |= (1 << (bit & 31));
3303 }
3304}
3305
3306static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
3307{
3308 int idx;
3309
3310 switch (be_id) {
3311 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3312 idx = DP_RX_IDX;
3313 break;
3314 default:
3315 pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
3316 idx = -EINVAL;
3317 break;
3318 }
3319
3320 return idx;
3321}
3322
3323static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3324 struct snd_pcm_hw_params *params)
3325{
3326 struct snd_soc_dai_link *dai_link = rtd->dai_link;
3327 struct snd_interval *rate = hw_param_interval(params,
3328 SNDRV_PCM_HW_PARAM_RATE);
3329 struct snd_interval *channels = hw_param_interval(params,
3330 SNDRV_PCM_HW_PARAM_CHANNELS);
3331 int rc = 0;
3332 int idx;
3333
3334 pr_debug("%s: format = %d, rate = %d\n",
3335 __func__, params_format(params), params_rate(params));
3336
3337 switch (dai_link->id) {
3338 case MSM_BACKEND_DAI_USB_RX:
3339 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3340 usb_rx_cfg.bit_format);
3341 rate->min = rate->max = usb_rx_cfg.sample_rate;
3342 channels->min = channels->max = usb_rx_cfg.channels;
3343 break;
3344
3345 case MSM_BACKEND_DAI_USB_TX:
3346 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3347 usb_tx_cfg.bit_format);
3348 rate->min = rate->max = usb_tx_cfg.sample_rate;
3349 channels->min = channels->max = usb_tx_cfg.channels;
3350 break;
3351
3352 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3353 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
3354 if (idx < 0) {
3355 pr_err("%s: Incorrect ext disp idx %d\n",
3356 __func__, idx);
3357 rc = idx;
3358 goto done;
3359 }
3360
3361 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3362 ext_disp_rx_cfg[idx].bit_format);
3363 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
3364 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
3365 break;
3366
3367 case MSM_BACKEND_DAI_AFE_PCM_RX:
3368 channels->min = channels->max = proxy_rx_cfg.channels;
3369 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3370 break;
3371
3372 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
3373 channels->min = channels->max =
3374 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3375 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3376 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3377 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3378 break;
3379
3380 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
3381 channels->min = channels->max =
3382 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3383 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3384 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3385 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3386 break;
3387
3388 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
3389 channels->min = channels->max =
3390 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3391 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3392 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3393 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3394 break;
3395
3396 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
3397 channels->min = channels->max =
3398 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3399 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3400 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3401 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3402 break;
3403
3404 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
3405 channels->min = channels->max =
3406 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3407 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3408 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3409 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3410 break;
3411
3412 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
3413 channels->min = channels->max =
3414 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3415 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3416 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3417 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
3418 break;
3419
3420 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
3421 channels->min = channels->max =
3422 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
3423 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3424 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
3425 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
3426 break;
3427
3428 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
3429 channels->min = channels->max =
3430 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
3431 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3432 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
3433 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
3434 break;
3435
3436 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
3437 channels->min = channels->max =
3438 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
3439 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3440 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
3441 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
3442 break;
3443
3444 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
3445 channels->min = channels->max =
3446 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
3447 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3448 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
3449 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
3450 break;
3451
3452
3453 case MSM_BACKEND_DAI_AUXPCM_RX:
3454 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3455 aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
3456 rate->min = rate->max =
3457 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
3458 channels->min = channels->max =
3459 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
3460 break;
3461
3462 case MSM_BACKEND_DAI_AUXPCM_TX:
3463 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3464 aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
3465 rate->min = rate->max =
3466 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
3467 channels->min = channels->max =
3468 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
3469 break;
3470
3471 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
3472 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3473 aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
3474 rate->min = rate->max =
3475 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
3476 channels->min = channels->max =
3477 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
3478 break;
3479
3480 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
3481 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3482 aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
3483 rate->min = rate->max =
3484 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
3485 channels->min = channels->max =
3486 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
3487 break;
3488
3489 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
3490 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3491 aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
3492 rate->min = rate->max =
3493 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
3494 channels->min = channels->max =
3495 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
3496 break;
3497
3498 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
3499 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3500 aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
3501 rate->min = rate->max =
3502 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
3503 channels->min = channels->max =
3504 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
3505 break;
3506
3507 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
3508 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3509 aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
3510 rate->min = rate->max =
3511 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
3512 channels->min = channels->max =
3513 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
3514 break;
3515
3516 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
3517 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3518 aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
3519 rate->min = rate->max =
3520 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
3521 channels->min = channels->max =
3522 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
3523 break;
3524
3525 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
3526 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3527 aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
3528 rate->min = rate->max =
3529 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
3530 channels->min = channels->max =
3531 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
3532 break;
3533
3534 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
3535 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3536 aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
3537 rate->min = rate->max =
3538 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
3539 channels->min = channels->max =
3540 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
3541 break;
3542
3543 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3544 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3545 mi2s_rx_cfg[PRIM_MI2S].bit_format);
3546 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
3547 channels->min = channels->max =
3548 mi2s_rx_cfg[PRIM_MI2S].channels;
3549 break;
3550
3551 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3552 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3553 mi2s_tx_cfg[PRIM_MI2S].bit_format);
3554 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
3555 channels->min = channels->max =
3556 mi2s_tx_cfg[PRIM_MI2S].channels;
3557 break;
3558
3559 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3560 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3561 mi2s_rx_cfg[SEC_MI2S].bit_format);
3562 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
3563 channels->min = channels->max =
3564 mi2s_rx_cfg[SEC_MI2S].channels;
3565 break;
3566
3567 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3568 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3569 mi2s_tx_cfg[SEC_MI2S].bit_format);
3570 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
3571 channels->min = channels->max =
3572 mi2s_tx_cfg[SEC_MI2S].channels;
3573 break;
3574
3575 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3576 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3577 mi2s_rx_cfg[TERT_MI2S].bit_format);
3578 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
3579 channels->min = channels->max =
3580 mi2s_rx_cfg[TERT_MI2S].channels;
3581 break;
3582
3583 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3584 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3585 mi2s_tx_cfg[TERT_MI2S].bit_format);
3586 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
3587 channels->min = channels->max =
3588 mi2s_tx_cfg[TERT_MI2S].channels;
3589 break;
3590
3591 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3592 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3593 mi2s_rx_cfg[QUAT_MI2S].bit_format);
3594 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
3595 channels->min = channels->max =
3596 mi2s_rx_cfg[QUAT_MI2S].channels;
3597 break;
3598
3599 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3600 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3601 mi2s_tx_cfg[QUAT_MI2S].bit_format);
3602 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
3603 channels->min = channels->max =
3604 mi2s_tx_cfg[QUAT_MI2S].channels;
3605 break;
3606
3607 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3608 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3609 mi2s_rx_cfg[QUIN_MI2S].bit_format);
3610 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
3611 channels->min = channels->max =
3612 mi2s_rx_cfg[QUIN_MI2S].channels;
3613 break;
3614
3615 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3616 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3617 mi2s_tx_cfg[QUIN_MI2S].bit_format);
3618 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
3619 channels->min = channels->max =
3620 mi2s_tx_cfg[QUIN_MI2S].channels;
3621 break;
3622
3623 default:
3624 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3625 break;
3626 }
3627
3628done:
3629 return rc;
3630}
3631
3632static int msm_get_port_id(int be_id)
3633{
3634 int afe_port_id;
3635
3636 switch (be_id) {
3637 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3638 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
3639 break;
3640 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3641 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
3642 break;
3643 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3644 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
3645 break;
3646 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3647 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
3648 break;
3649 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3650 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
3651 break;
3652 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3653 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
3654 break;
3655 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3656 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
3657 break;
3658 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3659 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
3660 break;
3661 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3662 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
3663 break;
3664 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3665 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
3666 break;
3667 default:
3668 pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
3669 afe_port_id = -EINVAL;
3670 }
3671
3672 return afe_port_id;
3673}
3674
3675static u32 get_mi2s_bits_per_sample(u32 bit_format)
3676{
3677 u32 bit_per_sample;
3678
3679 switch (bit_format) {
3680 case SNDRV_PCM_FORMAT_S32_LE:
3681 case SNDRV_PCM_FORMAT_S24_3LE:
3682 case SNDRV_PCM_FORMAT_S24_LE:
3683 bit_per_sample = 32;
3684 break;
3685 case SNDRV_PCM_FORMAT_S16_LE:
3686 default:
3687 bit_per_sample = 16;
3688 break;
3689 }
3690
3691 return bit_per_sample;
3692}
3693
3694static void update_mi2s_clk_val(int dai_id, int stream)
3695{
3696 u32 bit_per_sample;
3697
3698 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
3699 bit_per_sample =
3700 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
3701 mi2s_clk[dai_id].clk_freq_in_hz =
3702 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3703 } else {
3704 bit_per_sample =
3705 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
3706 mi2s_clk[dai_id].clk_freq_in_hz =
3707 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3708 }
3709}
3710
3711static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
3712{
3713 int ret = 0;
3714 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3715 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3716 int port_id = 0;
3717 int index = cpu_dai->id;
3718
3719 port_id = msm_get_port_id(rtd->dai_link->id);
3720 if (port_id < 0) {
3721 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
3722 ret = port_id;
3723 goto err;
3724 }
3725
3726 if (enable) {
3727 update_mi2s_clk_val(index, substream->stream);
3728 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
3729 mi2s_clk[index].clk_freq_in_hz);
3730 }
3731
3732 mi2s_clk[index].enable = enable;
3733 ret = afe_set_lpass_clock_v2(port_id,
3734 &mi2s_clk[index]);
3735 if (ret < 0) {
3736 dev_err(rtd->card->dev,
3737 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
3738 __func__, port_id, ret);
3739 goto err;
3740 }
3741
3742err:
3743 return ret;
3744}
3745
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3746static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3747 enum pinctrl_pin_state new_state)
3748{
3749 int ret = 0;
3750 int curr_state = 0;
3751
3752 if (pinctrl_info == NULL) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3753 pr_err("%s: pinctrl info is NULL\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3754 ret = -EINVAL;
3755 goto err;
3756 }
3757
3758 if (pinctrl_info->pinctrl == NULL) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3759 pr_err("%s: pinctrl handle is NULL\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3760 ret = -EINVAL;
3761 goto err;
3762 }
3763
3764 curr_state = pinctrl_info->curr_state;
3765 pinctrl_info->curr_state = new_state;
3766 pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
3767 pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
3768
3769 if (curr_state == pinctrl_info->curr_state) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3770 pr_debug("%s: pin already in same state\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3771 goto err;
3772 }
3773
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3774 if (curr_state != STATE_SLEEP &&
3775 pinctrl_info->curr_state != STATE_SLEEP) {
3776 pr_debug("%s: pin state is already active, cannot switch\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3777 ret = -EIO;
3778 goto err;
3779 }
3780
3781 switch (pinctrl_info->curr_state) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3782 case STATE_ACTIVE:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3783 ret = pinctrl_select_state(pinctrl_info->pinctrl,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3784 pinctrl_info->active);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3785 if (ret) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3786 pr_err("%s: state select to active failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3787 __func__, ret);
3788 ret = -EIO;
3789 goto err;
3790 }
3791 break;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3792 case STATE_SLEEP:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3793 ret = pinctrl_select_state(pinctrl_info->pinctrl,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3794 pinctrl_info->sleep);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3795 if (ret) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3796 pr_err("%s: state select to sleep failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3797 __func__, ret);
3798 ret = -EIO;
3799 goto err;
3800 }
3801 break;
3802 default:
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3803 pr_err("%s: pin state is invalid\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3804 return -EINVAL;
3805 }
3806
3807err:
3808 return ret;
3809}
3810
3811static void msm_release_pinctrl(struct platform_device *pdev)
3812{
3813 struct snd_soc_card *card = platform_get_drvdata(pdev);
3814 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3815 struct msm_pinctrl_info *pinctrl_info = NULL;
3816 int i;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3817
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3818 for (i = TDM_PRI; i < TDM_INTERFACE_MAX; i++) {
3819 pinctrl_info = &pdata->pinctrl_info[i];
3820 if (pinctrl_info == NULL)
3821 continue;
3822 if (pinctrl_info->pinctrl) {
3823 devm_pinctrl_put(pinctrl_info->pinctrl);
3824 pinctrl_info->pinctrl = NULL;
3825 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3826 }
3827}
3828
3829static int msm_get_pinctrl(struct platform_device *pdev)
3830{
3831 struct snd_soc_card *card = platform_get_drvdata(pdev);
3832 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3833 struct msm_pinctrl_info *pinctrl_info = NULL;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3834 struct pinctrl *pinctrl = NULL;
3835 int i, j;
3836 struct device_node *np = NULL;
3837 struct platform_device *pdev_np = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3838 int ret = 0;
3839
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3840 for (i = TDM_PRI; i < TDM_INTERFACE_MAX; i++) {
3841 np = of_parse_phandle(pdev->dev.of_node,
3842 tdm_gpio_phandle[i], 0);
3843 if (!np) {
3844 pr_debug("%s: device node %s is null\n",
3845 __func__, tdm_gpio_phandle[i]);
3846 continue;
3847 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3848
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3849 pdev_np = of_find_device_by_node(np);
3850 if (!pdev_np) {
3851 pr_err("%s: platform device not found\n", __func__);
3852 continue;
3853 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3854
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3855 pinctrl_info = &pdata->pinctrl_info[i];
3856 if (pinctrl_info == NULL) {
3857 pr_err("%s: pinctrl info is null\n", __func__);
3858 continue;
3859 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3860
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3861 pinctrl = devm_pinctrl_get(&pdev_np->dev);
3862 if (IS_ERR_OR_NULL(pinctrl)) {
3863 pr_err("%s: fail to get pinctrl handle\n", __func__);
3864 goto err;
3865 }
3866 pinctrl_info->pinctrl = pinctrl;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3867
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3868 /* get all the states handles from Device Tree */
3869 pinctrl_info->sleep = pinctrl_lookup_state(pinctrl,
3870 "sleep");
3871 if (IS_ERR(pinctrl_info->sleep)) {
3872 pr_err("%s: could not get sleep pin state\n", __func__);
3873 goto err;
3874 }
3875 pinctrl_info->active = pinctrl_lookup_state(pinctrl,
3876 "default");
3877 if (IS_ERR(pinctrl_info->active)) {
3878 pr_err("%s: could not get active pin state\n",
3879 __func__);
3880 goto err;
3881 }
3882
3883 /* Reset the TLMM pins to a sleep state */
3884 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3885 pinctrl_info->sleep);
3886 if (ret != 0) {
3887 pr_err("%s: set pin state to sleep failed with %d\n",
3888 __func__, ret);
3889 ret = -EIO;
3890 goto err;
3891 }
3892 pinctrl_info->curr_state = STATE_SLEEP;
3893 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3894 return 0;
3895
3896err:
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3897 for (j = i; j >= 0; j--) {
3898 pinctrl_info = &pdata->pinctrl_info[j];
3899 if (pinctrl_info == NULL)
3900 continue;
3901 if (pinctrl_info->pinctrl) {
3902 devm_pinctrl_put(pinctrl_info->pinctrl);
3903 pinctrl_info->pinctrl = NULL;
3904 }
3905 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3906 return -EINVAL;
3907}
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3908
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3909static int msm_tdm_get_intf_idx(u16 id)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3910{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]3911 switch (id) {
3912 case AFE_PORT_ID_PRIMARY_TDM_RX:
3913 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3914 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3915 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3916 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
3917 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
3918 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
3919 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
3920 case AFE_PORT_ID_PRIMARY_TDM_TX:
3921 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3922 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3923 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3924 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
3925 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
3926 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
3927 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
3928 return TDM_PRI;
3929 case AFE_PORT_ID_SECONDARY_TDM_RX:
3930 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3931 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
3932 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
3933 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
3934 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
3935 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
3936 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
3937 case AFE_PORT_ID_SECONDARY_TDM_TX:
3938 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
3939 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
3940 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
3941 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
3942 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
3943 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
3944 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
3945 return TDM_SEC;
3946 case AFE_PORT_ID_TERTIARY_TDM_RX:
3947 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
3948 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
3949 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
3950 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
3951 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
3952 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
3953 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
3954 case AFE_PORT_ID_TERTIARY_TDM_TX:
3955 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
3956 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
3957 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
3958 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
3959 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
3960 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
3961 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
3962 return TDM_TERT;
3963 case AFE_PORT_ID_QUATERNARY_TDM_RX:
3964 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
3965 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
3966 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
3967 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
3968 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
3969 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
3970 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
3971 case AFE_PORT_ID_QUATERNARY_TDM_TX:
3972 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
3973 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
3974 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
3975 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
3976 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
3977 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
3978 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
3979 return TDM_QUAT;
3980 case AFE_PORT_ID_QUINARY_TDM_RX:
3981 case AFE_PORT_ID_QUINARY_TDM_RX_1:
3982 case AFE_PORT_ID_QUINARY_TDM_RX_2:
3983 case AFE_PORT_ID_QUINARY_TDM_RX_3:
3984 case AFE_PORT_ID_QUINARY_TDM_RX_4:
3985 case AFE_PORT_ID_QUINARY_TDM_RX_5:
3986 case AFE_PORT_ID_QUINARY_TDM_RX_6:
3987 case AFE_PORT_ID_QUINARY_TDM_RX_7:
3988 case AFE_PORT_ID_QUINARY_TDM_TX:
3989 case AFE_PORT_ID_QUINARY_TDM_TX_1:
3990 case AFE_PORT_ID_QUINARY_TDM_TX_2:
3991 case AFE_PORT_ID_QUINARY_TDM_TX_3:
3992 case AFE_PORT_ID_QUINARY_TDM_TX_4:
3993 case AFE_PORT_ID_QUINARY_TDM_TX_5:
3994 case AFE_PORT_ID_QUINARY_TDM_TX_6:
3995 case AFE_PORT_ID_QUINARY_TDM_TX_7:
3996 return TDM_QUIN;
3997 default: return -EINVAL;
3998 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]3999}
4000
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4001static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
4002 struct snd_pcm_hw_params *params)
4003{
4004 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4005 struct snd_interval *rate = hw_param_interval(params,
4006 SNDRV_PCM_HW_PARAM_RATE);
4007 struct snd_interval *channels = hw_param_interval(params,
4008 SNDRV_PCM_HW_PARAM_CHANNELS);
4009
4010 switch (cpu_dai->id) {
4011 case AFE_PORT_ID_PRIMARY_TDM_RX:
4012 channels->min = channels->max =
4013 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
4014 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4015 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
4016 rate->min = rate->max =
4017 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
4018 break;
4019 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4020 channels->min = channels->max =
4021 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
4022 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4023 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
4024 rate->min = rate->max =
4025 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
4026 break;
4027 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4028 channels->min = channels->max =
4029 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
4030 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4031 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
4032 rate->min = rate->max =
4033 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
4034 break;
4035 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4036 channels->min = channels->max =
4037 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
4038 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4039 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
4040 rate->min = rate->max =
4041 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
4042 break;
4043 case AFE_PORT_ID_PRIMARY_TDM_TX:
4044 channels->min = channels->max =
4045 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
4046 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4047 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
4048 rate->min = rate->max =
4049 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
4050 break;
4051 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4052 channels->min = channels->max =
4053 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
4054 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4055 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
4056 rate->min = rate->max =
4057 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
4058 break;
4059 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4060 channels->min = channels->max =
4061 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
4062 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4063 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
4064 rate->min = rate->max =
4065 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
4066 break;
4067 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4068 channels->min = channels->max =
4069 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
4070 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4071 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
4072 rate->min = rate->max =
4073 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
4074 break;
4075 case AFE_PORT_ID_SECONDARY_TDM_RX:
4076 channels->min = channels->max =
4077 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
4078 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4079 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
4080 rate->min = rate->max =
4081 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
4082 break;
4083 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4084 channels->min = channels->max =
4085 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
4086 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4087 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
4088 rate->min = rate->max =
4089 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
4090 break;
4091 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4092 channels->min = channels->max =
4093 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
4094 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4095 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
4096 rate->min = rate->max =
4097 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
4098 break;
4099 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4100 channels->min = channels->max =
4101 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
4102 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4103 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
4104 rate->min = rate->max =
4105 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
4106 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4107 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
4108 channels->min = channels->max =
4109 tdm_rx_cfg[TDM_SEC][TDM_7].channels;
4110 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4111 tdm_rx_cfg[TDM_SEC][TDM_7].bit_format);
4112 rate->min = rate->max =
4113 tdm_rx_cfg[TDM_SEC][TDM_7].sample_rate;
4114 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4115 case AFE_PORT_ID_SECONDARY_TDM_TX:
4116 channels->min = channels->max =
4117 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4118 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4119 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4120 rate->min = rate->max =
4121 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4122 break;
4123 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4124 channels->min = channels->max =
4125 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
4126 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4127 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
4128 rate->min = rate->max =
4129 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
4130 break;
4131 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4132 channels->min = channels->max =
4133 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
4134 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4135 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
4136 rate->min = rate->max =
4137 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
4138 break;
4139 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4140 channels->min = channels->max =
4141 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
4142 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4143 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
4144 rate->min = rate->max =
4145 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
4146 break;
4147 case AFE_PORT_ID_TERTIARY_TDM_RX:
4148 channels->min = channels->max =
4149 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4150 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4151 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4152 rate->min = rate->max =
4153 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4154 break;
4155 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4156 channels->min = channels->max =
4157 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
4158 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4159 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
4160 rate->min = rate->max =
4161 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
4162 break;
4163 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4164 channels->min = channels->max =
4165 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
4166 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4167 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
4168 rate->min = rate->max =
4169 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
4170 break;
4171 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4172 channels->min = channels->max =
4173 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
4174 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4175 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
4176 rate->min = rate->max =
4177 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
4178 break;
4179 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4180 channels->min = channels->max =
4181 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
4182 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4183 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
4184 rate->min = rate->max =
4185 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
4186 break;
4187 case AFE_PORT_ID_TERTIARY_TDM_TX:
4188 channels->min = channels->max =
4189 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4190 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4191 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4192 rate->min = rate->max =
4193 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4194 break;
4195 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4196 channels->min = channels->max =
4197 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
4198 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4199 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
4200 rate->min = rate->max =
4201 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
4202 break;
4203 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4204 channels->min = channels->max =
4205 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
4206 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4207 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
4208 rate->min = rate->max =
4209 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
4210 break;
4211 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4212 channels->min = channels->max =
4213 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
4214 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4215 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
4216 rate->min = rate->max =
4217 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
4218 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4219 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
4220 channels->min = channels->max =
4221 tdm_tx_cfg[TDM_TERT][TDM_7].channels;
4222 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4223 tdm_tx_cfg[TDM_TERT][TDM_7].bit_format);
4224 rate->min = rate->max =
4225 tdm_tx_cfg[TDM_TERT][TDM_7].sample_rate;
4226 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4227 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4228 channels->min = channels->max =
4229 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4230 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4231 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4232 rate->min = rate->max =
4233 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4234 break;
4235 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4236 channels->min = channels->max =
4237 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
4238 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4239 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
4240 rate->min = rate->max =
4241 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
4242 break;
4243 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4244 channels->min = channels->max =
4245 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
4246 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4247 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
4248 rate->min = rate->max =
4249 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
4250 break;
4251 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4252 channels->min = channels->max =
4253 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
4254 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4255 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
4256 rate->min = rate->max =
4257 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
4258 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4259 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
4260 channels->min = channels->max =
4261 tdm_rx_cfg[TDM_QUAT][TDM_7].channels;
4262 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4263 tdm_rx_cfg[TDM_QUAT][TDM_7].bit_format);
4264 rate->min = rate->max =
4265 tdm_rx_cfg[TDM_QUAT][TDM_7].sample_rate;
4266 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4267 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4268 channels->min = channels->max =
4269 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4270 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4271 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4272 rate->min = rate->max =
4273 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4274 break;
4275 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4276 channels->min = channels->max =
4277 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
4278 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4279 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
4280 rate->min = rate->max =
4281 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
4282 break;
4283 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4284 channels->min = channels->max =
4285 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
4286 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4287 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
4288 rate->min = rate->max =
4289 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
4290 break;
4291 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4292 channels->min = channels->max =
4293 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
4294 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4295 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
4296 rate->min = rate->max =
4297 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
4298 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4299 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4300 channels->min = channels->max =
4301 tdm_tx_cfg[TDM_QUAT][TDM_7].channels;
4302 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4303 tdm_tx_cfg[TDM_QUAT][TDM_7].bit_format);
4304 rate->min = rate->max =
4305 tdm_tx_cfg[TDM_QUAT][TDM_7].sample_rate;
4306 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4307 case AFE_PORT_ID_QUINARY_TDM_RX:
4308 channels->min = channels->max =
4309 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4310 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4311 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4312 rate->min = rate->max =
4313 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4314 break;
4315 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4316 channels->min = channels->max =
4317 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4318 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4319 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4320 rate->min = rate->max =
4321 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4322 break;
4323 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4324 channels->min = channels->max =
4325 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4326 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4327 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4328 rate->min = rate->max =
4329 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4330 break;
4331 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4332 channels->min = channels->max =
4333 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4334 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4335 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4336 rate->min = rate->max =
4337 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4338 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4339 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4340 channels->min = channels->max =
4341 tdm_rx_cfg[TDM_QUIN][TDM_7].channels;
4342 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4343 tdm_rx_cfg[TDM_QUIN][TDM_7].bit_format);
4344 rate->min = rate->max =
4345 tdm_rx_cfg[TDM_QUIN][TDM_7].sample_rate;
4346 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4347 case AFE_PORT_ID_QUINARY_TDM_TX:
4348 channels->min = channels->max =
4349 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4350 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4351 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4352 rate->min = rate->max =
4353 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4354 break;
4355 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4356 channels->min = channels->max =
4357 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4358 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4359 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4360 rate->min = rate->max =
4361 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4362 break;
4363 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4364 channels->min = channels->max =
4365 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4366 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4367 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4368 rate->min = rate->max =
4369 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4370 break;
4371 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4372 channels->min = channels->max =
4373 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4374 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4375 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4376 rate->min = rate->max =
4377 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4378 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4379 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4380 channels->min = channels->max =
4381 tdm_tx_cfg[TDM_QUIN][TDM_7].channels;
4382 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4383 tdm_tx_cfg[TDM_QUIN][TDM_7].bit_format);
4384 rate->min = rate->max =
4385 tdm_tx_cfg[TDM_QUIN][TDM_7].sample_rate;
4386 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4387 default:
4388 pr_err("%s: dai id 0x%x not supported\n",
4389 __func__, cpu_dai->id);
4390 return -EINVAL;
4391 }
4392
4393 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4394 __func__, cpu_dai->id, channels->max, rate->max,
4395 params_format(params));
4396
4397 return 0;
4398}
4399
4400static unsigned int tdm_param_set_slot_mask(int slots)
4401{
4402 unsigned int slot_mask = 0;
4403 int i = 0;
4404
4405 if ((slots <= 0) || (slots > 32)) {
4406 pr_err("%s: invalid slot number %d\n", __func__, slots);
4407 return -EINVAL;
4408 }
4409
4410 for (i = 0; i < slots ; i++)
4411 slot_mask |= 1 << i;
4412 return slot_mask;
4413}
4414
4415static int sa6155_tdm_snd_hw_params(struct snd_pcm_substream *substream,
4416 struct snd_pcm_hw_params *params)
4417{
4418 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4419 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4420 int ret = 0;
4421 int channels, slot_width, slots, rate, format;
4422 unsigned int slot_mask;
4423 unsigned int *slot_offset;
4424 int offset_channels = 0;
4425 int i;
4426 int clk_freq;
4427
4428 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
4429
4430 channels = params_channels(params);
4431 if (channels < 1 || channels > 32) {
4432 pr_err("%s: invalid param channels %d\n",
4433 __func__, channels);
4434 return -EINVAL;
4435 }
4436
4437 format = params_format(params);
4438 if (format != SNDRV_PCM_FORMAT_S32_LE &&
4439 format != SNDRV_PCM_FORMAT_S24_LE &&
4440 format != SNDRV_PCM_FORMAT_S16_LE) {
4441 /*
4442 * Up to 8 channel HW configuration should
4443 * use 32 bit slot width for max support of
4444 * stream bit width. (slot_width > bit_width)
4445 */
4446 pr_err("%s: invalid param format 0x%x\n",
4447 __func__, format);
4448 return -EINVAL;
4449 }
4450
4451 switch (cpu_dai->id) {
4452 case AFE_PORT_ID_PRIMARY_TDM_RX:
4453 slots = tdm_slot[TDM_PRI].num;
4454 slot_width = tdm_slot[TDM_PRI].width;
4455 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
4456 break;
4457 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4458 slots = tdm_slot[TDM_PRI].num;
4459 slot_width = tdm_slot[TDM_PRI].width;
4460 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
4461 break;
4462 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4463 slots = tdm_slot[TDM_PRI].num;
4464 slot_width = tdm_slot[TDM_PRI].width;
4465 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
4466 break;
4467 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4468 slots = tdm_slot[TDM_PRI].num;
4469 slot_width = tdm_slot[TDM_PRI].width;
4470 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
4471 break;
4472 case AFE_PORT_ID_PRIMARY_TDM_TX:
4473 slots = tdm_slot[TDM_PRI].num;
4474 slot_width = tdm_slot[TDM_PRI].width;
4475 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
4476 break;
4477 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4478 slots = tdm_slot[TDM_PRI].num;
4479 slot_width = tdm_slot[TDM_PRI].width;
4480 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
4481 break;
4482 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4483 slots = tdm_slot[TDM_PRI].num;
4484 slot_width = tdm_slot[TDM_PRI].width;
4485 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
4486 break;
4487 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4488 slots = tdm_slot[TDM_PRI].num;
4489 slot_width = tdm_slot[TDM_PRI].width;
4490 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
4491 break;
4492 case AFE_PORT_ID_SECONDARY_TDM_RX:
4493 slots = tdm_slot[TDM_SEC].num;
4494 slot_width = tdm_slot[TDM_SEC].width;
4495 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
4496 break;
4497 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4498 slots = tdm_slot[TDM_SEC].num;
4499 slot_width = tdm_slot[TDM_SEC].width;
4500 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
4501 break;
4502 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4503 slots = tdm_slot[TDM_SEC].num;
4504 slot_width = tdm_slot[TDM_SEC].width;
4505 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
4506 break;
4507 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4508 slots = tdm_slot[TDM_SEC].num;
4509 slot_width = tdm_slot[TDM_SEC].width;
4510 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
4511 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4512 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
4513 slots = tdm_slot[TDM_SEC].num;
4514 slot_width = tdm_slot[TDM_SEC].width;
4515 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_7];
4516 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4517 case AFE_PORT_ID_SECONDARY_TDM_TX:
4518 slots = tdm_slot[TDM_SEC].num;
4519 slot_width = tdm_slot[TDM_SEC].width;
4520 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
4521 break;
4522 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4523 slots = tdm_slot[TDM_SEC].num;
4524 slot_width = tdm_slot[TDM_SEC].width;
4525 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
4526 break;
4527 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4528 slots = tdm_slot[TDM_SEC].num;
4529 slot_width = tdm_slot[TDM_SEC].width;
4530 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
4531 break;
4532 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4533 slots = tdm_slot[TDM_SEC].num;
4534 slot_width = tdm_slot[TDM_SEC].width;
4535 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
4536 break;
4537 case AFE_PORT_ID_TERTIARY_TDM_RX:
4538 slots = tdm_slot[TDM_TERT].num;
4539 slot_width = tdm_slot[TDM_TERT].width;
4540 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
4541 break;
4542 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4543 slots = tdm_slot[TDM_TERT].num;
4544 slot_width = tdm_slot[TDM_TERT].width;
4545 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
4546 break;
4547 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4548 slots = tdm_slot[TDM_TERT].num;
4549 slot_width = tdm_slot[TDM_TERT].width;
4550 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
4551 break;
4552 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4553 slots = tdm_slot[TDM_TERT].num;
4554 slot_width = tdm_slot[TDM_TERT].width;
4555 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
4556 break;
4557 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4558 slots = tdm_slot[TDM_TERT].num;
4559 slot_width = tdm_slot[TDM_TERT].width;
4560 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
4561 break;
4562 case AFE_PORT_ID_TERTIARY_TDM_TX:
4563 slots = tdm_slot[TDM_TERT].num;
4564 slot_width = tdm_slot[TDM_TERT].width;
4565 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
4566 break;
4567 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4568 slots = tdm_slot[TDM_TERT].num;
4569 slot_width = tdm_slot[TDM_TERT].width;
4570 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
4571 break;
4572 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4573 slots = tdm_slot[TDM_TERT].num;
4574 slot_width = tdm_slot[TDM_TERT].width;
4575 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
4576 break;
4577 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4578 slots = tdm_slot[TDM_TERT].num;
4579 slot_width = tdm_slot[TDM_TERT].width;
4580 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
4581 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4582 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
4583 slots = tdm_slot[TDM_TERT].num;
4584 slot_width = tdm_slot[TDM_TERT].width;
4585 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_7];
4586 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4587 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4588 slots = tdm_slot[TDM_QUAT].num;
4589 slot_width = tdm_slot[TDM_QUAT].width;
4590 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
4591 break;
4592 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4593 slots = tdm_slot[TDM_QUAT].num;
4594 slot_width = tdm_slot[TDM_QUAT].width;
4595 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
4596 break;
4597 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4598 slots = tdm_slot[TDM_QUAT].num;
4599 slot_width = tdm_slot[TDM_QUAT].width;
4600 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
4601 break;
4602 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4603 slots = tdm_slot[TDM_QUAT].num;
4604 slot_width = tdm_slot[TDM_QUAT].width;
4605 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
4606 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4607 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
4608 slots = tdm_slot[TDM_QUAT].num;
4609 slot_width = tdm_slot[TDM_QUAT].width;
4610 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_7];
4611 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4612 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4613 slots = tdm_slot[TDM_QUAT].num;
4614 slot_width = tdm_slot[TDM_QUAT].width;
4615 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
4616 break;
4617 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4618 slots = tdm_slot[TDM_QUAT].num;
4619 slot_width = tdm_slot[TDM_QUAT].width;
4620 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
4621 break;
4622 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4623 slots = tdm_slot[TDM_QUAT].num;
4624 slot_width = tdm_slot[TDM_QUAT].width;
4625 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
4626 break;
4627 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4628 slots = tdm_slot[TDM_QUAT].num;
4629 slot_width = tdm_slot[TDM_QUAT].width;
4630 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
4631 break;
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]4632 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4633 slots = tdm_slot[TDM_QUAT].num;
4634 slot_width = tdm_slot[TDM_QUAT].width;
4635 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_7];
4636 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4637 case AFE_PORT_ID_QUINARY_TDM_RX:
4638 slots = tdm_slot[TDM_QUIN].num;
4639 slot_width = tdm_slot[TDM_QUIN].width;
4640 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
4641 break;
4642 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4643 slots = tdm_slot[TDM_QUIN].num;
4644 slot_width = tdm_slot[TDM_QUIN].width;
4645 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
4646 break;
4647 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4648 slots = tdm_slot[TDM_QUIN].num;
4649 slot_width = tdm_slot[TDM_QUIN].width;
4650 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
4651 break;
4652 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4653 slots = tdm_slot[TDM_QUIN].num;
4654 slot_width = tdm_slot[TDM_QUIN].width;
4655 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
4656 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4657 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4658 slots = tdm_slot[TDM_QUIN].num;
4659 slot_width = tdm_slot[TDM_QUIN].width;
4660 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_7];
4661 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4662 case AFE_PORT_ID_QUINARY_TDM_TX:
4663 slots = tdm_slot[TDM_QUIN].num;
4664 slot_width = tdm_slot[TDM_QUIN].width;
4665 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
4666 break;
4667 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4668 slots = tdm_slot[TDM_QUIN].num;
4669 slot_width = tdm_slot[TDM_QUIN].width;
4670 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
4671 break;
4672 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4673 slots = tdm_slot[TDM_QUIN].num;
4674 slot_width = tdm_slot[TDM_QUIN].width;
4675 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
4676 break;
4677 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4678 slots = tdm_slot[TDM_QUIN].num;
4679 slot_width = tdm_slot[TDM_QUIN].width;
4680 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
4681 break;
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4682 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4683 slots = tdm_slot[TDM_QUIN].num;
4684 slot_width = tdm_slot[TDM_QUIN].width;
4685 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_7];
4686 break;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4687 default:
4688 pr_err("%s: dai id 0x%x not supported\n",
4689 __func__, cpu_dai->id);
4690 return -EINVAL;
4691 }
4692
4693 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
4694 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
4695 offset_channels++;
4696 else
4697 break;
4698 }
4699
4700 if (offset_channels == 0) {
4701 pr_err("%s: invalid offset_channels %d\n",
4702 __func__, offset_channels);
4703 return -EINVAL;
4704 }
4705
4706 if (channels > offset_channels) {
4707 pr_err("%s: channels %d exceed offset_channels %d\n",
4708 __func__, channels, offset_channels);
4709 return -EINVAL;
4710 }
4711
4712 slot_mask = tdm_param_set_slot_mask(slots);
4713 if (!slot_mask) {
4714 pr_err("%s: invalid slot_mask 0x%x\n",
4715 __func__, slot_mask);
4716 return -EINVAL;
4717 }
4718
4719 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4720 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
4721 slots, slot_width);
4722 if (ret < 0) {
4723 pr_err("%s: failed to set tdm slot, err:%d\n",
4724 __func__, ret);
4725 goto end;
4726 }
4727
4728 ret = snd_soc_dai_set_channel_map(cpu_dai,
4729 0, NULL, channels, slot_offset);
4730 if (ret < 0) {
4731 pr_err("%s: failed to set channel map, err:%d\n",
4732 __func__, ret);
4733 goto end;
4734 }
4735 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
4736 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
4737 slots, slot_width);
4738 if (ret < 0) {
4739 pr_err("%s: failed to set tdm slot, err:%d\n",
4740 __func__, ret);
4741 goto end;
4742 }
4743
4744 ret = snd_soc_dai_set_channel_map(cpu_dai,
4745 channels, slot_offset, 0, NULL);
4746 if (ret < 0) {
4747 pr_err("%s: failed to set channel map, err:%d\n",
4748 __func__, ret);
4749 goto end;
4750 }
4751 } else {
4752 ret = -EINVAL;
4753 pr_err("%s: invalid use case, err:%d\n",
4754 __func__, ret);
4755 goto end;
4756 }
4757
4758 rate = params_rate(params);
4759 clk_freq = rate * slot_width * slots;
4760 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
4761 if (ret < 0)
4762 pr_err("%s: failed to set tdm clk, err:%d\n",
4763 __func__, ret);
4764
4765end:
4766 return ret;
4767}
4768
4769static int sa6155_tdm_snd_startup(struct snd_pcm_substream *substream)
4770{
4771 int ret = 0;
4772 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4773 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4774 struct snd_soc_card *card = rtd->card;
4775 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4776 struct msm_pinctrl_info *pinctrl_info = NULL;
4777 struct tdm_conf *intf_conf = NULL;
4778 int ret_pinctrl = 0;
4779 int index;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4780
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4781 pr_debug("%s: substream = %s, stream = %d, dai name = %s, dai id = %d\n",
4782 __func__, substream->name, substream->stream,
4783 cpu_dai->name, cpu_dai->id);
4784
4785 index = msm_tdm_get_intf_idx(cpu_dai->id);
4786 if (index < 0) {
4787 ret = -EINVAL;
4788 pr_err("%s: CPU DAI id (%d) out of range\n",
4789 __func__, cpu_dai->id);
4790 goto err;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4791 }
4792
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4793 /*
4794 * Mutex protection in case the same TDM
4795 * interface using for both TX and RX so
4796 * that the same clock won't be enable twice.
4797 */
4798 intf_conf = &pdata->tdm_intf_conf[index];
4799 mutex_lock(&intf_conf->lock);
4800 if (++intf_conf->ref_cnt == 1) {
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4801 if (index == TDM_TERT || index == TDM_QUAT ||
4802 index == TDM_QUIN) {
4803 pinctrl_info = &pdata->pinctrl_info[index];
4804 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4805 STATE_ACTIVE);
4806 if (ret_pinctrl)
4807 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4808 __func__, ret_pinctrl);
4809 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4810 }
4811 mutex_unlock(&intf_conf->lock);
4812
4813err:
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4814 return ret;
4815}
4816
4817static void sa6155_tdm_snd_shutdown(struct snd_pcm_substream *substream)
4818{
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4819 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4820 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4821 struct snd_soc_card *card = rtd->card;
4822 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4823 struct msm_pinctrl_info *pinctrl_info = NULL;
4824 struct tdm_conf *intf_conf = NULL;
4825 int ret_pinctrl = 0;
4826 int index;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4827
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4828 pr_debug("%s: substream = %s, stream = %d\n", __func__,
4829 substream->name, substream->stream);
4830
4831 index = msm_tdm_get_intf_idx(cpu_dai->id);
4832 if (index < 0) {
4833 pr_err("%s: CPU DAI id (%d) out of range\n",
4834 __func__, cpu_dai->id);
4835 return;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4836 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4837
4838 intf_conf = &pdata->tdm_intf_conf[index];
4839 mutex_lock(&intf_conf->lock);
4840 if (--intf_conf->ref_cnt == 0) {
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]4841 if (index == TDM_TERT || index == TDM_QUAT ||
4842 index == TDM_QUIN) {
4843 pinctrl_info = &pdata->pinctrl_info[index];
4844 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4845 STATE_SLEEP);
4846 if (ret_pinctrl)
4847 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4848 __func__, ret_pinctrl);
4849 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4850 }
4851 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4852}
4853
4854static struct snd_soc_ops sa6155_tdm_be_ops = {
4855 .hw_params = sa6155_tdm_snd_hw_params,
4856 .startup = sa6155_tdm_snd_startup,
4857 .shutdown = sa6155_tdm_snd_shutdown
4858};
4859
4860static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
4861{
4862 cpumask_t mask;
4863
4864 if (pm_qos_request_active(&substream->latency_pm_qos_req))
4865 pm_qos_remove_request(&substream->latency_pm_qos_req);
4866
4867 cpumask_clear(&mask);
4868 cpumask_set_cpu(1, &mask); /* affine to core 1 */
4869 cpumask_set_cpu(2, &mask); /* affine to core 2 */
4870 cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
4871
4872 substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
4873
4874 pm_qos_add_request(&substream->latency_pm_qos_req,
4875 PM_QOS_CPU_DMA_LATENCY,
4876 MSM_LL_QOS_VALUE);
4877 return 0;
4878}
4879
4880static struct snd_soc_ops msm_fe_qos_ops = {
4881 .prepare = msm_fe_qos_prepare,
4882};
4883
4884static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4885{
4886 int ret = 0;
4887 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4888 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4889 int index = cpu_dai->id;
4890 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
4891 struct snd_soc_card *card = rtd->card;
4892 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4893 struct msm_pinctrl_info *pinctrl_info = NULL;
4894 struct mi2s_conf *intf_conf = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4895 int ret_pinctrl = 0;
4896
4897 dev_dbg(rtd->card->dev,
4898 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4899 __func__, substream->name, substream->stream,
4900 cpu_dai->name, cpu_dai->id);
4901
4902 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4903 ret = -EINVAL;
4904 dev_err(rtd->card->dev,
4905 "%s: CPU DAI id (%d) out of range\n",
4906 __func__, cpu_dai->id);
4907 goto err;
4908 }
4909 /*
4910 * Mutex protection in case the same MI2S
4911 * interface using for both TX and RX so
4912 * that the same clock won't be enable twice.
4913 */
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4914 intf_conf = &pdata->mi2s_intf_conf[index];
4915 mutex_lock(&intf_conf->lock);
4916 if (++intf_conf->ref_cnt == 1) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4917 /* Check if msm needs to provide the clock to the interface */
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4918 if (!intf_conf->msm_is_mi2s_master) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4919 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4920 fmt = SND_SOC_DAIFMT_CBM_CFM;
4921 }
4922 ret = msm_mi2s_set_sclk(substream, true);
4923 if (ret < 0) {
4924 dev_err(rtd->card->dev,
4925 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4926 __func__, ret);
4927 goto clean_up;
4928 }
4929
4930 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4931 if (ret < 0) {
4932 pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4933 __func__, index, ret);
4934 goto clk_off;
4935 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4936
4937 pinctrl_info = &pdata->pinctrl_info[index];
4938 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4939 STATE_ACTIVE);
4940 if (ret_pinctrl)
4941 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4942 __func__, ret_pinctrl);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4943 }
4944clk_off:
4945 if (ret < 0)
4946 msm_mi2s_set_sclk(substream, false);
4947clean_up:
4948 if (ret < 0)
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4949 intf_conf->ref_cnt--;
4950 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4951err:
4952 return ret;
4953}
4954
4955static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4956{
4957 int ret;
4958 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4959 int index = rtd->cpu_dai->id;
4960 struct snd_soc_card *card = rtd->card;
4961 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4962 struct msm_pinctrl_info *pinctrl_info = NULL;
4963 struct mi2s_conf *intf_conf = NULL;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4964 int ret_pinctrl = 0;
4965
4966 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4967 substream->name, substream->stream);
4968 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4969 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4970 return;
4971 }
4972
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4973 intf_conf = &pdata->mi2s_intf_conf[index];
4974 mutex_lock(&intf_conf->lock);
4975 if (--intf_conf->ref_cnt == 0) {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4976 ret = msm_mi2s_set_sclk(substream, false);
4977 if (ret < 0)
4978 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4979 __func__, index, ret);
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4980
4981 pinctrl_info = &pdata->pinctrl_info[index];
4982 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4983 STATE_SLEEP);
4984 if (ret_pinctrl)
4985 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4986 __func__, ret_pinctrl);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4987 }
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]4988 mutex_unlock(&intf_conf->lock);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]4989}
4990
4991static struct snd_soc_ops msm_mi2s_be_ops = {
4992 .startup = msm_mi2s_snd_startup,
4993 .shutdown = msm_mi2s_snd_shutdown,
4994};
4995
4996
4997/* Digital audio interface glue - connects codec <---> CPU */
4998static struct snd_soc_dai_link msm_common_dai_links[] = {
4999 /* FrontEnd DAI Links */
5000 {
5001 .name = MSM_DAILINK_NAME(Media1),
5002 .stream_name = "MultiMedia1",
5003 .cpu_dai_name = "MultiMedia1",
5004 .platform_name = "msm-pcm-dsp.0",
5005 .dynamic = 1,
5006 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5007 .dpcm_playback = 1,
5008 .dpcm_capture = 1,
5009 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5010 SND_SOC_DPCM_TRIGGER_POST},
5011 .codec_dai_name = "snd-soc-dummy-dai",
5012 .codec_name = "snd-soc-dummy",
5013 .ignore_suspend = 1,
5014 /* this dainlink has playback support */
5015 .ignore_pmdown_time = 1,
5016 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
5017 },
5018 {
5019 .name = MSM_DAILINK_NAME(Media2),
5020 .stream_name = "MultiMedia2",
5021 .cpu_dai_name = "MultiMedia2",
5022 .platform_name = "msm-pcm-dsp.0",
5023 .dynamic = 1,
5024 .dpcm_playback = 1,
5025 .dpcm_capture = 1,
5026 .codec_dai_name = "snd-soc-dummy-dai",
5027 .codec_name = "snd-soc-dummy",
5028 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5029 SND_SOC_DPCM_TRIGGER_POST},
5030 .ignore_suspend = 1,
5031 /* this dainlink has playback support */
5032 .ignore_pmdown_time = 1,
5033 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5034 },
5035 {
5036 .name = "VoiceMMode1",
5037 .stream_name = "VoiceMMode1",
5038 .cpu_dai_name = "VoiceMMode1",
5039 .platform_name = "msm-pcm-voice",
5040 .dynamic = 1,
5041 .dpcm_playback = 1,
5042 .dpcm_capture = 1,
5043 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5044 SND_SOC_DPCM_TRIGGER_POST},
5045 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5046 .ignore_suspend = 1,
5047 .ignore_pmdown_time = 1,
5048 .codec_dai_name = "snd-soc-dummy-dai",
5049 .codec_name = "snd-soc-dummy",
5050 .id = MSM_FRONTEND_DAI_VOICEMMODE1,
5051 },
5052 {
5053 .name = "MSM VoIP",
5054 .stream_name = "VoIP",
5055 .cpu_dai_name = "VoIP",
5056 .platform_name = "msm-voip-dsp",
5057 .dynamic = 1,
5058 .dpcm_playback = 1,
5059 .dpcm_capture = 1,
5060 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5061 SND_SOC_DPCM_TRIGGER_POST},
5062 .codec_dai_name = "snd-soc-dummy-dai",
5063 .codec_name = "snd-soc-dummy",
5064 .ignore_suspend = 1,
5065 /* this dainlink has playback support */
5066 .ignore_pmdown_time = 1,
5067 .id = MSM_FRONTEND_DAI_VOIP,
5068 },
5069 {
5070 .name = MSM_DAILINK_NAME(ULL),
5071 .stream_name = "MultiMedia3",
5072 .cpu_dai_name = "MultiMedia3",
5073 .platform_name = "msm-pcm-dsp.2",
5074 .dynamic = 1,
5075 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5076 .dpcm_playback = 1,
5077 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5078 SND_SOC_DPCM_TRIGGER_POST},
5079 .codec_dai_name = "snd-soc-dummy-dai",
5080 .codec_name = "snd-soc-dummy",
5081 .ignore_suspend = 1,
5082 /* this dainlink has playback support */
5083 .ignore_pmdown_time = 1,
5084 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5085 },
5086 /* - SLIMBUS_0 Hostless */
5087 {
5088 .name = "MSM AFE-PCM RX",
5089 .stream_name = "AFE-PROXY RX",
5090 .cpu_dai_name = "msm-dai-q6-dev.241",
5091 .codec_name = "msm-stub-codec.1",
5092 .codec_dai_name = "msm-stub-rx",
5093 .platform_name = "msm-pcm-afe",
5094 .dpcm_playback = 1,
5095 .ignore_suspend = 1,
5096 /* this dainlink has playback support */
5097 .ignore_pmdown_time = 1,
5098 },
5099 {
5100 .name = "MSM AFE-PCM TX",
5101 .stream_name = "AFE-PROXY TX",
5102 .cpu_dai_name = "msm-dai-q6-dev.240",
5103 .codec_name = "msm-stub-codec.1",
5104 .codec_dai_name = "msm-stub-tx",
5105 .platform_name = "msm-pcm-afe",
5106 .dpcm_capture = 1,
5107 .ignore_suspend = 1,
5108 },
5109 {
5110 .name = MSM_DAILINK_NAME(Compress1),
5111 .stream_name = "Compress1",
5112 .cpu_dai_name = "MultiMedia4",
5113 .platform_name = "msm-compress-dsp",
5114 .dynamic = 1,
5115 .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
5116 .dpcm_playback = 1,
5117 .dpcm_capture = 1,
5118 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5119 SND_SOC_DPCM_TRIGGER_POST},
5120 .codec_dai_name = "snd-soc-dummy-dai",
5121 .codec_name = "snd-soc-dummy",
5122 .ignore_suspend = 1,
5123 .ignore_pmdown_time = 1,
5124 /* this dainlink has playback support */
5125 .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
5126 },
5127 /* Hostless PCM purpose */
5128 {
5129 .name = "AUXPCM Hostless",
5130 .stream_name = "AUXPCM Hostless",
5131 .cpu_dai_name = "AUXPCM_HOSTLESS",
5132 .platform_name = "msm-pcm-hostless",
5133 .dynamic = 1,
5134 .dpcm_playback = 1,
5135 .dpcm_capture = 1,
5136 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5137 SND_SOC_DPCM_TRIGGER_POST},
5138 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5139 .ignore_suspend = 1,
5140 /* this dainlink has playback support */
5141 .ignore_pmdown_time = 1,
5142 .codec_dai_name = "snd-soc-dummy-dai",
5143 .codec_name = "snd-soc-dummy",
5144 },
5145 /* - SLIMBUS_1 Hostless */
5146 /* - SLIMBUS_3 Hostless */
5147 /* - SLIMBUS_4 Hostless */
5148 {
5149 .name = MSM_DAILINK_NAME(LowLatency),
5150 .stream_name = "MultiMedia5",
5151 .cpu_dai_name = "MultiMedia5",
5152 .platform_name = "msm-pcm-dsp.1",
5153 .dynamic = 1,
5154 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5155 .dpcm_playback = 1,
5156 .dpcm_capture = 1,
5157 .codec_dai_name = "snd-soc-dummy-dai",
5158 .codec_name = "snd-soc-dummy",
5159 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5160 SND_SOC_DPCM_TRIGGER_POST},
5161 .ignore_suspend = 1,
5162 /* this dainlink has playback support */
5163 .ignore_pmdown_time = 1,
5164 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
5165 .ops = &msm_fe_qos_ops,
5166 },
5167 {
5168 .name = "Listen 1 Audio Service",
5169 .stream_name = "Listen 1 Audio Service",
5170 .cpu_dai_name = "LSM1",
5171 .platform_name = "msm-lsm-client",
5172 .dynamic = 1,
5173 .dpcm_capture = 1,
5174 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5175 SND_SOC_DPCM_TRIGGER_POST },
5176 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5177 .ignore_suspend = 1,
5178 .codec_dai_name = "snd-soc-dummy-dai",
5179 .codec_name = "snd-soc-dummy",
5180 .id = MSM_FRONTEND_DAI_LSM1,
5181 },
5182 /* Multiple Tunnel instances */
5183 {
5184 .name = MSM_DAILINK_NAME(Compress2),
5185 .stream_name = "Compress2",
5186 .cpu_dai_name = "MultiMedia7",
5187 .platform_name = "msm-compress-dsp",
5188 .dynamic = 1,
5189 .dpcm_playback = 1,
5190 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5191 SND_SOC_DPCM_TRIGGER_POST},
5192 .codec_dai_name = "snd-soc-dummy-dai",
5193 .codec_name = "snd-soc-dummy",
5194 .ignore_suspend = 1,
5195 .ignore_pmdown_time = 1,
5196 /* this dainlink has playback support */
5197 .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
5198 },
5199 {
5200 .name = MSM_DAILINK_NAME(MultiMedia10),
5201 .stream_name = "MultiMedia10",
5202 .cpu_dai_name = "MultiMedia10",
5203 .platform_name = "msm-pcm-dsp.1",
5204 .dynamic = 1,
5205 .dpcm_playback = 1,
5206 .dpcm_capture = 1,
5207 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5208 SND_SOC_DPCM_TRIGGER_POST},
5209 .codec_dai_name = "snd-soc-dummy-dai",
5210 .codec_name = "snd-soc-dummy",
5211 .ignore_suspend = 1,
5212 .ignore_pmdown_time = 1,
5213 /* this dainlink has playback support */
5214 .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
5215 },
5216 {
5217 .name = MSM_DAILINK_NAME(ULL_NOIRQ),
5218 .stream_name = "MM_NOIRQ",
5219 .cpu_dai_name = "MultiMedia8",
5220 .platform_name = "msm-pcm-dsp-noirq",
5221 .dynamic = 1,
5222 .dpcm_playback = 1,
5223 .dpcm_capture = 1,
5224 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5225 SND_SOC_DPCM_TRIGGER_POST},
5226 .codec_dai_name = "snd-soc-dummy-dai",
5227 .codec_name = "snd-soc-dummy",
5228 .ignore_suspend = 1,
5229 .ignore_pmdown_time = 1,
5230 /* this dainlink has playback support */
5231 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5232 .ops = &msm_fe_qos_ops,
5233 },
5234 /* HDMI Hostless */
5235 {
5236 .name = "HDMI_RX_HOSTLESS",
5237 .stream_name = "HDMI_RX_HOSTLESS",
5238 .cpu_dai_name = "HDMI_HOSTLESS",
5239 .platform_name = "msm-pcm-hostless",
5240 .dynamic = 1,
5241 .dpcm_playback = 1,
5242 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5243 SND_SOC_DPCM_TRIGGER_POST},
5244 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5245 .ignore_suspend = 1,
5246 .ignore_pmdown_time = 1,
5247 .codec_dai_name = "snd-soc-dummy-dai",
5248 .codec_name = "snd-soc-dummy",
5249 },
5250 {
5251 .name = "VoiceMMode2",
5252 .stream_name = "VoiceMMode2",
5253 .cpu_dai_name = "VoiceMMode2",
5254 .platform_name = "msm-pcm-voice",
5255 .dynamic = 1,
5256 .dpcm_playback = 1,
5257 .dpcm_capture = 1,
5258 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5259 SND_SOC_DPCM_TRIGGER_POST},
5260 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5261 .ignore_suspend = 1,
5262 .ignore_pmdown_time = 1,
5263 .codec_dai_name = "snd-soc-dummy-dai",
5264 .codec_name = "snd-soc-dummy",
5265 .id = MSM_FRONTEND_DAI_VOICEMMODE2,
5266 },
5267 /* LSM FE */
5268 {
5269 .name = "Listen 2 Audio Service",
5270 .stream_name = "Listen 2 Audio Service",
5271 .cpu_dai_name = "LSM2",
5272 .platform_name = "msm-lsm-client",
5273 .dynamic = 1,
5274 .dpcm_capture = 1,
5275 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5276 SND_SOC_DPCM_TRIGGER_POST },
5277 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5278 .ignore_suspend = 1,
5279 .codec_dai_name = "snd-soc-dummy-dai",
5280 .codec_name = "snd-soc-dummy",
5281 .id = MSM_FRONTEND_DAI_LSM2,
5282 },
5283 {
5284 .name = "Listen 3 Audio Service",
5285 .stream_name = "Listen 3 Audio Service",
5286 .cpu_dai_name = "LSM3",
5287 .platform_name = "msm-lsm-client",
5288 .dynamic = 1,
5289 .dpcm_capture = 1,
5290 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5291 SND_SOC_DPCM_TRIGGER_POST },
5292 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5293 .ignore_suspend = 1,
5294 .codec_dai_name = "snd-soc-dummy-dai",
5295 .codec_name = "snd-soc-dummy",
5296 .id = MSM_FRONTEND_DAI_LSM3,
5297 },
5298 {
5299 .name = "Listen 4 Audio Service",
5300 .stream_name = "Listen 4 Audio Service",
5301 .cpu_dai_name = "LSM4",
5302 .platform_name = "msm-lsm-client",
5303 .dynamic = 1,
5304 .dpcm_capture = 1,
5305 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5306 SND_SOC_DPCM_TRIGGER_POST },
5307 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5308 .ignore_suspend = 1,
5309 .codec_dai_name = "snd-soc-dummy-dai",
5310 .codec_name = "snd-soc-dummy",
5311 .id = MSM_FRONTEND_DAI_LSM4,
5312 },
5313 {
5314 .name = "Listen 5 Audio Service",
5315 .stream_name = "Listen 5 Audio Service",
5316 .cpu_dai_name = "LSM5",
5317 .platform_name = "msm-lsm-client",
5318 .dynamic = 1,
5319 .dpcm_capture = 1,
5320 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5321 SND_SOC_DPCM_TRIGGER_POST },
5322 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5323 .ignore_suspend = 1,
5324 .codec_dai_name = "snd-soc-dummy-dai",
5325 .codec_name = "snd-soc-dummy",
5326 .id = MSM_FRONTEND_DAI_LSM5,
5327 },
5328 {
5329 .name = "Listen 6 Audio Service",
5330 .stream_name = "Listen 6 Audio Service",
5331 .cpu_dai_name = "LSM6",
5332 .platform_name = "msm-lsm-client",
5333 .dynamic = 1,
5334 .dpcm_capture = 1,
5335 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5336 SND_SOC_DPCM_TRIGGER_POST },
5337 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5338 .ignore_suspend = 1,
5339 .codec_dai_name = "snd-soc-dummy-dai",
5340 .codec_name = "snd-soc-dummy",
5341 .id = MSM_FRONTEND_DAI_LSM6,
5342 },
5343 {
5344 .name = "Listen 7 Audio Service",
5345 .stream_name = "Listen 7 Audio Service",
5346 .cpu_dai_name = "LSM7",
5347 .platform_name = "msm-lsm-client",
5348 .dynamic = 1,
5349 .dpcm_capture = 1,
5350 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5351 SND_SOC_DPCM_TRIGGER_POST },
5352 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5353 .ignore_suspend = 1,
5354 .codec_dai_name = "snd-soc-dummy-dai",
5355 .codec_name = "snd-soc-dummy",
5356 .id = MSM_FRONTEND_DAI_LSM7,
5357 },
5358 {
5359 .name = "Listen 8 Audio Service",
5360 .stream_name = "Listen 8 Audio Service",
5361 .cpu_dai_name = "LSM8",
5362 .platform_name = "msm-lsm-client",
5363 .dynamic = 1,
5364 .dpcm_capture = 1,
5365 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5366 SND_SOC_DPCM_TRIGGER_POST },
5367 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5368 .ignore_suspend = 1,
5369 .codec_dai_name = "snd-soc-dummy-dai",
5370 .codec_name = "snd-soc-dummy",
5371 .id = MSM_FRONTEND_DAI_LSM8,
5372 },
5373 /* - Multimedia9 */
5374 {
5375 .name = MSM_DAILINK_NAME(Compress4),
5376 .stream_name = "Compress4",
5377 .cpu_dai_name = "MultiMedia11",
5378 .platform_name = "msm-compress-dsp",
5379 .dynamic = 1,
5380 .dpcm_playback = 1,
5381 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5382 SND_SOC_DPCM_TRIGGER_POST},
5383 .codec_dai_name = "snd-soc-dummy-dai",
5384 .codec_name = "snd-soc-dummy",
5385 .ignore_suspend = 1,
5386 .ignore_pmdown_time = 1,
5387 /* this dainlink has playback support */
5388 .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
5389 },
5390 {
5391 .name = MSM_DAILINK_NAME(Compress5),
5392 .stream_name = "Compress5",
5393 .cpu_dai_name = "MultiMedia12",
5394 .platform_name = "msm-compress-dsp",
5395 .dynamic = 1,
5396 .dpcm_playback = 1,
5397 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5398 SND_SOC_DPCM_TRIGGER_POST},
5399 .codec_dai_name = "snd-soc-dummy-dai",
5400 .codec_name = "snd-soc-dummy",
5401 .ignore_suspend = 1,
5402 .ignore_pmdown_time = 1,
5403 /* this dainlink has playback support */
5404 .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
5405 },
5406 {
5407 .name = MSM_DAILINK_NAME(Compress6),
5408 .stream_name = "Compress6",
5409 .cpu_dai_name = "MultiMedia13",
5410 .platform_name = "msm-compress-dsp",
5411 .dynamic = 1,
5412 .dpcm_playback = 1,
5413 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5414 SND_SOC_DPCM_TRIGGER_POST},
5415 .codec_dai_name = "snd-soc-dummy-dai",
5416 .codec_name = "snd-soc-dummy",
5417 .ignore_suspend = 1,
5418 .ignore_pmdown_time = 1,
5419 /* this dainlink has playback support */
5420 .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
5421 },
5422 {
5423 .name = MSM_DAILINK_NAME(Compress7),
5424 .stream_name = "Compress7",
5425 .cpu_dai_name = "MultiMedia14",
5426 .platform_name = "msm-compress-dsp",
5427 .dynamic = 1,
5428 .dpcm_playback = 1,
5429 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5430 SND_SOC_DPCM_TRIGGER_POST},
5431 .codec_dai_name = "snd-soc-dummy-dai",
5432 .codec_name = "snd-soc-dummy",
5433 .ignore_suspend = 1,
5434 .ignore_pmdown_time = 1,
5435 /* this dainlink has playback support */
5436 .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
5437 },
5438 {
5439 .name = MSM_DAILINK_NAME(Compress8),
5440 .stream_name = "Compress8",
5441 .cpu_dai_name = "MultiMedia15",
5442 .platform_name = "msm-compress-dsp",
5443 .dynamic = 1,
5444 .dpcm_playback = 1,
5445 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5446 SND_SOC_DPCM_TRIGGER_POST},
5447 .codec_dai_name = "snd-soc-dummy-dai",
5448 .codec_name = "snd-soc-dummy",
5449 .ignore_suspend = 1,
5450 .ignore_pmdown_time = 1,
5451 /* this dainlink has playback support */
5452 .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
5453 },
5454 {
5455 .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
5456 .stream_name = "MM_NOIRQ_2",
5457 .cpu_dai_name = "MultiMedia16",
5458 .platform_name = "msm-pcm-dsp-noirq",
5459 .dynamic = 1,
5460 .dpcm_playback = 1,
5461 .dpcm_capture = 1,
5462 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5463 SND_SOC_DPCM_TRIGGER_POST},
5464 .codec_dai_name = "snd-soc-dummy-dai",
5465 .codec_name = "snd-soc-dummy",
5466 .ignore_suspend = 1,
5467 .ignore_pmdown_time = 1,
5468 /* this dainlink has playback support */
5469 .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
5470 },
5471 /* - SLIMBUS_8 Hostless */
5472 /* - Slimbus4 Capture */
5473 /* - SLIMBUS_2 Hostless Playback */
5474 /* - SLIMBUS_2 Hostless Capture */
5475 /* HFP TX */
5476 {
5477 .name = MSM_DAILINK_NAME(ASM Loopback),
5478 .stream_name = "MultiMedia6",
5479 .cpu_dai_name = "MultiMedia6",
5480 .platform_name = "msm-pcm-loopback",
5481 .dynamic = 1,
5482 .dpcm_playback = 1,
5483 .dpcm_capture = 1,
5484 .codec_dai_name = "snd-soc-dummy-dai",
5485 .codec_name = "snd-soc-dummy",
5486 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5487 SND_SOC_DPCM_TRIGGER_POST},
5488 .ignore_suspend = 1,
5489 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5490 .ignore_pmdown_time = 1,
5491 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5492 },
5493 {
5494 .name = "USB Audio Hostless",
5495 .stream_name = "USB Audio Hostless",
5496 .cpu_dai_name = "USBAUDIO_HOSTLESS",
5497 .platform_name = "msm-pcm-hostless",
5498 .dynamic = 1,
5499 .dpcm_playback = 1,
5500 .dpcm_capture = 1,
5501 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5502 SND_SOC_DPCM_TRIGGER_POST},
5503 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5504 .ignore_suspend = 1,
5505 .ignore_pmdown_time = 1,
5506 .codec_dai_name = "snd-soc-dummy-dai",
5507 .codec_name = "snd-soc-dummy",
5508 },
5509 /* - SLIMBUS_7 Hostless */
5510 {
5511 .name = "Compress Capture",
5512 .stream_name = "Compress9",
5513 .cpu_dai_name = "MultiMedia17",
5514 .platform_name = "msm-compress-dsp",
5515 .dynamic = 1,
5516 .dpcm_capture = 1,
5517 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5518 SND_SOC_DPCM_TRIGGER_POST},
5519 .codec_dai_name = "snd-soc-dummy-dai",
5520 .codec_name = "snd-soc-dummy",
5521 .ignore_suspend = 1,
5522 .ignore_pmdown_time = 1,
5523 .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
5524 },
5525};
5526
5527static struct snd_soc_dai_link msm_auto_fe_dai_links[] = {
5528 {
5529 .name = "INT_HFP_BT Hostless",
5530 .stream_name = "INT_HFP_BT Hostless",
5531 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5532 .platform_name = "msm-pcm-hostless",
5533 .dynamic = 1,
5534 .dpcm_playback = 1,
5535 .dpcm_capture = 1,
5536 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5537 SND_SOC_DPCM_TRIGGER_POST},
5538 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5539 .ignore_suspend = 1,
5540 /* this dainlink has playback support */
5541 .ignore_pmdown_time = 1,
5542 .codec_dai_name = "snd-soc-dummy-dai",
5543 .codec_name = "snd-soc-dummy",
5544 },
5545 /* Low latency ASM loopback for ICC */
5546 {
5547 .name = MSM_DAILINK_NAME(LowLatency Loopback),
5548 .stream_name = "MultiMedia9",
5549 .cpu_dai_name = "MultiMedia9",
5550 .platform_name = "msm-pcm-loopback.1",
5551 .dynamic = 1,
5552 .dpcm_playback = 1,
5553 .dpcm_capture = 1,
5554 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5555 SND_SOC_DPCM_TRIGGER_POST},
5556 .codec_dai_name = "snd-soc-dummy-dai",
5557 .codec_name = "snd-soc-dummy",
5558 .ignore_suspend = 1,
5559 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5560 /* this dainlink has playback support */
5561 .ignore_pmdown_time = 1,
5562 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5563 },
5564 {
5565 .name = "Tertiary MI2S TX_Hostless",
5566 .stream_name = "Tertiary MI2S_TX Hostless Capture",
5567 .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
5568 .platform_name = "msm-pcm-hostless",
5569 .dynamic = 1,
5570 .dpcm_capture = 1,
5571 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5572 SND_SOC_DPCM_TRIGGER_POST},
5573 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5574 .ignore_suspend = 1,
5575 .ignore_pmdown_time = 1,
5576 .codec_dai_name = "snd-soc-dummy-dai",
5577 .codec_name = "snd-soc-dummy",
5578 },
5579 {
5580 .name = MSM_DAILINK_NAME(Media20),
5581 .stream_name = "MultiMedia20",
5582 .cpu_dai_name = "MultiMedia20",
5583 .platform_name = "msm-pcm-loopback",
5584 .dynamic = 1,
5585 .dpcm_playback = 1,
5586 .dpcm_capture = 1,
5587 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5588 SND_SOC_DPCM_TRIGGER_POST},
5589 .codec_dai_name = "snd-soc-dummy-dai",
5590 .codec_name = "snd-soc-dummy",
5591 .ignore_suspend = 1,
5592 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5593 /* this dainlink has playback support */
5594 .ignore_pmdown_time = 1,
5595 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5596 },
5597 {
5598 .name = MSM_DAILINK_NAME(HFP RX),
5599 .stream_name = "MultiMedia21",
5600 .cpu_dai_name = "MultiMedia21",
5601 .platform_name = "msm-pcm-loopback",
5602 .dynamic = 1,
5603 .dpcm_playback = 1,
5604 .dpcm_capture = 1,
5605 .codec_dai_name = "snd-soc-dummy-dai",
5606 .codec_name = "snd-soc-dummy",
5607 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5608 SND_SOC_DPCM_TRIGGER_POST},
5609 .ignore_suspend = 1,
5610 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5611 .ignore_pmdown_time = 1,
5612 .id = MSM_FRONTEND_DAI_MULTIMEDIA21,
5613 },
5614 /* TDM Hostless */
5615 {
5616 .name = "Primary TDM RX 0 Hostless",
5617 .stream_name = "Primary TDM RX 0 Hostless",
5618 .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS",
5619 .platform_name = "msm-pcm-hostless",
5620 .dynamic = 1,
5621 .dpcm_playback = 1,
5622 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5623 SND_SOC_DPCM_TRIGGER_POST},
5624 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5625 .ignore_suspend = 1,
5626 .ignore_pmdown_time = 1,
5627 .codec_dai_name = "snd-soc-dummy-dai",
5628 .codec_name = "snd-soc-dummy",
5629 },
5630 {
5631 .name = "Primary TDM TX 0 Hostless",
5632 .stream_name = "Primary TDM TX 0 Hostless",
5633 .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS",
5634 .platform_name = "msm-pcm-hostless",
5635 .dynamic = 1,
5636 .dpcm_capture = 1,
5637 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5638 SND_SOC_DPCM_TRIGGER_POST},
5639 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5640 .ignore_suspend = 1,
5641 .ignore_pmdown_time = 1,
5642 .codec_dai_name = "snd-soc-dummy-dai",
5643 .codec_name = "snd-soc-dummy",
5644 },
5645 {
5646 .name = "Secondary TDM RX 0 Hostless",
5647 .stream_name = "Secondary TDM RX 0 Hostless",
5648 .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS",
5649 .platform_name = "msm-pcm-hostless",
5650 .dynamic = 1,
5651 .dpcm_playback = 1,
5652 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5653 SND_SOC_DPCM_TRIGGER_POST},
5654 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5655 .ignore_suspend = 1,
5656 .ignore_pmdown_time = 1,
5657 .codec_dai_name = "snd-soc-dummy-dai",
5658 .codec_name = "snd-soc-dummy",
5659 },
5660 {
5661 .name = "Secondary TDM TX 0 Hostless",
5662 .stream_name = "Secondary TDM TX 0 Hostless",
5663 .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS",
5664 .platform_name = "msm-pcm-hostless",
5665 .dynamic = 1,
5666 .dpcm_capture = 1,
5667 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5668 SND_SOC_DPCM_TRIGGER_POST},
5669 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5670 .ignore_suspend = 1,
5671 .ignore_pmdown_time = 1,
5672 .codec_dai_name = "snd-soc-dummy-dai",
5673 .codec_name = "snd-soc-dummy",
5674 },
5675 {
5676 .name = "Tertiary TDM RX 0 Hostless",
5677 .stream_name = "Tertiary TDM RX 0 Hostless",
5678 .cpu_dai_name = "TERT_TDM_RX_0_HOSTLESS",
5679 .platform_name = "msm-pcm-hostless",
5680 .dynamic = 1,
5681 .dpcm_playback = 1,
5682 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5683 SND_SOC_DPCM_TRIGGER_POST},
5684 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5685 .ignore_suspend = 1,
5686 .ignore_pmdown_time = 1,
5687 .codec_dai_name = "snd-soc-dummy-dai",
5688 .codec_name = "snd-soc-dummy",
5689 },
5690 {
5691 .name = "Tertiary TDM TX 0 Hostless",
5692 .stream_name = "Tertiary TDM TX 0 Hostless",
5693 .cpu_dai_name = "TERT_TDM_TX_0_HOSTLESS",
5694 .platform_name = "msm-pcm-hostless",
5695 .dynamic = 1,
5696 .dpcm_capture = 1,
5697 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5698 SND_SOC_DPCM_TRIGGER_POST},
5699 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5700 .ignore_suspend = 1,
5701 .ignore_pmdown_time = 1,
5702 .codec_dai_name = "snd-soc-dummy-dai",
5703 .codec_name = "snd-soc-dummy",
5704 },
5705 {
5706 .name = "Quaternary TDM RX 0 Hostless",
5707 .stream_name = "Quaternary TDM RX 0 Hostless",
5708 .cpu_dai_name = "QUAT_TDM_RX_0_HOSTLESS",
5709 .platform_name = "msm-pcm-hostless",
5710 .dynamic = 1,
5711 .dpcm_playback = 1,
5712 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5713 SND_SOC_DPCM_TRIGGER_POST},
5714 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5715 .ignore_suspend = 1,
5716 .ignore_pmdown_time = 1,
5717 .codec_dai_name = "snd-soc-dummy-dai",
5718 .codec_name = "snd-soc-dummy",
5719 },
5720 {
5721 .name = "Quaternary TDM TX 0 Hostless",
5722 .stream_name = "Quaternary TDM TX 0 Hostless",
5723 .cpu_dai_name = "QUAT_TDM_TX_0_HOSTLESS",
5724 .platform_name = "msm-pcm-hostless",
5725 .dynamic = 1,
5726 .dpcm_capture = 1,
5727 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5728 SND_SOC_DPCM_TRIGGER_POST},
5729 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5730 .ignore_suspend = 1,
5731 .ignore_pmdown_time = 1,
5732 .codec_dai_name = "snd-soc-dummy-dai",
5733 .codec_name = "snd-soc-dummy",
5734 },
5735 {
5736 .name = "Quaternary MI2S_RX Hostless Playback",
5737 .stream_name = "Quaternary MI2S_RX Hostless Playback",
5738 .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS",
5739 .platform_name = "msm-pcm-hostless",
5740 .dynamic = 1,
5741 .dpcm_playback = 1,
5742 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5743 SND_SOC_DPCM_TRIGGER_POST},
5744 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5745 .ignore_suspend = 1,
5746 .ignore_pmdown_time = 1,
5747 .codec_dai_name = "snd-soc-dummy-dai",
5748 .codec_name = "snd-soc-dummy",
5749 },
5750 {
5751 .name = "Secondary MI2S_TX Hostless Capture",
5752 .stream_name = "Secondary MI2S_TX Hostless Capture",
5753 .cpu_dai_name = "SEC_MI2S_TX_HOSTLESS",
5754 .platform_name = "msm-pcm-hostless",
5755 .dynamic = 1,
5756 .dpcm_capture = 1,
5757 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5758 SND_SOC_DPCM_TRIGGER_POST},
5759 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5760 .ignore_suspend = 1,
5761 .ignore_pmdown_time = 1,
5762 .codec_dai_name = "snd-soc-dummy-dai",
5763 .codec_name = "snd-soc-dummy",
5764 },
5765 {
5766 .name = "DTMF RX Hostless",
5767 .stream_name = "DTMF RX Hostless",
5768 .cpu_dai_name = "DTMF_RX_HOSTLESS",
5769 .platform_name = "msm-pcm-dtmf",
5770 .dynamic = 1,
5771 .dpcm_playback = 1,
5772 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5773 SND_SOC_DPCM_TRIGGER_POST},
5774 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5775 .ignore_suspend = 1,
5776 .ignore_pmdown_time = 1,
5777 .codec_dai_name = "snd-soc-dummy-dai",
5778 .codec_name = "snd-soc-dummy",
5779 .id = MSM_FRONTEND_DAI_DTMF_RX,
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]5780 },
5781 {
5782 .name = "Secondary TDM RX 7 Hostless",
5783 .stream_name = "Secondary TDM RX 7 Hostless",
5784 .cpu_dai_name = "SEC_TDM_RX_7_HOSTLESS",
5785 .platform_name = "msm-pcm-hostless",
5786 .dynamic = 1,
5787 .dpcm_playback = 1,
5788 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5789 SND_SOC_DPCM_TRIGGER_POST},
5790 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5791 .ignore_suspend = 1,
5792 .ignore_pmdown_time = 1,
5793 .codec_dai_name = "snd-soc-dummy-dai",
5794 .codec_name = "snd-soc-dummy",
5795 },
5796 {
5797 .name = "Tertiary TDM TX 7 Hostless",
5798 .stream_name = "Tertiary TDM TX 7 Hostless",
5799 .cpu_dai_name = "TERT_TDM_TX_7_HOSTLESS",
5800 .platform_name = "msm-pcm-hostless",
5801 .dynamic = 1,
5802 .dpcm_capture = 1,
5803 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5804 SND_SOC_DPCM_TRIGGER_POST},
5805 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5806 .ignore_suspend = 1,
5807 .ignore_pmdown_time = 1,
5808 .codec_dai_name = "snd-soc-dummy-dai",
5809 .codec_name = "snd-soc-dummy",
5810 },
5811 {
5812 .name = "Quaternary TDM RX 7 Hostless",
5813 .stream_name = "Quaternary TDM RX 7 Hostless",
5814 .cpu_dai_name = "QUAT_TDM_RX_7_HOSTLESS",
5815 .platform_name = "msm-pcm-hostless",
5816 .dynamic = 1,
5817 .dpcm_playback = 1,
5818 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5819 SND_SOC_DPCM_TRIGGER_POST},
5820 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5821 .ignore_suspend = 1,
5822 .ignore_pmdown_time = 1,
5823 .codec_dai_name = "snd-soc-dummy-dai",
5824 .codec_name = "snd-soc-dummy",
5825 },
5826 {
5827 .name = "Quaternary TDM TX 7 Hostless",
5828 .stream_name = "Quaternary TDM TX 7 Hostless",
5829 .cpu_dai_name = "QUAT_TDM_TX_7_HOSTLESS",
5830 .platform_name = "msm-pcm-hostless",
5831 .dynamic = 1,
5832 .dpcm_capture = 1,
5833 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5834 SND_SOC_DPCM_TRIGGER_POST},
5835 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5836 .ignore_suspend = 1,
5837 .ignore_pmdown_time = 1,
5838 .codec_dai_name = "snd-soc-dummy-dai",
5839 .codec_name = "snd-soc-dummy",
5840 },
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]5841 {
5842 .name = "Quinary TDM RX 7 Hostless",
5843 .stream_name = "Quinary TDM RX 7 Hostless",
5844 .cpu_dai_name = "QUIN_TDM_RX_7_HOSTLESS",
5845 .platform_name = "msm-pcm-hostless",
5846 .dynamic = 1,
5847 .dpcm_playback = 1,
5848 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5849 SND_SOC_DPCM_TRIGGER_POST},
5850 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5851 .ignore_suspend = 1,
5852 .ignore_pmdown_time = 1,
5853 .codec_dai_name = "snd-soc-dummy-dai",
5854 .codec_name = "snd-soc-dummy",
5855 },
5856 {
5857 .name = "Quinary TDM TX 7 Hostless",
5858 .stream_name = "Quinary TDM TX 7 Hostless",
5859 .cpu_dai_name = "QUIN_TDM_TX_7_HOSTLESS",
5860 .platform_name = "msm-pcm-hostless",
5861 .dynamic = 1,
5862 .dpcm_capture = 1,
5863 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5864 SND_SOC_DPCM_TRIGGER_POST},
5865 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5866 .ignore_suspend = 1,
5867 .ignore_pmdown_time = 1,
5868 .codec_dai_name = "snd-soc-dummy-dai",
5869 .codec_name = "snd-soc-dummy",
5870 },
Derek Chen6c052da2019-07-31 17:30:46 -0700[diff] [blame]5871 {
5872 .name = MSM_DAILINK_NAME(Media22),
5873 .stream_name = "MultiMedia22",
5874 .cpu_dai_name = "MultiMedia22",
5875 .platform_name = "msm-pcm-dsp.0",
5876 .dynamic = 1,
5877 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5878 .dpcm_playback = 1,
5879 .dpcm_capture = 1,
5880 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5881 SND_SOC_DPCM_TRIGGER_POST},
5882 .codec_dai_name = "snd-soc-dummy-dai",
5883 .codec_name = "snd-soc-dummy",
5884 .ignore_suspend = 1,
5885 .ignore_pmdown_time = 1,
5886 .id = MSM_FRONTEND_DAI_MULTIMEDIA22
5887 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]5888};
5889
5890static struct snd_soc_dai_link msm_custom_fe_dai_links[] = {
5891 /* FrontEnd DAI Links */
5892 {
5893 .name = MSM_DAILINK_NAME(Media1),
5894 .stream_name = "MultiMedia1",
5895 .cpu_dai_name = "MultiMedia1",
5896 .platform_name = "msm-pcm-dsp.1",
5897 .dynamic = 1,
5898 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5899 .dpcm_playback = 1,
5900 .dpcm_capture = 1,
5901 .codec_dai_name = "snd-soc-dummy-dai",
5902 .codec_name = "snd-soc-dummy",
5903 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5904 SND_SOC_DPCM_TRIGGER_POST},
5905 .ignore_suspend = 1,
5906 /* this dainlink has playback support */
5907 .ignore_pmdown_time = 1,
5908 .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
5909 .ops = &msm_fe_qos_ops,
5910 },
5911 {
5912 .name = MSM_DAILINK_NAME(Media2),
5913 .stream_name = "MultiMedia2",
5914 .cpu_dai_name = "MultiMedia2",
5915 .platform_name = "msm-pcm-dsp.1",
5916 .dynamic = 1,
5917 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5918 .dpcm_playback = 1,
5919 .dpcm_capture = 1,
5920 .codec_dai_name = "snd-soc-dummy-dai",
5921 .codec_name = "snd-soc-dummy",
5922 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5923 SND_SOC_DPCM_TRIGGER_POST},
5924 .ignore_suspend = 1,
5925 /* this dainlink has playback support */
5926 .ignore_pmdown_time = 1,
5927 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5928 .ops = &msm_fe_qos_ops,
5929 },
5930 {
5931 .name = MSM_DAILINK_NAME(Media3),
5932 .stream_name = "MultiMedia3",
5933 .cpu_dai_name = "MultiMedia3",
5934 .platform_name = "msm-pcm-dsp.1",
5935 .dynamic = 1,
5936 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5937 .dpcm_playback = 1,
5938 .dpcm_capture = 1,
5939 .codec_dai_name = "snd-soc-dummy-dai",
5940 .codec_name = "snd-soc-dummy",
5941 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5942 SND_SOC_DPCM_TRIGGER_POST},
5943 .ignore_suspend = 1,
5944 /* this dainlink has playback support */
5945 .ignore_pmdown_time = 1,
5946 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5947 .ops = &msm_fe_qos_ops,
5948 },
5949 {
5950 .name = MSM_DAILINK_NAME(Media5),
5951 .stream_name = "MultiMedia5",
5952 .cpu_dai_name = "MultiMedia5",
5953 .platform_name = "msm-pcm-dsp.1",
5954 .dynamic = 1,
5955 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5956 .dpcm_playback = 1,
5957 .dpcm_capture = 1,
5958 .codec_dai_name = "snd-soc-dummy-dai",
5959 .codec_name = "snd-soc-dummy",
5960 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5961 SND_SOC_DPCM_TRIGGER_POST},
5962 .ignore_suspend = 1,
5963 /* this dainlink has playback support */
5964 .ignore_pmdown_time = 1,
5965 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
5966 .ops = &msm_fe_qos_ops,
5967 },
5968 {
5969 .name = MSM_DAILINK_NAME(Media6),
5970 .stream_name = "MultiMedia6",
5971 .cpu_dai_name = "MultiMedia6",
5972 .platform_name = "msm-pcm-dsp.1",
5973 .dynamic = 1,
5974 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5975 .dpcm_playback = 1,
5976 .dpcm_capture = 1,
5977 .codec_dai_name = "snd-soc-dummy-dai",
5978 .codec_name = "snd-soc-dummy",
5979 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5980 SND_SOC_DPCM_TRIGGER_POST},
5981 .ignore_suspend = 1,
5982 /* this dainlink has playback support */
5983 .ignore_pmdown_time = 1,
5984 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5985 .ops = &msm_fe_qos_ops,
5986 },
5987 {
5988 .name = MSM_DAILINK_NAME(Media8),
5989 .stream_name = "MultiMedia8",
5990 .cpu_dai_name = "MultiMedia8",
5991 .platform_name = "msm-pcm-dsp.1",
5992 .dynamic = 1,
5993 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5994 .dpcm_playback = 1,
5995 .dpcm_capture = 1,
5996 .codec_dai_name = "snd-soc-dummy-dai",
5997 .codec_name = "snd-soc-dummy",
5998 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5999 SND_SOC_DPCM_TRIGGER_POST},
6000 .ignore_suspend = 1,
6001 /* this dainlink has playback support */
6002 .ignore_pmdown_time = 1,
6003 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
6004 .ops = &msm_fe_qos_ops,
6005 },
6006 {
6007 .name = MSM_DAILINK_NAME(Media9),
6008 .stream_name = "MultiMedia9",
6009 .cpu_dai_name = "MultiMedia9",
6010 .platform_name = "msm-pcm-dsp.1",
6011 .dynamic = 1,
6012 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6013 .dpcm_playback = 1,
6014 .dpcm_capture = 1,
6015 .codec_dai_name = "snd-soc-dummy-dai",
6016 .codec_name = "snd-soc-dummy",
6017 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6018 SND_SOC_DPCM_TRIGGER_POST},
6019 .ignore_suspend = 1,
6020 /* this dainlink has playback support */
6021 .ignore_pmdown_time = 1,
6022 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
6023 .ops = &msm_fe_qos_ops,
6024 },
6025 {
6026 .name = "INT_HFP_BT Hostless",
6027 .stream_name = "INT_HFP_BT Hostless",
6028 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
6029 .platform_name = "msm-pcm-hostless",
6030 .dynamic = 1,
6031 .dpcm_playback = 1,
6032 .dpcm_capture = 1,
6033 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6034 SND_SOC_DPCM_TRIGGER_POST},
6035 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6036 .ignore_suspend = 1,
6037 /* this dainlink has playback support */
6038 .ignore_pmdown_time = 1,
6039 .codec_dai_name = "snd-soc-dummy-dai",
6040 .codec_name = "snd-soc-dummy",
6041 },
6042 {
6043 .name = "AUXPCM Hostless",
6044 .stream_name = "AUXPCM Hostless",
6045 .cpu_dai_name = "AUXPCM_HOSTLESS",
6046 .platform_name = "msm-pcm-hostless",
6047 .dynamic = 1,
6048 .dpcm_playback = 1,
6049 .dpcm_capture = 1,
6050 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6051 SND_SOC_DPCM_TRIGGER_POST},
6052 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6053 .ignore_suspend = 1,
6054 /* this dainlink has playback support */
6055 .ignore_pmdown_time = 1,
6056 .codec_dai_name = "snd-soc-dummy-dai",
6057 .codec_name = "snd-soc-dummy",
6058 },
6059 {
6060 .name = MSM_DAILINK_NAME(Media20),
6061 .stream_name = "MultiMedia20",
6062 .cpu_dai_name = "MultiMedia20",
6063 .platform_name = "msm-pcm-loopback",
6064 .dynamic = 1,
6065 .dpcm_playback = 1,
6066 .dpcm_capture = 1,
6067 .codec_dai_name = "snd-soc-dummy-dai",
6068 .codec_name = "snd-soc-dummy",
6069 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6070 SND_SOC_DPCM_TRIGGER_POST},
6071 .ignore_suspend = 1,
6072 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6073 /* this dainlink has playback support */
6074 .ignore_pmdown_time = 1,
6075 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
6076 },
6077};
6078
6079static struct snd_soc_dai_link msm_common_be_dai_links[] = {
6080 /* Backend AFE DAI Links */
6081 {
6082 .name = LPASS_BE_AFE_PCM_RX,
6083 .stream_name = "AFE Playback",
6084 .cpu_dai_name = "msm-dai-q6-dev.224",
6085 .platform_name = "msm-pcm-routing",
6086 .codec_name = "msm-stub-codec.1",
6087 .codec_dai_name = "msm-stub-rx",
6088 .no_pcm = 1,
6089 .dpcm_playback = 1,
6090 .id = MSM_BACKEND_DAI_AFE_PCM_RX,
6091 .be_hw_params_fixup = msm_be_hw_params_fixup,
6092 /* this dainlink has playback support */
6093 .ignore_pmdown_time = 1,
6094 .ignore_suspend = 1,
6095 },
6096 {
6097 .name = LPASS_BE_AFE_PCM_TX,
6098 .stream_name = "AFE Capture",
6099 .cpu_dai_name = "msm-dai-q6-dev.225",
6100 .platform_name = "msm-pcm-routing",
6101 .codec_name = "msm-stub-codec.1",
6102 .codec_dai_name = "msm-stub-tx",
6103 .no_pcm = 1,
6104 .dpcm_capture = 1,
6105 .id = MSM_BACKEND_DAI_AFE_PCM_TX,
6106 .be_hw_params_fixup = msm_be_hw_params_fixup,
6107 .ignore_suspend = 1,
6108 },
6109 /* Incall Record Uplink BACK END DAI Link */
6110 {
6111 .name = LPASS_BE_INCALL_RECORD_TX,
6112 .stream_name = "Voice Uplink Capture",
6113 .cpu_dai_name = "msm-dai-q6-dev.32772",
6114 .platform_name = "msm-pcm-routing",
6115 .codec_name = "msm-stub-codec.1",
6116 .codec_dai_name = "msm-stub-tx",
6117 .no_pcm = 1,
6118 .dpcm_capture = 1,
6119 .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
6120 .be_hw_params_fixup = msm_be_hw_params_fixup,
6121 .ignore_suspend = 1,
6122 },
6123 /* Incall Record Downlink BACK END DAI Link */
6124 {
6125 .name = LPASS_BE_INCALL_RECORD_RX,
6126 .stream_name = "Voice Downlink Capture",
6127 .cpu_dai_name = "msm-dai-q6-dev.32771",
6128 .platform_name = "msm-pcm-routing",
6129 .codec_name = "msm-stub-codec.1",
6130 .codec_dai_name = "msm-stub-tx",
6131 .no_pcm = 1,
6132 .dpcm_capture = 1,
6133 .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
6134 .be_hw_params_fixup = msm_be_hw_params_fixup,
6135 .ignore_suspend = 1,
6136 },
6137 /* Incall Music BACK END DAI Link */
6138 {
6139 .name = LPASS_BE_VOICE_PLAYBACK_TX,
6140 .stream_name = "Voice Farend Playback",
6141 .cpu_dai_name = "msm-dai-q6-dev.32773",
6142 .platform_name = "msm-pcm-routing",
6143 .codec_name = "msm-stub-codec.1",
6144 .codec_dai_name = "msm-stub-rx",
6145 .no_pcm = 1,
6146 .dpcm_playback = 1,
6147 .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
6148 .be_hw_params_fixup = msm_be_hw_params_fixup,
6149 .ignore_suspend = 1,
6150 .ignore_pmdown_time = 1,
6151 },
6152 /* Incall Music 2 BACK END DAI Link */
6153 {
6154 .name = LPASS_BE_VOICE2_PLAYBACK_TX,
6155 .stream_name = "Voice2 Farend Playback",
6156 .cpu_dai_name = "msm-dai-q6-dev.32770",
6157 .platform_name = "msm-pcm-routing",
6158 .codec_name = "msm-stub-codec.1",
6159 .codec_dai_name = "msm-stub-rx",
6160 .no_pcm = 1,
6161 .dpcm_playback = 1,
6162 .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
6163 .be_hw_params_fixup = msm_be_hw_params_fixup,
6164 .ignore_suspend = 1,
6165 .ignore_pmdown_time = 1,
6166 },
6167 {
6168 .name = LPASS_BE_USB_AUDIO_RX,
6169 .stream_name = "USB Audio Playback",
6170 .cpu_dai_name = "msm-dai-q6-dev.28672",
6171 .platform_name = "msm-pcm-routing",
6172 .codec_name = "msm-stub-codec.1",
6173 .codec_dai_name = "msm-stub-rx",
6174 .no_pcm = 1,
6175 .dpcm_playback = 1,
6176 .id = MSM_BACKEND_DAI_USB_RX,
6177 .be_hw_params_fixup = msm_be_hw_params_fixup,
6178 .ignore_pmdown_time = 1,
6179 .ignore_suspend = 1,
6180 },
6181 {
6182 .name = LPASS_BE_USB_AUDIO_TX,
6183 .stream_name = "USB Audio Capture",
6184 .cpu_dai_name = "msm-dai-q6-dev.28673",
6185 .platform_name = "msm-pcm-routing",
6186 .codec_name = "msm-stub-codec.1",
6187 .codec_dai_name = "msm-stub-tx",
6188 .no_pcm = 1,
6189 .dpcm_capture = 1,
6190 .id = MSM_BACKEND_DAI_USB_TX,
6191 .be_hw_params_fixup = msm_be_hw_params_fixup,
6192 .ignore_suspend = 1,
6193 },
6194 {
6195 .name = LPASS_BE_PRI_TDM_RX_0,
6196 .stream_name = "Primary TDM0 Playback",
6197 .cpu_dai_name = "msm-dai-q6-tdm.36864",
6198 .platform_name = "msm-pcm-routing",
6199 .codec_name = "msm-stub-codec.1",
6200 .codec_dai_name = "msm-stub-rx",
6201 .no_pcm = 1,
6202 .dpcm_playback = 1,
6203 .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
6204 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6205 .ops = &sa6155_tdm_be_ops,
6206 .ignore_suspend = 1,
6207 .ignore_pmdown_time = 1,
6208 },
6209 {
6210 .name = LPASS_BE_PRI_TDM_TX_0,
6211 .stream_name = "Primary TDM0 Capture",
6212 .cpu_dai_name = "msm-dai-q6-tdm.36865",
6213 .platform_name = "msm-pcm-routing",
6214 .codec_name = "msm-stub-codec.1",
6215 .codec_dai_name = "msm-stub-tx",
6216 .no_pcm = 1,
6217 .dpcm_capture = 1,
6218 .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
6219 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6220 .ops = &sa6155_tdm_be_ops,
6221 .ignore_suspend = 1,
6222 },
6223 {
6224 .name = LPASS_BE_SEC_TDM_RX_0,
6225 .stream_name = "Secondary TDM0 Playback",
6226 .cpu_dai_name = "msm-dai-q6-tdm.36880",
6227 .platform_name = "msm-pcm-routing",
6228 .codec_name = "msm-stub-codec.1",
6229 .codec_dai_name = "msm-stub-rx",
6230 .no_pcm = 1,
6231 .dpcm_playback = 1,
6232 .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
6233 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6234 .ops = &sa6155_tdm_be_ops,
6235 .ignore_suspend = 1,
6236 .ignore_pmdown_time = 1,
6237 },
6238 {
6239 .name = LPASS_BE_SEC_TDM_TX_0,
6240 .stream_name = "Secondary TDM0 Capture",
6241 .cpu_dai_name = "msm-dai-q6-tdm.36881",
6242 .platform_name = "msm-pcm-routing",
6243 .codec_name = "msm-stub-codec.1",
6244 .codec_dai_name = "msm-stub-tx",
6245 .no_pcm = 1,
6246 .dpcm_capture = 1,
6247 .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
6248 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6249 .ops = &sa6155_tdm_be_ops,
6250 .ignore_suspend = 1,
6251 },
6252 {
6253 .name = LPASS_BE_TERT_TDM_RX_0,
6254 .stream_name = "Tertiary TDM0 Playback",
6255 .cpu_dai_name = "msm-dai-q6-tdm.36896",
6256 .platform_name = "msm-pcm-routing",
6257 .codec_name = "msm-stub-codec.1",
6258 .codec_dai_name = "msm-stub-rx",
6259 .no_pcm = 1,
6260 .dpcm_playback = 1,
6261 .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
6262 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6263 .ops = &sa6155_tdm_be_ops,
6264 .ignore_suspend = 1,
6265 .ignore_pmdown_time = 1,
6266 },
6267 {
6268 .name = LPASS_BE_TERT_TDM_TX_0,
6269 .stream_name = "Tertiary TDM0 Capture",
6270 .cpu_dai_name = "msm-dai-q6-tdm.36897",
6271 .platform_name = "msm-pcm-routing",
6272 .codec_name = "msm-stub-codec.1",
6273 .codec_dai_name = "msm-stub-tx",
6274 .no_pcm = 1,
6275 .dpcm_capture = 1,
6276 .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
6277 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6278 .ops = &sa6155_tdm_be_ops,
6279 .ignore_suspend = 1,
6280 },
6281 {
6282 .name = LPASS_BE_QUAT_TDM_RX_0,
6283 .stream_name = "Quaternary TDM0 Playback",
6284 .cpu_dai_name = "msm-dai-q6-tdm.36912",
6285 .platform_name = "msm-pcm-routing",
6286 .codec_name = "msm-stub-codec.1",
6287 .codec_dai_name = "msm-stub-rx",
6288 .no_pcm = 1,
6289 .dpcm_playback = 1,
6290 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
6291 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6292 .ops = &sa6155_tdm_be_ops,
6293 .ignore_suspend = 1,
6294 .ignore_pmdown_time = 1,
6295 },
6296 {
6297 .name = LPASS_BE_QUAT_TDM_TX_0,
6298 .stream_name = "Quaternary TDM0 Capture",
6299 .cpu_dai_name = "msm-dai-q6-tdm.36913",
6300 .platform_name = "msm-pcm-routing",
6301 .codec_name = "msm-stub-codec.1",
6302 .codec_dai_name = "msm-stub-tx",
6303 .no_pcm = 1,
6304 .dpcm_capture = 1,
6305 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
6306 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6307 .ops = &sa6155_tdm_be_ops,
6308 .ignore_suspend = 1,
6309 },
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]6310 {
6311 .name = LPASS_BE_QUIN_TDM_RX_0,
6312 .stream_name = "Quinary TDM0 Playback",
6313 .cpu_dai_name = "msm-dai-q6-tdm.36928",
6314 .platform_name = "msm-pcm-routing",
6315 .codec_name = "msm-stub-codec.1",
6316 .codec_dai_name = "msm-stub-rx",
6317 .no_pcm = 1,
6318 .dpcm_playback = 1,
6319 .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
6320 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6321 .ops = &sa6155_tdm_be_ops,
6322 .ignore_suspend = 1,
6323 .ignore_pmdown_time = 1,
6324 },
6325 {
6326 .name = LPASS_BE_QUIN_TDM_TX_0,
6327 .stream_name = "Quinary TDM0 Capture",
6328 .cpu_dai_name = "msm-dai-q6-tdm.36929",
6329 .platform_name = "msm-pcm-routing",
6330 .codec_name = "msm-stub-codec.1",
6331 .codec_dai_name = "msm-stub-tx",
6332 .no_pcm = 1,
6333 .dpcm_capture = 1,
6334 .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
6335 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6336 .ops = &sa6155_tdm_be_ops,
6337 .ignore_suspend = 1,
6338 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6339};
6340
6341static struct snd_soc_dai_link msm_auto_be_dai_links[] = {
6342 /* Backend DAI Links */
6343 {
6344 .name = LPASS_BE_PRI_TDM_RX_1,
6345 .stream_name = "Primary TDM1 Playback",
6346 .cpu_dai_name = "msm-dai-q6-tdm.36866",
6347 .platform_name = "msm-pcm-routing",
6348 .codec_name = "msm-stub-codec.1",
6349 .codec_dai_name = "msm-stub-rx",
6350 .no_pcm = 1,
6351 .dpcm_playback = 1,
6352 .id = MSM_BACKEND_DAI_PRI_TDM_RX_1,
6353 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6354 .ops = &sa6155_tdm_be_ops,
6355 .ignore_suspend = 1,
6356 },
6357 {
6358 .name = LPASS_BE_PRI_TDM_RX_2,
6359 .stream_name = "Primary TDM2 Playback",
6360 .cpu_dai_name = "msm-dai-q6-tdm.36868",
6361 .platform_name = "msm-pcm-routing",
6362 .codec_name = "msm-stub-codec.1",
6363 .codec_dai_name = "msm-stub-rx",
6364 .no_pcm = 1,
6365 .dpcm_playback = 1,
6366 .id = MSM_BACKEND_DAI_PRI_TDM_RX_2,
6367 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6368 .ops = &sa6155_tdm_be_ops,
6369 .ignore_suspend = 1,
6370 },
6371 {
6372 .name = LPASS_BE_PRI_TDM_RX_3,
6373 .stream_name = "Primary TDM3 Playback",
6374 .cpu_dai_name = "msm-dai-q6-tdm.36870",
6375 .platform_name = "msm-pcm-routing",
6376 .codec_name = "msm-stub-codec.1",
6377 .codec_dai_name = "msm-stub-rx",
6378 .no_pcm = 1,
6379 .dpcm_playback = 1,
6380 .id = MSM_BACKEND_DAI_PRI_TDM_RX_3,
6381 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6382 .ops = &sa6155_tdm_be_ops,
6383 .ignore_suspend = 1,
6384 },
6385 {
6386 .name = LPASS_BE_PRI_TDM_TX_1,
6387 .stream_name = "Primary TDM1 Capture",
6388 .cpu_dai_name = "msm-dai-q6-tdm.36867",
6389 .platform_name = "msm-pcm-routing",
6390 .codec_name = "msm-stub-codec.1",
6391 .codec_dai_name = "msm-stub-rx",
6392 .no_pcm = 1,
6393 .dpcm_capture = 1,
6394 .id = MSM_BACKEND_DAI_PRI_TDM_TX_1,
6395 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6396 .ops = &sa6155_tdm_be_ops,
6397 .ignore_suspend = 1,
6398 },
6399 {
6400 .name = LPASS_BE_PRI_TDM_TX_2,
6401 .stream_name = "Primary TDM2 Capture",
6402 .cpu_dai_name = "msm-dai-q6-tdm.36869",
6403 .platform_name = "msm-pcm-routing",
6404 .codec_name = "msm-stub-codec.1",
6405 .codec_dai_name = "msm-stub-rx",
6406 .no_pcm = 1,
6407 .dpcm_capture = 1,
6408 .id = MSM_BACKEND_DAI_PRI_TDM_TX_2,
6409 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6410 .ops = &sa6155_tdm_be_ops,
6411 .ignore_suspend = 1,
6412 },
6413 {
6414 .name = LPASS_BE_PRI_TDM_TX_3,
6415 .stream_name = "Primary TDM3 Capture",
6416 .cpu_dai_name = "msm-dai-q6-tdm.36871",
6417 .platform_name = "msm-pcm-routing",
6418 .codec_name = "msm-stub-codec.1",
6419 .codec_dai_name = "msm-stub-rx",
6420 .no_pcm = 1,
6421 .dpcm_capture = 1,
6422 .id = MSM_BACKEND_DAI_PRI_TDM_TX_3,
6423 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6424 .ops = &sa6155_tdm_be_ops,
6425 .ignore_suspend = 1,
6426 },
6427 {
6428 .name = LPASS_BE_SEC_TDM_RX_1,
6429 .stream_name = "Secondary TDM1 Playback",
6430 .cpu_dai_name = "msm-dai-q6-tdm.36882",
6431 .platform_name = "msm-pcm-routing",
6432 .codec_name = "msm-stub-codec.1",
6433 .codec_dai_name = "msm-stub-rx",
6434 .no_pcm = 1,
6435 .dpcm_playback = 1,
6436 .id = MSM_BACKEND_DAI_SEC_TDM_RX_1,
6437 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6438 .ops = &sa6155_tdm_be_ops,
6439 .ignore_suspend = 1,
6440 },
6441 {
6442 .name = LPASS_BE_SEC_TDM_RX_2,
6443 .stream_name = "Secondary TDM2 Playback",
6444 .cpu_dai_name = "msm-dai-q6-tdm.36884",
6445 .platform_name = "msm-pcm-routing",
6446 .codec_name = "msm-stub-codec.1",
6447 .codec_dai_name = "msm-stub-rx",
6448 .no_pcm = 1,
6449 .dpcm_playback = 1,
6450 .id = MSM_BACKEND_DAI_SEC_TDM_RX_2,
6451 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6452 .ops = &sa6155_tdm_be_ops,
6453 .ignore_suspend = 1,
6454 },
6455 {
6456 .name = LPASS_BE_SEC_TDM_RX_3,
6457 .stream_name = "Secondary TDM3 Playback",
6458 .cpu_dai_name = "msm-dai-q6-tdm.36886",
6459 .platform_name = "msm-pcm-routing",
6460 .codec_name = "msm-stub-codec.1",
6461 .codec_dai_name = "msm-stub-rx",
6462 .no_pcm = 1,
6463 .dpcm_playback = 1,
6464 .id = MSM_BACKEND_DAI_SEC_TDM_RX_3,
6465 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6466 .ops = &sa6155_tdm_be_ops,
6467 .ignore_suspend = 1,
6468 },
6469 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6470 .name = LPASS_BE_SEC_TDM_RX_7,
6471 .stream_name = "Secondary TDM7 Playback",
6472 .cpu_dai_name = "msm-dai-q6-tdm.36894",
6473 .platform_name = "msm-pcm-routing",
6474 .codec_name = "msm-stub-codec.1",
6475 .codec_dai_name = "msm-stub-rx",
6476 .no_pcm = 1,
6477 .dpcm_playback = 1,
6478 .id = MSM_BACKEND_DAI_SEC_TDM_RX_7,
6479 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6480 .ops = &sa6155_tdm_be_ops,
6481 .ignore_suspend = 1,
6482 },
6483 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6484 .name = LPASS_BE_SEC_TDM_TX_1,
6485 .stream_name = "Secondary TDM1 Capture",
6486 .cpu_dai_name = "msm-dai-q6-tdm.36883",
6487 .platform_name = "msm-pcm-routing",
6488 .codec_name = "msm-stub-codec.1",
6489 .codec_dai_name = "msm-stub-rx",
6490 .no_pcm = 1,
6491 .dpcm_capture = 1,
6492 .id = MSM_BACKEND_DAI_SEC_TDM_TX_1,
6493 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6494 .ops = &sa6155_tdm_be_ops,
6495 .ignore_suspend = 1,
6496 },
6497 {
6498 .name = LPASS_BE_SEC_TDM_TX_2,
6499 .stream_name = "Secondary TDM2 Capture",
6500 .cpu_dai_name = "msm-dai-q6-tdm.36885",
6501 .platform_name = "msm-pcm-routing",
6502 .codec_name = "msm-stub-codec.1",
6503 .codec_dai_name = "msm-stub-rx",
6504 .no_pcm = 1,
6505 .dpcm_capture = 1,
6506 .id = MSM_BACKEND_DAI_SEC_TDM_TX_2,
6507 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6508 .ops = &sa6155_tdm_be_ops,
6509 .ignore_suspend = 1,
6510 },
6511 {
6512 .name = LPASS_BE_SEC_TDM_TX_3,
6513 .stream_name = "Secondary TDM3 Capture",
6514 .cpu_dai_name = "msm-dai-q6-tdm.36887",
6515 .platform_name = "msm-pcm-routing",
6516 .codec_name = "msm-stub-codec.1",
6517 .codec_dai_name = "msm-stub-rx",
6518 .no_pcm = 1,
6519 .dpcm_capture = 1,
6520 .id = MSM_BACKEND_DAI_SEC_TDM_TX_3,
6521 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6522 .ops = &sa6155_tdm_be_ops,
6523 .ignore_suspend = 1,
6524 },
6525 {
6526 .name = LPASS_BE_TERT_TDM_RX_1,
6527 .stream_name = "Tertiary TDM1 Playback",
6528 .cpu_dai_name = "msm-dai-q6-tdm.36898",
6529 .platform_name = "msm-pcm-routing",
6530 .codec_name = "msm-stub-codec.1",
6531 .codec_dai_name = "msm-stub-rx",
6532 .no_pcm = 1,
6533 .dpcm_playback = 1,
6534 .id = MSM_BACKEND_DAI_TERT_TDM_RX_1,
6535 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6536 .ops = &sa6155_tdm_be_ops,
6537 .ignore_suspend = 1,
6538 },
6539 {
6540 .name = LPASS_BE_TERT_TDM_RX_2,
6541 .stream_name = "Tertiary TDM2 Playback",
6542 .cpu_dai_name = "msm-dai-q6-tdm.36900",
6543 .platform_name = "msm-pcm-routing",
6544 .codec_name = "msm-stub-codec.1",
6545 .codec_dai_name = "msm-stub-rx",
6546 .no_pcm = 1,
6547 .dpcm_playback = 1,
6548 .id = MSM_BACKEND_DAI_TERT_TDM_RX_2,
6549 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6550 .ops = &sa6155_tdm_be_ops,
6551 .ignore_suspend = 1,
6552 },
6553 {
6554 .name = LPASS_BE_TERT_TDM_RX_3,
6555 .stream_name = "Tertiary TDM3 Playback",
6556 .cpu_dai_name = "msm-dai-q6-tdm.36902",
6557 .platform_name = "msm-pcm-routing",
6558 .codec_name = "msm-stub-codec.1",
6559 .codec_dai_name = "msm-stub-rx",
6560 .no_pcm = 1,
6561 .dpcm_playback = 1,
6562 .id = MSM_BACKEND_DAI_TERT_TDM_RX_3,
6563 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6564 .ops = &sa6155_tdm_be_ops,
6565 .ignore_suspend = 1,
6566 },
6567 {
6568 .name = LPASS_BE_TERT_TDM_RX_4,
6569 .stream_name = "Tertiary TDM4 Playback",
6570 .cpu_dai_name = "msm-dai-q6-tdm.36904",
6571 .platform_name = "msm-pcm-routing",
6572 .codec_name = "msm-stub-codec.1",
6573 .codec_dai_name = "msm-stub-rx",
6574 .no_pcm = 1,
6575 .dpcm_playback = 1,
6576 .id = MSM_BACKEND_DAI_TERT_TDM_RX_4,
6577 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6578 .ops = &sa6155_tdm_be_ops,
6579 .ignore_suspend = 1,
6580 },
6581 {
6582 .name = LPASS_BE_TERT_TDM_TX_1,
6583 .stream_name = "Tertiary TDM1 Capture",
6584 .cpu_dai_name = "msm-dai-q6-tdm.36899",
6585 .platform_name = "msm-pcm-routing",
6586 .codec_name = "msm-stub-codec.1",
6587 .codec_dai_name = "msm-stub-rx",
6588 .no_pcm = 1,
6589 .dpcm_capture = 1,
6590 .id = MSM_BACKEND_DAI_TERT_TDM_TX_1,
6591 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6592 .ops = &sa6155_tdm_be_ops,
6593 .ignore_suspend = 1,
6594 },
6595 {
6596 .name = LPASS_BE_TERT_TDM_TX_2,
6597 .stream_name = "Tertiary TDM2 Capture",
6598 .cpu_dai_name = "msm-dai-q6-tdm.36901",
6599 .platform_name = "msm-pcm-routing",
6600 .codec_name = "msm-stub-codec.1",
6601 .codec_dai_name = "msm-stub-rx",
6602 .no_pcm = 1,
6603 .dpcm_capture = 1,
6604 .id = MSM_BACKEND_DAI_TERT_TDM_TX_2,
6605 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6606 .ops = &sa6155_tdm_be_ops,
6607 .ignore_suspend = 1,
6608 },
6609 {
6610 .name = LPASS_BE_TERT_TDM_TX_3,
6611 .stream_name = "Tertiary TDM3 Capture",
6612 .cpu_dai_name = "msm-dai-q6-tdm.36903",
6613 .platform_name = "msm-pcm-routing",
6614 .codec_name = "msm-stub-codec.1",
6615 .codec_dai_name = "msm-stub-rx",
6616 .no_pcm = 1,
6617 .dpcm_capture = 1,
6618 .id = MSM_BACKEND_DAI_TERT_TDM_TX_3,
6619 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6620 .ops = &sa6155_tdm_be_ops,
6621 .ignore_suspend = 1,
6622 },
6623 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6624 .name = LPASS_BE_TERT_TDM_TX_7,
6625 .stream_name = "Tertiary TDM7 Capture",
6626 .cpu_dai_name = "msm-dai-q6-tdm.36911",
6627 .platform_name = "msm-pcm-routing",
6628 .codec_name = "msm-stub-codec.1",
6629 .codec_dai_name = "msm-stub-rx",
6630 .no_pcm = 1,
6631 .dpcm_capture = 1,
6632 .id = MSM_BACKEND_DAI_TERT_TDM_TX_7,
6633 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6634 .ops = &sa6155_tdm_be_ops,
6635 .ignore_suspend = 1,
6636 },
6637 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6638 .name = LPASS_BE_QUAT_TDM_RX_1,
6639 .stream_name = "Quaternary TDM1 Playback",
6640 .cpu_dai_name = "msm-dai-q6-tdm.36914",
6641 .platform_name = "msm-pcm-routing",
6642 .codec_name = "msm-stub-codec.1",
6643 .codec_dai_name = "msm-stub-rx",
6644 .no_pcm = 1,
6645 .dpcm_playback = 1,
6646 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_1,
6647 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6648 .ops = &sa6155_tdm_be_ops,
6649 .ignore_suspend = 1,
6650 },
6651 {
6652 .name = LPASS_BE_QUAT_TDM_RX_2,
6653 .stream_name = "Quaternary TDM2 Playback",
6654 .cpu_dai_name = "msm-dai-q6-tdm.36916",
6655 .platform_name = "msm-pcm-routing",
6656 .codec_name = "msm-stub-codec.1",
6657 .codec_dai_name = "msm-stub-rx",
6658 .no_pcm = 1,
6659 .dpcm_playback = 1,
6660 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_2,
6661 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6662 .ops = &sa6155_tdm_be_ops,
6663 .ignore_suspend = 1,
6664 },
6665 {
6666 .name = LPASS_BE_QUAT_TDM_RX_3,
6667 .stream_name = "Quaternary TDM3 Playback",
6668 .cpu_dai_name = "msm-dai-q6-tdm.36918",
6669 .platform_name = "msm-pcm-routing",
6670 .codec_name = "msm-stub-codec.1",
6671 .codec_dai_name = "msm-stub-rx",
6672 .no_pcm = 1,
6673 .dpcm_playback = 1,
6674 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_3,
6675 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6676 .ops = &sa6155_tdm_be_ops,
6677 .ignore_suspend = 1,
6678 },
6679 {
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6680 .name = LPASS_BE_QUAT_TDM_RX_7,
6681 .stream_name = "Quaternary TDM7 Playback",
6682 .cpu_dai_name = "msm-dai-q6-tdm.36926",
6683 .platform_name = "msm-pcm-routing",
6684 .codec_name = "msm-stub-codec.1",
6685 .codec_dai_name = "msm-stub-rx",
6686 .no_pcm = 1,
6687 .dpcm_playback = 1,
6688 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_7,
6689 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6690 .ops = &sa6155_tdm_be_ops,
6691 .ignore_suspend = 1,
6692 },
6693 {
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6694 .name = LPASS_BE_QUAT_TDM_TX_1,
6695 .stream_name = "Quaternary TDM1 Capture",
6696 .cpu_dai_name = "msm-dai-q6-tdm.36915",
6697 .platform_name = "msm-pcm-routing",
6698 .codec_name = "msm-stub-codec.1",
6699 .codec_dai_name = "msm-stub-rx",
6700 .no_pcm = 1,
6701 .dpcm_capture = 1,
6702 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_1,
6703 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6704 .ops = &sa6155_tdm_be_ops,
6705 .ignore_suspend = 1,
6706 },
6707 {
6708 .name = LPASS_BE_QUAT_TDM_TX_2,
6709 .stream_name = "Quaternary TDM2 Capture",
6710 .cpu_dai_name = "msm-dai-q6-tdm.36917",
6711 .platform_name = "msm-pcm-routing",
6712 .codec_name = "msm-stub-codec.1",
6713 .codec_dai_name = "msm-stub-rx",
6714 .no_pcm = 1,
6715 .dpcm_capture = 1,
6716 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_2,
6717 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6718 .ops = &sa6155_tdm_be_ops,
6719 .ignore_suspend = 1,
6720 },
6721 {
6722 .name = LPASS_BE_QUAT_TDM_TX_3,
6723 .stream_name = "Quaternary TDM3 Capture",
6724 .cpu_dai_name = "msm-dai-q6-tdm.36919",
6725 .platform_name = "msm-pcm-routing",
6726 .codec_name = "msm-stub-codec.1",
6727 .codec_dai_name = "msm-stub-rx",
6728 .no_pcm = 1,
6729 .dpcm_capture = 1,
6730 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_3,
6731 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6732 .ops = &sa6155_tdm_be_ops,
6733 .ignore_suspend = 1,
6734 },
Derek Chen0150b832019-06-05 18:46:29 +0530[diff] [blame]6735 {
6736 .name = LPASS_BE_QUAT_TDM_TX_7,
6737 .stream_name = "Quaternary TDM7 Capture",
6738 .cpu_dai_name = "msm-dai-q6-tdm.36927",
6739 .platform_name = "msm-pcm-routing",
6740 .codec_name = "msm-stub-codec.1",
6741 .codec_dai_name = "msm-stub-rx",
6742 .no_pcm = 1,
6743 .dpcm_capture = 1,
6744 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_7,
6745 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6746 .ops = &sa6155_tdm_be_ops,
6747 .ignore_suspend = 1,
6748 },
Derek Chen47883832019-06-25 13:40:25 -0700[diff] [blame]6749 {
6750 .name = LPASS_BE_QUIN_TDM_RX_7,
6751 .stream_name = "Quinary TDM7 Playback",
6752 .cpu_dai_name = "msm-dai-q6-tdm.36942",
6753 .platform_name = "msm-pcm-routing",
6754 .codec_name = "msm-stub-codec.1",
6755 .codec_dai_name = "msm-stub-rx",
6756 .no_pcm = 1,
6757 .dpcm_playback = 1,
6758 .id = MSM_BACKEND_DAI_QUIN_TDM_RX_7,
6759 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6760 .ops = &sa6155_tdm_be_ops,
6761 .ignore_suspend = 1,
6762 },
6763 {
6764 .name = LPASS_BE_QUIN_TDM_TX_7,
6765 .stream_name = "Quinary TDM7 Capture",
6766 .cpu_dai_name = "msm-dai-q6-tdm.36943",
6767 .platform_name = "msm-pcm-routing",
6768 .codec_name = "msm-stub-codec.1",
6769 .codec_dai_name = "msm-stub-rx",
6770 .no_pcm = 1,
6771 .dpcm_capture = 1,
6772 .id = MSM_BACKEND_DAI_QUIN_TDM_TX_7,
6773 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6774 .ops = &sa6155_tdm_be_ops,
6775 .ignore_suspend = 1,
6776 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6777};
6778
6779static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
6780 /* DISP PORT BACK END DAI Link */
6781 {
6782 .name = LPASS_BE_DISPLAY_PORT,
6783 .stream_name = "Display Port Playback",
6784 .cpu_dai_name = "msm-dai-q6-dp.24608",
6785 .platform_name = "msm-pcm-routing",
6786 .codec_name = "msm-ext-disp-audio-codec-rx",
6787 .codec_dai_name = "msm_dp_audio_codec_rx_dai",
6788 .no_pcm = 1,
6789 .dpcm_playback = 1,
6790 .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
6791 .be_hw_params_fixup = msm_be_hw_params_fixup,
6792 .ignore_pmdown_time = 1,
6793 .ignore_suspend = 1,
6794 },
6795};
6796
6797static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
6798 {
6799 .name = LPASS_BE_PRI_MI2S_RX,
6800 .stream_name = "Primary MI2S Playback",
6801 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6802 .platform_name = "msm-pcm-routing",
6803 .codec_name = "msm-stub-codec.1",
6804 .codec_dai_name = "msm-stub-rx",
6805 .no_pcm = 1,
6806 .dpcm_playback = 1,
6807 .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
6808 .be_hw_params_fixup = msm_be_hw_params_fixup,
6809 .ops = &msm_mi2s_be_ops,
6810 .ignore_suspend = 1,
6811 .ignore_pmdown_time = 1,
6812 },
6813 {
6814 .name = LPASS_BE_PRI_MI2S_TX,
6815 .stream_name = "Primary MI2S Capture",
6816 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6817 .platform_name = "msm-pcm-routing",
6818 .codec_name = "msm-stub-codec.1",
6819 .codec_dai_name = "msm-stub-tx",
6820 .no_pcm = 1,
6821 .dpcm_capture = 1,
6822 .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
6823 .be_hw_params_fixup = msm_be_hw_params_fixup,
6824 .ops = &msm_mi2s_be_ops,
6825 .ignore_suspend = 1,
6826 },
6827 {
6828 .name = LPASS_BE_SEC_MI2S_RX,
6829 .stream_name = "Secondary MI2S Playback",
6830 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6831 .platform_name = "msm-pcm-routing",
6832 .codec_name = "msm-stub-codec.1",
6833 .codec_dai_name = "msm-stub-rx",
6834 .no_pcm = 1,
6835 .dpcm_playback = 1,
6836 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
6837 .be_hw_params_fixup = msm_be_hw_params_fixup,
6838 .ops = &msm_mi2s_be_ops,
6839 .ignore_suspend = 1,
6840 .ignore_pmdown_time = 1,
6841 },
6842 {
6843 .name = LPASS_BE_SEC_MI2S_TX,
6844 .stream_name = "Secondary MI2S Capture",
6845 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6846 .platform_name = "msm-pcm-routing",
6847 .codec_name = "msm-stub-codec.1",
6848 .codec_dai_name = "msm-stub-tx",
6849 .no_pcm = 1,
6850 .dpcm_capture = 1,
6851 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
6852 .be_hw_params_fixup = msm_be_hw_params_fixup,
6853 .ops = &msm_mi2s_be_ops,
6854 .ignore_suspend = 1,
6855 },
6856 {
6857 .name = LPASS_BE_TERT_MI2S_RX,
6858 .stream_name = "Tertiary MI2S Playback",
6859 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6860 .platform_name = "msm-pcm-routing",
6861 .codec_name = "msm-stub-codec.1",
6862 .codec_dai_name = "msm-stub-rx",
6863 .no_pcm = 1,
6864 .dpcm_playback = 1,
6865 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
6866 .be_hw_params_fixup = msm_be_hw_params_fixup,
6867 .ops = &msm_mi2s_be_ops,
6868 .ignore_suspend = 1,
6869 .ignore_pmdown_time = 1,
6870 },
6871 {
6872 .name = LPASS_BE_TERT_MI2S_TX,
6873 .stream_name = "Tertiary MI2S Capture",
6874 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6875 .platform_name = "msm-pcm-routing",
6876 .codec_name = "msm-stub-codec.1",
6877 .codec_dai_name = "msm-stub-tx",
6878 .no_pcm = 1,
6879 .dpcm_capture = 1,
6880 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
6881 .be_hw_params_fixup = msm_be_hw_params_fixup,
6882 .ops = &msm_mi2s_be_ops,
6883 .ignore_suspend = 1,
6884 },
6885 {
6886 .name = LPASS_BE_QUAT_MI2S_RX,
6887 .stream_name = "Quaternary MI2S Playback",
6888 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6889 .platform_name = "msm-pcm-routing",
6890 .codec_name = "msm-stub-codec.1",
6891 .codec_dai_name = "msm-stub-rx",
6892 .no_pcm = 1,
6893 .dpcm_playback = 1,
6894 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
6895 .be_hw_params_fixup = msm_be_hw_params_fixup,
6896 .ops = &msm_mi2s_be_ops,
6897 .ignore_suspend = 1,
6898 .ignore_pmdown_time = 1,
6899 },
6900 {
6901 .name = LPASS_BE_QUAT_MI2S_TX,
6902 .stream_name = "Quaternary MI2S Capture",
6903 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6904 .platform_name = "msm-pcm-routing",
6905 .codec_name = "msm-stub-codec.1",
6906 .codec_dai_name = "msm-stub-tx",
6907 .no_pcm = 1,
6908 .dpcm_capture = 1,
6909 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
6910 .be_hw_params_fixup = msm_be_hw_params_fixup,
6911 .ops = &msm_mi2s_be_ops,
6912 .ignore_suspend = 1,
6913 },
6914 {
6915 .name = LPASS_BE_QUIN_MI2S_RX,
6916 .stream_name = "Quinary MI2S Playback",
6917 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6918 .platform_name = "msm-pcm-routing",
6919 .codec_name = "msm-stub-codec.1",
6920 .codec_dai_name = "msm-stub-rx",
6921 .no_pcm = 1,
6922 .dpcm_playback = 1,
6923 .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
6924 .be_hw_params_fixup = msm_be_hw_params_fixup,
6925 .ops = &msm_mi2s_be_ops,
6926 .ignore_suspend = 1,
6927 .ignore_pmdown_time = 1,
6928 },
6929 {
6930 .name = LPASS_BE_QUIN_MI2S_TX,
6931 .stream_name = "Quinary MI2S Capture",
6932 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6933 .platform_name = "msm-pcm-routing",
6934 .codec_name = "msm-stub-codec.1",
6935 .codec_dai_name = "msm-stub-tx",
6936 .no_pcm = 1,
6937 .dpcm_capture = 1,
6938 .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
6939 .be_hw_params_fixup = msm_be_hw_params_fixup,
6940 .ops = &msm_mi2s_be_ops,
6941 .ignore_suspend = 1,
6942 },
6943};
6944
6945static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
6946 /* Primary AUX PCM Backend DAI Links */
6947 {
6948 .name = LPASS_BE_AUXPCM_RX,
6949 .stream_name = "AUX PCM Playback",
6950 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6951 .platform_name = "msm-pcm-routing",
6952 .codec_name = "msm-stub-codec.1",
6953 .codec_dai_name = "msm-stub-rx",
6954 .no_pcm = 1,
6955 .dpcm_playback = 1,
6956 .id = MSM_BACKEND_DAI_AUXPCM_RX,
6957 .be_hw_params_fixup = msm_be_hw_params_fixup,
6958 .ignore_pmdown_time = 1,
6959 .ignore_suspend = 1,
6960 },
6961 {
6962 .name = LPASS_BE_AUXPCM_TX,
6963 .stream_name = "AUX PCM Capture",
6964 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6965 .platform_name = "msm-pcm-routing",
6966 .codec_name = "msm-stub-codec.1",
6967 .codec_dai_name = "msm-stub-tx",
6968 .no_pcm = 1,
6969 .dpcm_capture = 1,
6970 .id = MSM_BACKEND_DAI_AUXPCM_TX,
6971 .be_hw_params_fixup = msm_be_hw_params_fixup,
6972 .ignore_suspend = 1,
6973 },
6974 /* Secondary AUX PCM Backend DAI Links */
6975 {
6976 .name = LPASS_BE_SEC_AUXPCM_RX,
6977 .stream_name = "Sec AUX PCM Playback",
6978 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6979 .platform_name = "msm-pcm-routing",
6980 .codec_name = "msm-stub-codec.1",
6981 .codec_dai_name = "msm-stub-rx",
6982 .no_pcm = 1,
6983 .dpcm_playback = 1,
6984 .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
6985 .be_hw_params_fixup = msm_be_hw_params_fixup,
6986 .ignore_pmdown_time = 1,
6987 .ignore_suspend = 1,
6988 },
6989 {
6990 .name = LPASS_BE_SEC_AUXPCM_TX,
6991 .stream_name = "Sec AUX PCM Capture",
6992 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6993 .platform_name = "msm-pcm-routing",
6994 .codec_name = "msm-stub-codec.1",
6995 .codec_dai_name = "msm-stub-tx",
6996 .no_pcm = 1,
6997 .dpcm_capture = 1,
6998 .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
6999 .be_hw_params_fixup = msm_be_hw_params_fixup,
7000 .ignore_suspend = 1,
7001 },
7002 /* Tertiary AUX PCM Backend DAI Links */
7003 {
7004 .name = LPASS_BE_TERT_AUXPCM_RX,
7005 .stream_name = "Tert AUX PCM Playback",
7006 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7007 .platform_name = "msm-pcm-routing",
7008 .codec_name = "msm-stub-codec.1",
7009 .codec_dai_name = "msm-stub-rx",
7010 .no_pcm = 1,
7011 .dpcm_playback = 1,
7012 .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
7013 .be_hw_params_fixup = msm_be_hw_params_fixup,
7014 .ignore_suspend = 1,
7015 },
7016 {
7017 .name = LPASS_BE_TERT_AUXPCM_TX,
7018 .stream_name = "Tert AUX PCM Capture",
7019 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7020 .platform_name = "msm-pcm-routing",
7021 .codec_name = "msm-stub-codec.1",
7022 .codec_dai_name = "msm-stub-tx",
7023 .no_pcm = 1,
7024 .dpcm_capture = 1,
7025 .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
7026 .be_hw_params_fixup = msm_be_hw_params_fixup,
7027 .ignore_suspend = 1,
7028 },
7029 /* Quaternary AUX PCM Backend DAI Links */
7030 {
7031 .name = LPASS_BE_QUAT_AUXPCM_RX,
7032 .stream_name = "Quat AUX PCM Playback",
7033 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7034 .platform_name = "msm-pcm-routing",
7035 .codec_name = "msm-stub-codec.1",
7036 .codec_dai_name = "msm-stub-rx",
7037 .no_pcm = 1,
7038 .dpcm_playback = 1,
7039 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
7040 .be_hw_params_fixup = msm_be_hw_params_fixup,
7041 .ignore_pmdown_time = 1,
7042 .ignore_suspend = 1,
7043 },
7044 {
7045 .name = LPASS_BE_QUAT_AUXPCM_TX,
7046 .stream_name = "Quat AUX PCM Capture",
7047 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7048 .platform_name = "msm-pcm-routing",
7049 .codec_name = "msm-stub-codec.1",
7050 .codec_dai_name = "msm-stub-tx",
7051 .no_pcm = 1,
7052 .dpcm_capture = 1,
7053 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
7054 .be_hw_params_fixup = msm_be_hw_params_fixup,
7055 .ignore_suspend = 1,
7056 },
7057 /* Quinary AUX PCM Backend DAI Links */
7058 {
7059 .name = LPASS_BE_QUIN_AUXPCM_RX,
7060 .stream_name = "Quin AUX PCM Playback",
7061 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7062 .platform_name = "msm-pcm-routing",
7063 .codec_name = "msm-stub-codec.1",
7064 .codec_dai_name = "msm-stub-rx",
7065 .no_pcm = 1,
7066 .dpcm_playback = 1,
7067 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
7068 .be_hw_params_fixup = msm_be_hw_params_fixup,
7069 .ignore_pmdown_time = 1,
7070 .ignore_suspend = 1,
7071 },
7072 {
7073 .name = LPASS_BE_QUIN_AUXPCM_TX,
7074 .stream_name = "Quin AUX PCM Capture",
7075 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7076 .platform_name = "msm-pcm-routing",
7077 .codec_name = "msm-stub-codec.1",
7078 .codec_dai_name = "msm-stub-tx",
7079 .no_pcm = 1,
7080 .dpcm_capture = 1,
7081 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
7082 .be_hw_params_fixup = msm_be_hw_params_fixup,
7083 .ignore_suspend = 1,
7084 },
7085};
7086
7087static struct snd_soc_dai_link msm_auto_dai_links[
7088 ARRAY_SIZE(msm_common_dai_links) +
7089 ARRAY_SIZE(msm_auto_fe_dai_links) +
7090 ARRAY_SIZE(msm_common_be_dai_links) +
7091 ARRAY_SIZE(msm_auto_be_dai_links) +
7092 ARRAY_SIZE(ext_disp_be_dai_link) +
7093 ARRAY_SIZE(msm_mi2s_be_dai_links) +
7094 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
7095
7096static struct snd_soc_dai_link msm_auto_custom_dai_links[
7097 ARRAY_SIZE(msm_custom_fe_dai_links) +
7098 ARRAY_SIZE(msm_auto_fe_dai_links) +
7099 ARRAY_SIZE(msm_common_be_dai_links) +
7100 ARRAY_SIZE(msm_auto_be_dai_links) +
7101 ARRAY_SIZE(ext_disp_be_dai_link) +
7102 ARRAY_SIZE(msm_mi2s_be_dai_links) +
7103 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
7104
7105struct snd_soc_card snd_soc_card_auto_msm = {
7106 .name = "sa6155-adp-star-snd-card",
7107};
7108
7109struct snd_soc_card snd_soc_card_auto_custom_msm = {
7110 .name = "sa6155-custom-snd-card",
7111};
7112
7113static int msm_populate_dai_link_component_of_node(
7114 struct snd_soc_card *card)
7115{
7116 int i, index, ret = 0;
7117 struct device *cdev = card->dev;
7118 struct snd_soc_dai_link *dai_link = card->dai_link;
7119 struct device_node *np;
7120
7121 if (!cdev) {
7122 pr_err("%s: Sound card device memory NULL\n", __func__);
7123 return -ENODEV;
7124 }
7125
7126 for (i = 0; i < card->num_links; i++) {
7127 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
7128 continue;
7129
7130 /* populate platform_of_node for snd card dai links */
7131 if (dai_link[i].platform_name &&
7132 !dai_link[i].platform_of_node) {
7133 index = of_property_match_string(cdev->of_node,
7134 "asoc-platform-names",
7135 dai_link[i].platform_name);
7136 if (index < 0) {
7137 pr_err("%s: No match found for platform name: %s\n",
7138 __func__, dai_link[i].platform_name);
7139 ret = index;
7140 goto err;
7141 }
7142 np = of_parse_phandle(cdev->of_node, "asoc-platform",
7143 index);
7144 if (!np) {
7145 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
7146 __func__, dai_link[i].platform_name,
7147 index);
7148 ret = -ENODEV;
7149 goto err;
7150 }
7151 dai_link[i].platform_of_node = np;
7152 dai_link[i].platform_name = NULL;
7153 }
7154
7155 /* populate cpu_of_node for snd card dai links */
7156 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
7157 index = of_property_match_string(cdev->of_node,
7158 "asoc-cpu-names",
7159 dai_link[i].cpu_dai_name);
7160 if (index >= 0) {
7161 np = of_parse_phandle(cdev->of_node, "asoc-cpu",
7162 index);
7163 if (!np) {
7164 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
7165 __func__,
7166 dai_link[i].cpu_dai_name);
7167 ret = -ENODEV;
7168 goto err;
7169 }
7170 dai_link[i].cpu_of_node = np;
7171 dai_link[i].cpu_dai_name = NULL;
7172 }
7173 }
7174
7175 /* populate codec_of_node for snd card dai links */
7176 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
7177 index = of_property_match_string(cdev->of_node,
7178 "asoc-codec-names",
7179 dai_link[i].codec_name);
7180 if (index < 0)
7181 continue;
7182 np = of_parse_phandle(cdev->of_node, "asoc-codec",
7183 index);
7184 if (!np) {
7185 pr_err("%s: retrieving phandle for codec %s failed\n",
7186 __func__, dai_link[i].codec_name);
7187 ret = -ENODEV;
7188 goto err;
7189 }
7190 dai_link[i].codec_of_node = np;
7191 dai_link[i].codec_name = NULL;
7192 }
7193 }
7194
7195err:
7196 return ret;
7197}
7198
7199static const struct of_device_id sa6155_asoc_machine_of_match[] = {
7200 { .compatible = "qcom,sa6155-asoc-snd-adp-star",
7201 .data = "adp_star_codec"},
7202 { .compatible = "qcom,sa6155-asoc-snd-custom",
7203 .data = "custom_codec"},
7204 {},
7205};
7206
7207static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
7208{
7209 struct snd_soc_card *card = NULL;
7210 struct snd_soc_dai_link *dailink;
7211 int len_1, len_2, len_3;
7212 int total_links;
7213 const struct of_device_id *match;
7214
7215 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
7216 if (!match) {
7217 dev_err(dev, "%s: No DT match found for sound card\n",
7218 __func__);
7219 return NULL;
7220 }
7221
7222 if (!strcmp(match->data, "adp_star_codec")) {
7223 card = &snd_soc_card_auto_msm;
7224 len_1 = ARRAY_SIZE(msm_common_dai_links);
7225 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
7226 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
7227 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
7228 memcpy(msm_auto_dai_links,
7229 msm_common_dai_links,
7230 sizeof(msm_common_dai_links));
7231 memcpy(msm_auto_dai_links + len_1,
7232 msm_auto_fe_dai_links,
7233 sizeof(msm_auto_fe_dai_links));
7234 memcpy(msm_auto_dai_links + len_2,
7235 msm_common_be_dai_links,
7236 sizeof(msm_common_be_dai_links));
7237 memcpy(msm_auto_dai_links + len_3,
7238 msm_auto_be_dai_links,
7239 sizeof(msm_auto_be_dai_links));
7240
7241 if (of_property_read_bool(dev->of_node,
7242 "qcom,ext-disp-audio-rx")) {
7243 dev_dbg(dev, "%s(): ext disp audio support present\n",
7244 __func__);
7245 memcpy(msm_auto_dai_links + total_links,
7246 ext_disp_be_dai_link,
7247 sizeof(ext_disp_be_dai_link));
7248 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
7249 }
7250 if (of_property_read_bool(dev->of_node,
7251 "qcom,mi2s-audio-intf")) {
7252 memcpy(msm_auto_dai_links + total_links,
7253 msm_mi2s_be_dai_links,
7254 sizeof(msm_mi2s_be_dai_links));
7255 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
7256 }
7257 if (of_property_read_bool(dev->of_node,
7258 "qcom,auxpcm-audio-intf")) {
7259 memcpy(msm_auto_dai_links + total_links,
7260 msm_auxpcm_be_dai_links,
7261 sizeof(msm_auxpcm_be_dai_links));
7262 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
7263 }
7264
7265 dailink = msm_auto_dai_links;
7266 } else if (!strcmp(match->data, "custom_codec")) {
7267 card = &snd_soc_card_auto_custom_msm;
7268 len_1 = ARRAY_SIZE(msm_custom_fe_dai_links);
7269 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
7270 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
7271 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
7272 memcpy(msm_auto_custom_dai_links,
7273 msm_custom_fe_dai_links,
7274 sizeof(msm_custom_fe_dai_links));
7275 memcpy(msm_auto_custom_dai_links + len_1,
7276 msm_auto_fe_dai_links,
7277 sizeof(msm_auto_fe_dai_links));
7278 memcpy(msm_auto_custom_dai_links + len_2,
7279 msm_common_be_dai_links,
7280 sizeof(msm_common_be_dai_links));
7281 memcpy(msm_auto_custom_dai_links + len_3,
7282 msm_auto_be_dai_links,
7283 sizeof(msm_auto_be_dai_links));
7284
7285 if (of_property_read_bool(dev->of_node,
7286 "qcom,ext-disp-audio-rx")) {
7287 dev_dbg(dev, "%s(): ext disp audio support present\n",
7288 __func__);
7289 memcpy(msm_auto_custom_dai_links + total_links,
7290 ext_disp_be_dai_link,
7291 sizeof(ext_disp_be_dai_link));
7292 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
7293 }
7294 if (of_property_read_bool(dev->of_node,
7295 "qcom,mi2s-audio-intf")) {
7296 memcpy(msm_auto_custom_dai_links + total_links,
7297 msm_mi2s_be_dai_links,
7298 sizeof(msm_mi2s_be_dai_links));
7299 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
7300 }
7301 if (of_property_read_bool(dev->of_node,
7302 "qcom,auxpcm-audio-intf")) {
7303 memcpy(msm_auto_custom_dai_links + total_links,
7304 msm_auxpcm_be_dai_links,
7305 sizeof(msm_auxpcm_be_dai_links));
7306 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
7307 }
7308 dailink = msm_auto_custom_dai_links;
7309 } else {
7310 dev_err(dev, "%s: Codec not supported\n",
7311 __func__);
7312 return NULL;
7313 }
7314
7315 if (card) {
7316 card->dai_link = dailink;
7317 card->num_links = total_links;
7318 }
7319
7320 return card;
7321}
7322
7323/*****************************************************************************
7324* TO BE UPDATED: Codec/Platform specific tdm slot and offset table selection
7325*****************************************************************************/
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7326static int msm_tdm_init(struct platform_device *pdev)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7327{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7328 struct snd_soc_card *card = platform_get_drvdata(pdev);
7329 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7330 const struct of_device_id *match;
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7331 int count;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7332
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7333 match = of_match_node(sa6155_asoc_machine_of_match, pdev->dev.of_node);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7334 if (!match) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7335 dev_err(&pdev->dev, "%s: No DT match found for sound card\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7336 __func__);
7337 return -EINVAL;
7338 }
7339
7340 if (!strcmp(match->data, "custom_codec")) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7341 dev_dbg(&pdev->dev, "%s: custom tdm configuration\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7342
7343 memcpy(tdm_rx_slot_offset,
7344 tdm_rx_slot_offset_custom,
7345 sizeof(tdm_rx_slot_offset_custom));
7346 memcpy(tdm_tx_slot_offset,
7347 tdm_tx_slot_offset_custom,
7348 sizeof(tdm_tx_slot_offset_custom));
7349 memcpy(tdm_slot,
7350 tdm_slot_custom,
7351 sizeof(tdm_slot_custom));
7352 } else {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7353 dev_dbg(&pdev->dev, "%s: default tdm configuration\n", __func__);
7354 }
7355
7356 for (count = 0; count < TDM_INTERFACE_MAX; count++) {
7357 mutex_init(&pdata->tdm_intf_conf[count].lock);
7358 pdata->tdm_intf_conf[count].ref_cnt = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7359 }
7360
7361 return 0;
7362}
7363
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7364static void msm_tdm_deinit(struct platform_device *pdev)
7365{
7366 struct snd_soc_card *card = platform_get_drvdata(pdev);
7367 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
7368 int count;
7369
7370 for (count = 0; count < TDM_INTERFACE_MAX; count++) {
7371 mutex_destroy(&pdata->tdm_intf_conf[count].lock);
7372 pdata->tdm_intf_conf[count].ref_cnt = 0;
7373 }
7374}
7375
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7376static void msm_i2s_auxpcm_init(struct platform_device *pdev)
7377{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7378 struct snd_soc_card *card = platform_get_drvdata(pdev);
7379 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7380 int count;
7381 u32 mi2s_master_slave[MI2S_MAX];
7382 int ret;
7383
7384 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7385 mutex_init(&pdata->mi2s_intf_conf[count].lock);
7386 pdata->mi2s_intf_conf[count].ref_cnt = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7387 }
7388
7389 ret = of_property_read_u32_array(pdev->dev.of_node,
7390 "qcom,msm-mi2s-master",
7391 mi2s_master_slave, MI2S_MAX);
7392 if (ret) {
7393 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
7394 __func__);
7395 } else {
7396 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7397 pdata->mi2s_intf_conf[count].msm_is_mi2s_master =
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7398 mi2s_master_slave[count];
7399 }
7400 }
7401}
7402
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7403static void msm_i2s_auxpcm_deinit(struct platform_device *pdev)
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7404{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7405 struct snd_soc_card *card = platform_get_drvdata(pdev);
7406 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7407 int count;
7408
7409 for (count = 0; count < MI2S_MAX; count++) {
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7410 mutex_destroy(&pdata->mi2s_intf_conf[count].lock);
7411 pdata->mi2s_intf_conf[count].ref_cnt = 0;
7412 pdata->mi2s_intf_conf[count].msm_is_mi2s_master = 0;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7413 }
7414}
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]7415
7416static int sa6155_ssr_enable(struct device *dev, void *data)
7417{
7418 struct platform_device *pdev = to_platform_device(dev);
7419 struct snd_soc_card *card = platform_get_drvdata(pdev);
7420 int ret = 0;
7421
7422 if (!card) {
7423 dev_err(dev, "%s: card is NULL\n", __func__);
7424 ret = -EINVAL;
7425 goto err;
7426 }
7427
7428 dev_info(dev, "%s: setting snd_card to ONLINE\n", __func__);
7429 snd_soc_card_change_online_state(card, 1);
7430
7431err:
7432 return ret;
7433}
7434
7435static void sa6155_ssr_disable(struct device *dev, void *data)
7436{
7437 struct platform_device *pdev = to_platform_device(dev);
7438 struct snd_soc_card *card = platform_get_drvdata(pdev);
7439
7440 if (!card) {
7441 dev_err(dev, "%s: card is NULL\n", __func__);
7442 return;
7443 }
7444
7445 dev_info(dev, "%s: setting snd_card to OFFLINE\n", __func__);
7446 snd_soc_card_change_online_state(card, 0);
7447}
7448
7449static const struct snd_event_ops sa6155_ssr_ops = {
7450 .enable = sa6155_ssr_enable,
7451 .disable = sa6155_ssr_disable,
7452};
7453
7454static int msm_audio_ssr_compare(struct device *dev, void *data)
7455{
7456 struct device_node *node = data;
7457
7458 dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
7459 __func__, dev->of_node, node);
7460 return (dev->of_node && dev->of_node == node);
7461}
7462
7463static int msm_audio_ssr_register(struct device *dev)
7464{
7465 struct device_node *np = dev->of_node;
7466 struct snd_event_clients *ssr_clients = NULL;
7467 struct device_node *node;
7468 int ret;
7469 int i;
7470
7471 for (i = 0; ; i++) {
7472 node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
7473 if (!node)
7474 break;
7475 snd_event_mstr_add_client(&ssr_clients,
7476 msm_audio_ssr_compare, node);
7477 }
7478
7479 ret = snd_event_master_register(dev, &sa6155_ssr_ops,
7480 ssr_clients, NULL);
7481 if (!ret)
7482 snd_event_notify(dev, SND_EVENT_UP);
7483
7484 return ret;
7485}
7486
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7487static int msm_asoc_machine_probe(struct platform_device *pdev)
7488{
7489 struct snd_soc_card *card;
7490 struct msm_asoc_mach_data *pdata;
7491 int ret;
7492 enum apr_subsys_state q6_state;
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7493 static int first_probe = 1;
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7494
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7495 if (first_probe) {
7496 place_marker("M - DRIVER Audio Init");
7497 first_probe = 0;
7498 }
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7499 if (!pdev->dev.of_node) {
7500 dev_err(&pdev->dev, "No platform supplied from device tree\n");
7501 return -EINVAL;
7502 }
7503
7504 q6_state = apr_get_q6_state();
7505 if (q6_state == APR_SUBSYS_DOWN) {
7506 dev_dbg(&pdev->dev, "deferring %s, adsp_state %d\n",
7507 __func__, q6_state);
7508 return -EPROBE_DEFER;
7509 }
7510
7511 pdata = devm_kzalloc(&pdev->dev,
7512 sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
7513 if (!pdata)
7514 return -ENOMEM;
7515
7516 card = populate_snd_card_dailinks(&pdev->dev);
7517 if (!card) {
7518 dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
7519 ret = -EINVAL;
7520 goto err;
7521 }
7522 card->dev = &pdev->dev;
7523 platform_set_drvdata(pdev, card);
7524 snd_soc_card_set_drvdata(card, pdata);
7525
7526 ret = snd_soc_of_parse_card_name(card, "qcom,model");
7527 if (ret) {
7528 dev_err(&pdev->dev, "parse card name failed, err:%d\n",
7529 ret);
7530 goto err;
7531 }
7532
7533 ret = msm_populate_dai_link_component_of_node(card);
7534 if (ret) {
7535 ret = -EPROBE_DEFER;
7536 goto err;
7537 }
7538
7539 /* Populate controls of snd card */
7540 card->controls = msm_snd_controls;
7541 card->num_controls = ARRAY_SIZE(msm_snd_controls);
7542
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7543 ret = msm_tdm_init(pdev);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7544 if (ret) {
7545 ret = -EPROBE_DEFER;
7546 goto err;
7547 }
7548
7549 ret = devm_snd_soc_register_card(&pdev->dev, card);
7550 if (ret == -EPROBE_DEFER) {
7551 goto err;
7552 } else if (ret) {
7553 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
7554 ret);
7555 goto err;
7556 }
7557 dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
7558
7559 /* Parse pinctrl info from devicetree */
7560 ret = msm_get_pinctrl(pdev);
7561 if (!ret) {
7562 pr_debug("%s: pinctrl parsing successful\n", __func__);
7563 } else {
7564 dev_dbg(&pdev->dev,
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7565 "%s: pinctrl parsing failed with %d\n",
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7566 __func__, ret);
7567 ret = 0;
7568 }
7569
7570 msm_i2s_auxpcm_init(pdev);
7571
Erin Yan300664f2019-05-14 10:42:31 +0800[diff] [blame]7572 ret = msm_audio_ssr_register(&pdev->dev);
7573 if (ret)
7574 pr_err("%s: Registration with SND event FWK failed ret = %d\n",
7575 __func__, ret);
7576
Derek Chen628c9952019-05-03 17:14:09 +0530[diff] [blame]7577 place_marker("M - DRIVER Audio Ready");
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7578 return 0;
7579err:
7580 msm_release_pinctrl(pdev);
7581 devm_kfree(&pdev->dev, pdata);
7582 return ret;
7583}
7584
7585static int msm_asoc_machine_remove(struct platform_device *pdev)
7586{
Derek Chen7bb78312019-06-18 00:36:55 -0700[diff] [blame]7587 msm_i2s_auxpcm_deinit(pdev);
7588 msm_tdm_deinit(pdev);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7589
7590 msm_release_pinctrl(pdev);
7591 return 0;
7592}
7593
7594static struct platform_driver sa6155_asoc_machine_driver = {
7595 .driver = {
7596 .name = DRV_NAME,
7597 .owner = THIS_MODULE,
7598 .pm = &snd_soc_pm_ops,
7599 .of_match_table = sa6155_asoc_machine_of_match,
7600 },
7601 .probe = msm_asoc_machine_probe,
7602 .remove = msm_asoc_machine_remove,
7603};
7604
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7605int __init sa6155_init(void)
7606{
7607 pr_debug("%s\n", __func__);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7608 return platform_driver_register(&sa6155_asoc_machine_driver);
7609}
7610
7611void sa6155_exit(void)
7612{
7613 pr_debug("%s\n", __func__);
7614 platform_driver_unregister(&sa6155_asoc_machine_driver);
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7615}
7616
Rahul Sharmaf53de7f2019-03-03 22:30:47 +0530[diff] [blame]7617module_init(sa6155_init);
7618module_exit(sa6155_exit);
7619
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7620MODULE_DESCRIPTION("ALSA SoC msm");
7621MODULE_LICENSE("GPL v2");
7622MODULE_ALIAS("platform:" DRV_NAME);
7623MODULE_DEVICE_TABLE(of, sa6155_asoc_machine_of_match);