Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 1 | /* |
Kiet Lam | 842dad0 | 2014-02-18 18:44:02 -0800 | [diff] [blame] | 2 | * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
Gopichand Nakkala | 92f07d8 | 2013-01-08 21:16:34 -0800 | [diff] [blame] | 20 | */ |
Kiet Lam | 842dad0 | 2014-02-18 18:44:02 -0800 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 28 | #ifndef WLAN_QCT_DXE_I_H |
| 29 | #define WLAN_QCT_DXE_I_H |
| 30 | |
| 31 | /**========================================================================= |
| 32 | |
| 33 | @file wlan_qct_dxe_i.h |
| 34 | |
| 35 | @brief |
| 36 | |
| 37 | This file contains the external API exposed by the wlan data transfer abstraction layer module. |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 38 | ========================================================================*/ |
| 39 | |
| 40 | /*=========================================================================== |
| 41 | |
| 42 | EDIT HISTORY FOR FILE |
| 43 | |
| 44 | |
| 45 | This section contains comments describing changes made to the module. |
| 46 | Notice that changes are listed in reverse chronological order. |
| 47 | |
| 48 | |
| 49 | $Header:$ $DateTime: $ $Author: $ |
| 50 | |
| 51 | |
| 52 | when who what, where, why |
| 53 | -------- --- ---------------------------------------------------------- |
| 54 | 08/03/10 schang Created module. |
| 55 | |
| 56 | ===========================================================================*/ |
| 57 | |
| 58 | /*=========================================================================== |
| 59 | |
| 60 | INCLUDE FILES FOR MODULE |
| 61 | |
| 62 | ===========================================================================*/ |
| 63 | |
| 64 | /*---------------------------------------------------------------------------- |
| 65 | * Include Files |
| 66 | * -------------------------------------------------------------------------*/ |
| 67 | #include "wlan_qct_dxe.h" |
| 68 | #include "wlan_qct_pal_trace.h" |
Madan Mohan Koyyalamudi | ea77701 | 2012-10-31 14:22:34 -0700 | [diff] [blame] | 69 | #include "wlan_qct_pal_timer.h" |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 70 | #include "vos_trace.h" |
| 71 | /*---------------------------------------------------------------------------- |
| 72 | * Preprocessor Definitions and Constants |
| 73 | * -------------------------------------------------------------------------*/ |
| 74 | #define WLANDXE_CTXT_COOKIE 0xC00CC111 |
| 75 | |
| 76 | |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 77 | /* From here WCNSS DXE register information |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 78 | * This is temporary definition location to make compile and unit test |
| 79 | * If official msmreg.h integrated, this part will be eliminated */ |
| 80 | /* Start with base address */ |
Madan Mohan Koyyalamudi | 8cb5398 | 2012-09-28 14:34:47 -0700 | [diff] [blame] | 81 | |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 82 | #ifdef WCN_PRONTO |
Hardik Kantilal Patel | 7d14392 | 2014-03-06 10:07:52 +0530 | [diff] [blame^] | 83 | #define WLANDXE_CCU_DXE_INT_SELECT 0x2050dc |
| 84 | #define WLANDXE_CCU_DXE_INT_SELECT_STAT 0x2050e0 |
| 85 | #define WLANDXE_CCU_ASIC_INT_ENABLE 0x2050e4 |
| 86 | #define WLANDXE_CCU_SOFT_RESET 0x204010 |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 87 | #else |
Hardik Kantilal Patel | 7d14392 | 2014-03-06 10:07:52 +0530 | [diff] [blame^] | 88 | #define WLANDXE_CCU_DXE_INT_SELECT 0x200b10 |
| 89 | #define WLANDXE_CCU_DXE_INT_SELECT_STAT 0x200b14 |
| 90 | #define WLANDXE_CCU_ASIC_INT_ENABLE 0x200b18 |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 91 | #endif |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 92 | |
Hardik Kantilal Patel | 7d14392 | 2014-03-06 10:07:52 +0530 | [diff] [blame^] | 93 | #define WLANDXE_BMU_AVAILABLE_BD_PDU 0x80084 |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 94 | |
Hardik Kantilal Patel | 7d14392 | 2014-03-06 10:07:52 +0530 | [diff] [blame^] | 95 | #define WLANDXE_REGISTER_BASE_ADDRESS 0x202000 |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 96 | |
| 97 | /* Common over the channels register addresses */ |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 98 | #define WALNDEX_DMA_CSR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x00) |
| 99 | #define WALNDEX_DMA_ENCH_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x04) |
| 100 | #define WALNDEX_DMA_CH_EN_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x08) |
| 101 | #define WALNDEX_DMA_CH_DONE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x0C) |
| 102 | #define WALNDEX_DMA_CH_ERR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x10) |
| 103 | #define WALNDEX_DMA_CH_STOP_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x14) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 104 | |
| 105 | /* Interrupt Control register address */ |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 106 | #define WLANDXE_INT_MASK_REG_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x18) |
| 107 | #define WLANDXE_INT_SRC_MSKD_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x1C) |
| 108 | #define WLANDXE_INT_SRC_RAW_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x20) |
| 109 | #define WLANDXE_INT_ED_SRC_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x24) |
| 110 | #define WLANDXE_INT_DONE_SRC_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x28) |
| 111 | #define WLANDXE_INT_ERR_SRC_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x2C) |
| 112 | #define WLANDXE_INT_CLR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x30) |
| 113 | #define WLANDXE_INT_ED_CLR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x34) |
| 114 | #define WLANDXE_INT_DONE_CLR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x38) |
| 115 | #define WLANDXE_INT_ERR_CLR_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x3C) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 116 | |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 117 | #define WLANDXE_DMA_CH_PRES_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x40) |
| 118 | #define WLANDXE_ARB_CH_MSK_CLR_ADDRRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x74) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 119 | |
| 120 | /* Channel Counter register */ |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 121 | #define WLANDXE_DMA_COUNTER_0 (WLANDXE_REGISTER_BASE_ADDRESS + 0x200) |
| 122 | #define WLANDXE_DMA_COUNTER_1 (WLANDXE_REGISTER_BASE_ADDRESS + 0x204) |
| 123 | #define WLANDXE_DMA_COUNTER_2 (WLANDXE_REGISTER_BASE_ADDRESS + 0x208) |
| 124 | #define WLANDXE_DMA_COUNTER_3 (WLANDXE_REGISTER_BASE_ADDRESS + 0x20C) |
| 125 | #define WLANDXE_DMA_COUNTER_4 (WLANDXE_REGISTER_BASE_ADDRESS + 0x210) |
| 126 | #define WLANDXE_DMA_COUNTER_5 (WLANDXE_REGISTER_BASE_ADDRESS + 0x214) |
| 127 | #define WLANDXE_DMA_COUNTER_6 (WLANDXE_REGISTER_BASE_ADDRESS + 0x218) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 128 | |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 129 | #define WLANDXE_ENGINE_STAT_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x64) |
| 130 | #define WLANDXE_BMU_SB_QDAT_AV_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x5c) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 131 | |
| 132 | /* Channel Base address */ |
Madan Mohan Koyyalamudi | a53c4dc | 2012-11-13 10:35:42 -0800 | [diff] [blame] | 133 | #define WLANDXE_DMA_CHAN0_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x400) |
| 134 | #define WLANDXE_DMA_CHAN1_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x440) |
| 135 | #define WLANDXE_DMA_CHAN2_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x480) |
| 136 | #define WLANDXE_DMA_CHAN3_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x4C0) |
| 137 | #define WLANDXE_DMA_CHAN4_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x500) |
| 138 | #define WLANDXE_DMA_CHAN5_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x540) |
| 139 | #define WLANDXE_DMA_CHAN6_BASE_ADDRESS (WLANDXE_REGISTER_BASE_ADDRESS + 0x580) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 140 | |
| 141 | /* Channel specific register offset */ |
| 142 | #define WLANDXE_DMA_CH_CTRL_REG 0x0000 |
| 143 | #define WLANDXE_DMA_CH_STATUS_REG 0x0004 |
| 144 | #define WLANDXE_DMA_CH_SZ_REG 0x0008 |
| 145 | #define WLANDXE_DMA_CH_SADRL_REG 0x000C |
| 146 | #define WLANDXE_DMA_CH_SADRH_REG 0x0010 |
| 147 | #define WLANDXE_DMA_CH_DADRL_REG 0x0014 |
| 148 | #define WLANDXE_DMA_CH_DADRH_REG 0x0018 |
| 149 | #define WLANDXE_DMA_CH_DESCL_REG 0x001C |
| 150 | #define WLANDXE_DMA_CH_DESCH_REG 0x0020 |
| 151 | #define WLANDXE_DMA_CH_LST_DESCL_REG 0x0024 |
| 152 | #define WLANDXE_DMA_CH_LST_DESCH_REG 0x0028 |
| 153 | #define WLANDXE_DMA_CH_BD_REG 0x002C |
| 154 | #define WLANDXE_DMA_CH_HEAD_REG 0x0030 |
| 155 | #define WLANDXE_DMA_CH_TAIL_REG 0x0034 |
| 156 | #define WLANDXE_DMA_CH_PDU_REG 0x0038 |
| 157 | #define WLANDXE_DMA_CH_TSTMP_REG 0x003C |
| 158 | |
| 159 | /* Common CSR Register Contorol mask and offset */ |
Leo Chang | 00708f6 | 2013-12-03 20:21:51 -0800 | [diff] [blame] | 160 | #ifdef WCN_PRONTO |
| 161 | #define WLANDXE_DMA_CSR_RESERVED_MASK 0xFFFF0000 |
| 162 | #define WLANDXE_DMA_CSR_RESERVED_OFFSET 0x10 |
| 163 | #define WLANDXE_DMA_CSR_RESERVED_DEFAULT 0x0 |
| 164 | |
| 165 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_MASK 0x8000 |
| 166 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_OFFSET 0x0F |
| 167 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_DEFAULT 0x0 |
| 168 | |
| 169 | #define WLANDXE_DMA_CSR_PAUSED_MASK 0x4000 |
| 170 | #define WLANDXE_DMA_CSR_PAUSED_OFFSET 0x0E |
| 171 | #define WLANDXE_DMA_CSR_PAUSED_DEFAULT 0x0 |
| 172 | |
| 173 | #define WLANDXE_DMA_CSR_ECTR_EN_MASK 0x2000 |
| 174 | #define WLANDXE_DMA_CSR_ECTR_EN_OFFSET 0x0D |
| 175 | #define WLANDXE_DMA_CSR_ECTR_EN_DEFAULT 0x2000 |
| 176 | |
| 177 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_MASK 0x1F00 |
| 178 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_OFFSET 0x08 |
| 179 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_DEFAULT 0x0F00 |
| 180 | |
| 181 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_MASK 0xF8 |
| 182 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_OFFSET 0x03 |
| 183 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_DEFAULT 0x28 |
| 184 | |
| 185 | #define WLANDXE_DMA_CSR_TSTMP_EN_MASK 0x04 |
| 186 | #define WLANDXE_DMA_CSR_TSTMP_EN_OFFSET 0x02 |
| 187 | #define WLANDXE_DMA_CSR_TSTMP_EN_DEFAULT 0x0 |
| 188 | |
| 189 | #define WLANDXE_DMA_CCU_DXE_RESET_MASK 0x4 |
| 190 | #else |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 191 | #define WLANDXE_DMA_CSR_RESERVED_MASK 0xFFFE0000 |
| 192 | #define WLANDXE_DMA_CSR_RESERVED_OFFSET 0x11 |
| 193 | #define WLANDXE_DMA_CSR_RESERVED_DEFAULT 0x0 |
| 194 | |
| 195 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_MASK 0x10000 |
| 196 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_OFFSET 0x10 |
| 197 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_DEFAULT 0x0 |
| 198 | |
| 199 | #define WLANDXE_DMA_CSR_PAUSED_MASK 0x8000 |
| 200 | #define WLANDXE_DMA_CSR_PAUSED_OFFSET 0xF |
| 201 | #define WLANDXE_DMA_CSR_PAUSED_DEFAULT 0x0 |
| 202 | |
| 203 | #define WLANDXE_DMA_CSR_ECTR_EN_MASK 0x4000 |
| 204 | #define WLANDXE_DMA_CSR_ECTR_EN_OFFSET 0xE |
| 205 | #define WLANDXE_DMA_CSR_ECTR_EN_DEFAULT 0x4000 |
| 206 | |
| 207 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_MASK 0x3E00 |
| 208 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_OFFSET 0x9 |
| 209 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_DEFAULT 0xE00 |
| 210 | |
| 211 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_MASK 0x1F0 |
| 212 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_OFFSET 0x4 |
| 213 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_DEFAULT 0x50 |
| 214 | |
| 215 | #define WLANDXE_DMA_CSR_TSTMP_EN_MASK 0x8 |
| 216 | #define WLANDXE_DMA_CSR_TSTMP_EN_OFFSET 0x3 |
| 217 | #define WLANDXE_DMA_CSR_TSTMP_EN_DEFAULT 0x0 |
| 218 | |
| 219 | #define WLANDXE_DMA_CSR_RESET_MASK 0x4 |
| 220 | #define WLANDXE_DMA_CSR_RESET_OFFSET 0x2 |
| 221 | #define WLANDXE_DMA_CSR_RESET_DEFAULT 0x0 |
Leo Chang | 00708f6 | 2013-12-03 20:21:51 -0800 | [diff] [blame] | 222 | #endif /* WCN_PRONTO */ |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 223 | |
| 224 | #define WLANDXE_DMA_CSR_PAUSE_MASK 0x2 |
| 225 | #define WLANDXE_DMA_CSR_PAUSE_OFFSET 0x1 |
| 226 | #define WLANDXE_DMA_CSR_PAUSE_DEFAULT 0x0 |
| 227 | |
| 228 | #define WLANDXE_DMA_CSR_EN_MASK 0x1 |
| 229 | #define WLANDXE_DMA_CSR_EN_OFFSET 0x0 |
| 230 | #define WLANDXE_DMA_CSR_EN_DEFAULT 0x0 |
Leo Chang | 00708f6 | 2013-12-03 20:21:51 -0800 | [diff] [blame] | 231 | |
| 232 | /* DXE CSR Master enable register value */ |
| 233 | #define WLANDXE_CSR_DEFAULT_ENABLE (WLANDXE_DMA_CSR_H2H_SYNC_EN_MASK | \ |
| 234 | WLANDXE_DMA_CSR_ECTR_EN_MASK | \ |
| 235 | WLANDXE_DMA_CSR_EN_MASK) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 236 | |
| 237 | /* Channel CTRL Register Control mask and offset */ |
| 238 | #define WLANDXE_CH_CTRL_RSVD_MASK 0x80000000 |
| 239 | #define WLANDXE_CH_CTRL_RSVD_OFFSET 0x1F |
| 240 | #define WLANDXE_CH_CTRL_RSVD_DEFAULT 0x0 |
| 241 | |
| 242 | #define WLANDXE_CH_CTRL_SWAP_MASK 0x80000000 |
| 243 | |
| 244 | #define WLANDXE_CH_CTRL_BDT_IDX_MASK 0x60000000 |
| 245 | #define WLANDXE_CH_CTRL_BDT_IDX_OFFSET 0x1D |
| 246 | #define WLANDXE_CH_CTRL_BDT_IDX_DEFAULT 0x0 |
| 247 | |
| 248 | #define WLANDXE_CH_CTRL_DFMT_MASK 0x10000000 |
| 249 | #define WLANDXE_CH_CTRL_DFMT_OFFSET 0x1C |
| 250 | #define WLANDXE_CH_CTRL_DFMT_DEFAULT 0x10000000 |
| 251 | #define WLANDXE_CH_CTRL_DFMT_ESHORT 0x0 |
| 252 | #define WLANDXE_CH_CTRL_DFMT_ELONG 0x1 |
| 253 | |
| 254 | #define WLANDXE_CH_CTRL_ABORT_MASK 0x8000000 |
| 255 | #define WLANDXE_CH_CTRL_ABORT_OFFSET 0x1B |
| 256 | #define WLANDXE_CH_CTRL_ABORT_DEFAULT 0x0 |
| 257 | |
| 258 | #define WLANDXE_CH_CTRL_ENDIAN_MASK 0x4000000 |
| 259 | |
| 260 | #define WLANDXE_CH_CTRL_CTR_SEL_MASK 0x3C00000 |
| 261 | #define WLANDXE_CH_CTRL_CTR_SEL_OFFSET 0x16 |
| 262 | #define WLANDXE_CH_CTRL_CTR_SEL_DEFAULT 0x0 |
| 263 | |
| 264 | #define WLANDXE_CH_CTRL_EDVEN_MASK 0x200000 |
| 265 | #define WLANDXE_CH_CTRL_EDVEN_OFFSET 0x15 |
| 266 | #define WLANDXE_CH_CTRL_EDVEN_DEFAULT 0x0 |
| 267 | |
| 268 | #define WLANDXE_CH_CTRL_EDEN_MASK 0x100000 |
| 269 | #define WLANDXE_CH_CTRL_EDEN_OFFSET 0x14 |
| 270 | #define WLANDXE_CH_CTRL_EDEN_DEFAULT 0x0 |
| 271 | |
| 272 | #define WLANDXE_CH_CTRL_INE_DONE_MASK 0x80000 |
| 273 | #define WLANDXE_CH_CTRL_INE_DONE_OFFSET 0x13 |
| 274 | #define WLANDXE_CH_CTRL_INE_DONE_DEFAULT 0x0 |
| 275 | |
| 276 | #define WLANDXE_CH_CTRL_INE_ERR_MASK 0x40000 |
| 277 | #define WLANDXE_CH_CTRL_INE_ERR_OFFSET 0x12 |
| 278 | #define WLANDXE_CH_CTRL_INE_ERR_DEFAULT 0x0 |
| 279 | |
| 280 | #define WLANDXE_CH_CTRL_INE_ED_MASK 0x20000 |
| 281 | #define WLANDXE_CH_CTRL_INE_ED_OFFSET 0x11 |
| 282 | #define WLANDXE_CH_CTRL_INE_ED_DEFAULT 0x0 |
| 283 | |
| 284 | #define WLANDXE_CH_CTRL_STOP_MASK 0x10000 |
| 285 | #define WLANDXE_CH_CTRL_STOP_OFFSET 0x10 |
| 286 | #define WLANDXE_CH_CTRL_STOP_DEFAULT 0x0 |
| 287 | |
| 288 | #define WLANDXE_CH_CTRL_PRIO_MASK 0xE000 |
| 289 | #define WLANDXE_CH_CTRL_PRIO_OFFSET 0xD |
| 290 | #define WLANDXE_CH_CTRL_PRIO_DEFAULT 0x0 |
| 291 | |
| 292 | #define WLANDXE_CH_CTRL_BTHLD_SEL_MASK 0x1E00 |
| 293 | #define WLANDXE_CH_CTRL_BTHLD_SEL_OFFSET 0x9 |
| 294 | #define WLANDXE_CH_CTRL_BTHLD_SEL_DEFAULT 0x600 |
| 295 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD0 0x0 |
| 296 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD1 0x1 |
| 297 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD2 0x2 |
| 298 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD3 0x3 |
| 299 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD4 0x4 |
| 300 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD5 0x5 |
| 301 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD6 0x6 |
| 302 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD7 0x7 |
| 303 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD8 0x8 |
| 304 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD9 0x9 |
| 305 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD10 0xA |
| 306 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD11 0xB |
| 307 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD12 0xC |
| 308 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD13 0xD |
| 309 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD14 0xE |
| 310 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD15 0xF |
| 311 | |
| 312 | #define WLANDXE_CH_CTRL_PDU_REL_MASK 0x100 |
| 313 | #define WLANDXE_CH_CTRL_PDU_REL_OFFSET 0x8 |
| 314 | #define WLANDXE_CH_CTRL_PDU_REL_DEFAULT 0x100 |
| 315 | #define WLANDXE_CH_CTRL_PDU_REL_EKEEP 0x0 |
| 316 | #define WLANDXE_CH_CTRL_PDU_REL_ERELEASE 0x1 |
| 317 | |
| 318 | #define WLANDXE_CH_CTRL_PIQ_MASK 0x80 |
| 319 | #define WLANDXE_CH_CTRL_PIQ_OFFSET 0x7 |
| 320 | #define WLANDXE_CH_CTRL_PIQ_DEFAULT 0x0 |
| 321 | #define WLANDXE_CH_CTRL_PIQ_EFLAT 0x0 |
| 322 | #define WLANDXE_CH_CTRL_PIQ_EQUEUE 0x1 |
| 323 | |
| 324 | #define WLANDXE_CH_CTRL_DIQ_MASK 0x40 |
| 325 | #define WLANDXE_CH_CTRL_DIQ_OFFSET 0x6 |
| 326 | #define WLANDXE_CH_CTRL_DIQ_DEFAULT 0x0 |
| 327 | #define WLANDXE_CH_CTRL_DIQ_EFLAT 0x0 |
| 328 | #define WLANDXE_CH_CTRL_DIQ_EQUEUE 0x1 |
| 329 | |
| 330 | #define WLANDXE_CH_CTRL_SIQ_MASK 0x20 |
| 331 | #define WLANDXE_CH_CTRL_SIQ_OFFSET 0x5 |
| 332 | #define WLANDXE_CH_CTRL_SIQ_DEFAULT 0x0 |
| 333 | #define WLANDXE_CH_CTRL_SIQ_EFLAT 0x0 |
| 334 | #define WLANDXE_CH_CTRL_SIQ_EQUEUE 0x1 |
| 335 | |
| 336 | #define WLANDXE_CH_CTRL_BDH_MASK 0x10 |
| 337 | #define WLANDXE_CH_CTRL_BDH_OFFSET 0x4 |
| 338 | #define WLANDXE_CH_CTRL_BDH_DEFAULT 0x0 |
| 339 | |
| 340 | #define WLANDXE_CH_CTRL_EOP_MASK 0x8 |
| 341 | #define WLANDXE_CH_CTRL_EOP_OFFSET 0x3 |
| 342 | #define WLANDXE_CH_CTRL_EOP_DEFAULT 0x8 |
| 343 | |
| 344 | #define WLANDXE_CH_CTRL_XTYPE_MASK 0x6 |
| 345 | #define WLANDXE_CH_CTRL_XTYPE_OFFSET 0x1 |
| 346 | #define WLANDXE_CH_CTRL_XTYPE_DEFAULT 0x0 |
| 347 | #define WLANDXE_CH_CTRL_XTYPE_EH2H 0x0 |
| 348 | #define WLANDXE_CH_CTRL_XTYPE_EB2B 0x1 |
| 349 | #define WLANDXE_CH_CTRL_XTYPE_EH2B 0x2 |
| 350 | #define WLANDXE_CH_CTRL_XTYPE_EB2H 0x3 |
| 351 | |
| 352 | #define WLANDXE_CH_CTRL_DONE_MASK 0x4 |
| 353 | |
| 354 | #define WLANDXE_CH_CTRL_ERR_MASK 0x20 |
| 355 | |
| 356 | #define WLANDXE_CH_CTRL_MASKED_MASK 0x8 |
| 357 | |
| 358 | #define WLANDXE_CH_CTRL_EN_MASK 0x1 |
| 359 | #define WLANDXE_CH_CTRL_EN_OFFSET 0x0 |
| 360 | #define WLANDXE_CH_CTRL_EN_DEFAULT 0x0 |
| 361 | #define WLANDXE_CH_CTRL_DEFAULT 0x10000708 |
| 362 | |
| 363 | |
| 364 | #define WLANDXE_DESC_CTRL_VALID 0x00000001 |
| 365 | #define WLANDXE_DESC_CTRL_XTYPE_MASK 0x00000006 |
| 366 | #define WLANDXE_DESC_CTRL_XTYPE_H2H 0x00000000 |
| 367 | #define WLANDXE_DESC_CTRL_XTYPE_B2B 0x00000002 |
| 368 | #define WLANDXE_DESC_CTRL_XTYPE_H2B 0x00000004 |
| 369 | #define WLANDXE_DESC_CTRL_XTYPE_B2H 0x00000006 |
| 370 | #define WLANDXE_DESC_CTRL_EOP 0x00000008 |
| 371 | #define WLANDXE_DESC_CTRL_BDH 0x00000010 |
| 372 | #define WLANDXE_DESC_CTRL_SIQ 0x00000020 |
| 373 | #define WLANDXE_DESC_CTRL_DIQ 0x00000040 |
| 374 | #define WLANDXE_DESC_CTRL_PIQ 0x00000080 |
| 375 | #define WLANDXE_DESC_CTRL_PDU_REL 0x00000100 |
| 376 | #define WLANDXE_DESC_CTRL_BTHLD_SEL 0x00001E00 |
| 377 | #define WLANDXE_DESC_CTRL_PRIO 0x0000E000 |
| 378 | #define WLANDXE_DESC_CTRL_STOP 0x00010000 |
| 379 | #define WLANDXE_DESC_CTRL_INT 0x00020000 |
| 380 | #define WLANDXE_DESC_CTRL_BDT_SWAP 0x00100000 |
| 381 | #define WLANDXE_DESC_CTRL_ENDIANNESS 0x00200000 |
| 382 | #define WLANDXE_DESC_CTRL_DFMT 0x10000000 |
| 383 | #define WLANDXE_DESC_CTRL_RSVD 0xfffc0000 |
| 384 | /* CSR Register Control mask and offset */ |
| 385 | |
| 386 | #define WLANDXE_CH_STAT_INT_DONE_MASK 0x00008000 |
| 387 | #define WLANDXE_CH_STAT_INT_ERR_MASK 0x00004000 |
| 388 | #define WLANDXE_CH_STAT_INT_ED_MASK 0x00002000 |
| 389 | |
| 390 | #define WLANDXE_CH_STAT_MASKED_MASK 0x00000008 |
Leo Chang | 094ece8 | 2013-04-23 17:57:41 -0700 | [diff] [blame] | 391 | #define WLANDXE_CH_STAT_ENABLED_MASK 0x00000001 |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 392 | /* Till here WCNSS DXE register information |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 393 | * This is temporary definition location to make compile and unit test |
| 394 | * If official msmreg.h integrated, this part will be eliminated */ |
| 395 | |
| 396 | /* Interrupt control channel mask */ |
| 397 | #define WLANDXE_INT_MASK_CHAN_0 0x00000001 |
| 398 | #define WLANDXE_INT_MASK_CHAN_1 0x00000002 |
| 399 | #define WLANDXE_INT_MASK_CHAN_2 0x00000004 |
| 400 | #define WLANDXE_INT_MASK_CHAN_3 0x00000008 |
| 401 | #define WLANDXE_INT_MASK_CHAN_4 0x00000010 |
| 402 | #define WLANDXE_INT_MASK_CHAN_5 0x00000020 |
| 403 | #define WLANDXE_INT_MASK_CHAN_6 0x00000040 |
| 404 | |
| 405 | #define WLANDXE_TX_LOW_RES_THRESHOLD (5) |
| 406 | |
| 407 | /* DXE Descriptor Endian swap macro */ |
| 408 | #ifdef WLANDXE_ENDIAN_SWAP_ENABLE |
| 409 | #define WLANDXE_U32_SWAP_ENDIAN(a) (((a & 0x000000FF) << 24) | \ |
| 410 | ((a & 0x0000FF00) << 8) | \ |
| 411 | ((a & 0x00FF0000) >> 8) | \ |
| 412 | ((a & 0xFF000000) >> 24)) |
| 413 | #else |
| 414 | /* If DXE HW does not need endian swap, DO NOTHING */ |
| 415 | #define WLANDXE_U32_SWAP_ENDIAN(a) (a) |
| 416 | #endif /* WLANDXE_ENDIAN_SWAP_ENABLE */ |
| 417 | |
| 418 | /* Log Definition will be mappped with PAL MSG */ |
| 419 | #define HDXE_MSG WPAL_TRACE |
| 420 | #define HDXE_ASSERT(a) VOS_ASSERT(a) |
| 421 | |
| 422 | /*---------------------------------------------------------------------------- |
| 423 | * Type Declarations |
| 424 | * -------------------------------------------------------------------------*/ |
| 425 | /* DMA Channel Q handle Method type |
| 426 | * Linear handle or circular */ |
| 427 | typedef enum |
| 428 | { |
| 429 | WLANDXE_CHANNEL_HANDLE_LINEAR, |
| 430 | WLANDXE_CHANNEL_HANDLE_CIRCULA |
| 431 | }WLANDXE_ChannelHandleType; |
| 432 | |
| 433 | typedef enum |
| 434 | { |
| 435 | WLANDXE_TX_COMP_INT_LR_THRESHOLD, |
| 436 | WLANDXE_TX_COMP_INT_PER_K_FRAMES, |
| 437 | WLANDXE_TX_COMP_INT_TIMER |
| 438 | } WLANDXE_TXCompIntEnableType; |
| 439 | |
| 440 | typedef enum |
| 441 | { |
| 442 | WLANDXE_SHORT_DESCRIPTOR, |
| 443 | WLANDXE_LONG_DESCRIPTOR |
| 444 | } WLANDXE_DescriptorType; |
| 445 | |
| 446 | typedef enum |
| 447 | { |
| 448 | WLANDXE_DMA_CHANNEL_0, |
| 449 | WLANDXE_DMA_CHANNEL_1, |
| 450 | WLANDXE_DMA_CHANNEL_2, |
| 451 | WLANDXE_DMA_CHANNEL_3, |
| 452 | WLANDXE_DMA_CHANNEL_4, |
| 453 | WLANDXE_DMA_CHANNEL_5, |
| 454 | WLANDXE_DMA_CHANNEL_6, |
| 455 | WLANDXE_DMA_CHANNEL_MAX |
| 456 | } WLANDXE_DMAChannelType; |
| 457 | |
| 458 | /** DXE HW Long Descriptor format */ |
| 459 | typedef struct |
| 460 | { |
| 461 | wpt_uint32 srcMemAddrL; |
| 462 | wpt_uint32 srcMemAddrH; |
| 463 | wpt_uint32 dstMemAddrL; |
| 464 | wpt_uint32 dstMemAddrH; |
| 465 | wpt_uint32 phyNextL; |
| 466 | wpt_uint32 phyNextH; |
| 467 | } WLANDXE_LongDesc; |
| 468 | |
| 469 | |
| 470 | /** DXE HW Short Descriptor format */ |
| 471 | typedef struct tDXEShortDesc |
| 472 | { |
| 473 | wpt_uint32 srcMemAddrL; |
| 474 | wpt_uint32 dstMemAddrL; |
| 475 | wpt_uint32 phyNextL; |
| 476 | } WLANDXE_ShortDesc; |
| 477 | |
| 478 | |
| 479 | /* DXE Descriptor Data Type |
| 480 | * Pick up from GEN5 */ |
| 481 | typedef struct |
| 482 | { |
| 483 | union |
| 484 | { |
| 485 | wpt_uint32 ctrl; |
| 486 | wpt_uint32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor |
| 487 | wpt_uint32 transferType :2; //0 = Host to Host space |
| 488 | wpt_uint32 eop :1; //End of Packet |
| 489 | wpt_uint32 bdHandling :1; //if transferType = Host to BMU, then 0 means first 128 bytes contain BD, and 1 means create new empty BD |
| 490 | wpt_uint32 siq :1; // SIQ |
| 491 | wpt_uint32 diq :1; // DIQ |
| 492 | wpt_uint32 pduRel :1; //0 = don't release BD and PDUs when done, 1 = release them |
| 493 | wpt_uint32 bthldSel :4; //BMU Threshold Select |
| 494 | wpt_uint32 prio :3; //Specifies the priority level to use for the transfer |
| 495 | wpt_uint32 stopChannel :1; //1 = DMA stops processing further, channel requires re-enabling after this |
| 496 | wpt_uint32 intr :1; //Interrupt on Descriptor Done |
| 497 | wpt_uint32 rsvd :1; //reserved |
| 498 | wpt_uint32 transferSize :14; //14 bits used - ignored for BMU transfers, only used for host to host transfers? |
| 499 | } descCtrl; |
| 500 | wpt_uint32 xfrSize; |
| 501 | union |
| 502 | { |
| 503 | WLANDXE_LongDesc dxe_long_desc; |
| 504 | WLANDXE_ShortDesc dxe_short_desc; |
| 505 | }dxedesc; |
| 506 | } WLANDXE_DescType; |
| 507 | |
| 508 | typedef struct |
| 509 | { |
| 510 | void *nextCtrlBlk; |
| 511 | wpt_packet *xfrFrame; |
| 512 | WLANDXE_DescType *linkedDesc; |
Arun Kumar Khandavalli | 6119f7d | 2013-12-18 00:16:17 +0530 | [diff] [blame] | 513 | wpt_uint32 linkedDescPhyAddr; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 514 | wpt_uint32 ctrlBlkOrder; |
| 515 | #ifdef FEATURE_R33D |
| 516 | wpt_uint32 shadowBufferVa; |
| 517 | #endif /* FEATURE_R33D */ |
| 518 | } WLANDXE_DescCtrlBlkType; |
| 519 | |
| 520 | typedef struct |
| 521 | { |
| 522 | /* Q handle method, linear or ring */ |
| 523 | WLANDXE_ChannelHandleType queueMethod; |
| 524 | |
| 525 | /* Number of descriptors for DXE that can be queued for transfer at one time */ |
| 526 | wpt_uint32 nDescs; |
| 527 | |
| 528 | /* Maximum number of receive buffers of shared memory to use for this pipe */ |
| 529 | wpt_uint32 nRxBuffers; |
| 530 | |
| 531 | /* Reference WQ - for H2B and B2H only */ |
| 532 | wpt_uint32 refWQ; |
| 533 | |
| 534 | /* for usb only, endpoint info for CH_SADR or CH_DADR */ |
| 535 | wpt_uint32 refEP; |
| 536 | |
| 537 | /* H2B(Tx), B2H(Rx), H2H(SRAM<->HostMem R/W) */ |
| 538 | wpt_uint32 xfrType; |
| 539 | |
| 540 | /* Channel Priority 7(Highest) - 0(Lowest) */ |
| 541 | wpt_uint32 chPriority; |
| 542 | |
| 543 | /* 1 = BD attached to frames for this pipe */ |
| 544 | wpt_boolean bdPresent; |
| 545 | |
| 546 | wpt_uint32 chk_size; |
| 547 | |
| 548 | wpt_uint32 bmuThdSel; |
| 549 | |
| 550 | /* Added in Gen5 for Prefetch */ |
| 551 | wpt_boolean useLower4G; |
| 552 | |
| 553 | wpt_boolean useShortDescFmt; |
| 554 | /* Till here inharited from GEN5 code */ |
| 555 | /* From now on, added for PRIMA */ |
| 556 | } WLANDXE_ChannelConfigType; |
| 557 | |
| 558 | typedef struct |
| 559 | { |
| 560 | wpt_uint32 chDXEBaseAddr; |
| 561 | wpt_uint32 chDXEStatusRegAddr; |
| 562 | wpt_uint32 chDXEDesclRegAddr; |
| 563 | wpt_uint32 chDXEDeschRegAddr; |
| 564 | wpt_uint32 chDXELstDesclRegAddr; |
| 565 | wpt_uint32 chDXECtrlRegAddr; |
| 566 | wpt_uint32 chDXESzRegAddr; |
| 567 | wpt_uint32 chDXEDadrlRegAddr; |
| 568 | wpt_uint32 chDXEDadrhRegAddr; |
| 569 | wpt_uint32 chDXESadrlRegAddr; |
| 570 | wpt_uint32 chDXESadrhRegAddr; |
| 571 | } WLANDXE_ChannelRegisterType; |
| 572 | |
| 573 | typedef struct |
| 574 | { |
| 575 | wpt_uint32 refWQ_swapped; |
| 576 | wpt_boolean chEnabled; |
| 577 | wpt_boolean chConfigured; |
| 578 | wpt_uint32 channel; |
| 579 | wpt_uint32 chk_size_mask; |
| 580 | wpt_uint32 bmuThdSel_mask; |
| 581 | wpt_uint32 cw_ctrl_read; |
| 582 | wpt_uint32 cw_ctrl_write; |
| 583 | wpt_uint32 cw_ctrl_write_valid; |
| 584 | wpt_uint32 cw_ctrl_write_eop; |
| 585 | wpt_uint32 cw_ctrl_write_eop_int; |
| 586 | wpt_uint32 chan_mask; |
| 587 | wpt_uint32 chan_mask_read_disable; |
| 588 | wpt_uint32 intMask; |
| 589 | } WLANDXE_ChannelExConfigType; |
| 590 | |
| 591 | typedef struct |
| 592 | { |
| 593 | WDTS_ChannelType channelType; |
| 594 | WLANDXE_DescCtrlBlkType *headCtrlBlk; |
| 595 | WLANDXE_DescCtrlBlkType *tailCtrlBlk; |
| 596 | #if !(defined(FEATURE_R33D) || defined(WLANDXE_TEST_CHANNEL_ENABLE)) |
| 597 | WLANDXE_DescType *descriptorAllocation; |
| 598 | #endif |
| 599 | WLANDXE_DescType *DescBottomLoc; |
Arun Kumar Khandavalli | 6119f7d | 2013-12-18 00:16:17 +0530 | [diff] [blame] | 600 | wpt_uint32 descBottomLocPhyAddr; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 601 | wpt_uint32 numDesc; |
| 602 | wpt_uint32 numFreeDesc; |
| 603 | wpt_uint32 numRsvdDesc; |
| 604 | wpt_uint32 maxFrameSize; |
| 605 | wpt_uint32 numFragmentCurrentChain; |
| 606 | wpt_uint32 numFrameBeforeInt; |
| 607 | wpt_uint32 numTotalFrame; |
| 608 | wpt_mutex dxeChannelLock; |
| 609 | wpt_boolean hitLowResource; |
| 610 | WLANDXE_ChannelConfigType channelConfig; |
| 611 | WLANDXE_ChannelRegisterType channelRegister; |
| 612 | WLANDXE_ChannelExConfigType extraConfig; |
| 613 | WLANDXE_DMAChannelType assignedDMAChannel; |
| 614 | wpt_uint64 rxDoneHistogram; |
Madan Mohan Koyyalamudi | ea77701 | 2012-10-31 14:22:34 -0700 | [diff] [blame] | 615 | wpt_timer healthMonitorTimer; |
| 616 | wpt_msg *healthMonitorMsg; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 617 | } WLANDXE_ChannelCBType; |
| 618 | |
| 619 | typedef struct |
| 620 | { |
| 621 | WLANDXE_TXCompIntEnableType txIntEnable; |
| 622 | unsigned int txLowResourceThreshold_LoPriCh; |
| 623 | unsigned int txLowResourceThreshold_HiPriCh; |
| 624 | unsigned int rxLowResourceThreshold; |
| 625 | unsigned int txInterruptEnableFrameCount; |
| 626 | unsigned int txInterruptEnablePeriod; |
| 627 | } WLANDXE_TxCompIntConfigType; |
| 628 | |
| 629 | typedef struct |
| 630 | { |
| 631 | WLANDXE_ChannelCBType dxeChannel[WDTS_CHANNEL_MAX]; |
| 632 | WLANDXE_RxFrameReadyCbType rxReadyCB; |
| 633 | WLANDXE_TxCompleteCbType txCompCB; |
| 634 | WLANDXE_LowResourceCbType lowResourceCB; |
| 635 | WLANDXE_TxCompIntConfigType txCompInt; |
| 636 | void *clientCtxt; |
| 637 | wpt_uint32 interruptPath; |
| 638 | wpt_msg *rxIsrMsg; |
| 639 | wpt_msg *txIsrMsg; |
| 640 | wpt_msg *rxPktAvailMsg; |
| 641 | volatile WLANDXE_PowerStateType hostPowerState; |
| 642 | wpt_boolean rxIntDisabledByIMPS; |
| 643 | wpt_boolean txIntDisabledByIMPS; |
| 644 | WLANDXE_SetPowerStateCbType setPowerStateCb; |
| 645 | volatile WLANDXE_RivaPowerStateType rivaPowerState; |
| 646 | wpt_boolean ringNotEmpty; |
| 647 | wpt_boolean txIntEnable; |
| 648 | wpt_uint32 txCompletedFrames; |
| 649 | wpt_uint8 ucTxMsgCnt; |
| 650 | wpt_uint16 lastKickOffDxe; |
| 651 | wpt_uint32 dxeCookie; |
| 652 | wpt_packet *freeRXPacket; |
| 653 | wpt_boolean rxPalPacketUnavailable; |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 654 | wpt_boolean driverReloadInProcessing; |
Leo Chang | ac1d361 | 2013-07-01 15:15:51 -0700 | [diff] [blame] | 655 | wpt_boolean smsmToggled; |
Mihir Shete | 44547fb | 2014-03-10 14:15:42 +0530 | [diff] [blame] | 656 | #ifdef WLAN_DXE_LOW_RESOURCE_TIMER |
Leo Chang | 72cdfd3 | 2013-10-17 20:36:30 -0700 | [diff] [blame] | 657 | wpt_timer rxResourceAvailableTimer; |
Mihir Shete | 44547fb | 2014-03-10 14:15:42 +0530 | [diff] [blame] | 658 | #endif |
Mihir Shete | fdc9f53 | 2014-01-09 15:03:02 +0530 | [diff] [blame] | 659 | wpt_timer dxeSSRTimer; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 660 | } WLANDXE_CtrlBlkType; |
| 661 | |
| 662 | /*========================================================================== |
| 663 | @ Function Name |
| 664 | dxeCommonDefaultConfig |
| 665 | |
| 666 | @ Description |
| 667 | |
| 668 | @ Parameters |
| 669 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 670 | DXE host driver main control block |
| 671 | |
| 672 | @ Return |
| 673 | wpt_status |
| 674 | |
| 675 | ===========================================================================*/ |
| 676 | extern wpt_status dxeCommonDefaultConfig |
| 677 | ( |
| 678 | WLANDXE_CtrlBlkType *dxeCtrlBlk |
| 679 | ); |
| 680 | |
| 681 | /*========================================================================== |
| 682 | @ Function Name |
| 683 | dxeChannelDefaultConfig |
| 684 | |
| 685 | @ Description |
| 686 | Get defualt configuration values from pre defined structure |
| 687 | All the channels must have it's own configurations |
| 688 | |
| 689 | @ Parameters |
| 690 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 691 | DXE host driver main control block |
| 692 | WLANDXE_ChannelCBType *channelEntry |
| 693 | Channel specific control block |
| 694 | |
| 695 | @ Return |
| 696 | wpt_status |
| 697 | |
| 698 | ===========================================================================*/ |
| 699 | extern wpt_status dxeChannelDefaultConfig |
| 700 | ( |
| 701 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 702 | WLANDXE_ChannelCBType *channelEntry |
| 703 | ); |
| 704 | |
| 705 | #endif /* WLAN_QCT_DXE_I_H */ |