blob: 452e67f01a70958b778f886b2dcd9b126fc90544 [file] [log] [blame]
Vivek126db5d2018-07-25 22:05:04 +05301/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -08002 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +053029#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +053030#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -070034#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +053035#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
41#ifdef CONFIG_MCL
hangtian04f0ad42019-06-07 11:04:02 +080042#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
43 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +053044#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
45#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +053046#else
jitiphil60ac9aa2018-10-05 19:54:04 +053047#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
48#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +053049#endif
Vivek126db5d2018-07-25 22:05:04 +053050#endif
51
52#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
53#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
54
55#ifdef CONFIG_MCL
56#define WLAN_CFG_PER_PDEV_RX_RING 0
57#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +053058#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -070059#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +053060#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -070061/* Size of TCL TX Ring */
62#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +053063#define WLAN_CFG_PER_PDEV_TX_RING 0
64#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
65#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
66#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +053067#else
68#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +053069#define WLAN_CFG_PER_PDEV_TX_RING 1
70#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
71#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
72#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +053073#endif
74#define WLAN_CFG_TX_COMP_RING_SIZE 1024
75
76/* Tx Descriptor and Tx Extension Descriptor pool sizes */
77#define WLAN_CFG_NUM_TX_DESC 1024
78#define WLAN_CFG_NUM_TX_EXT_DESC 1024
79
80/* Interrupt Mitigation - Batch threshold in terms of number of frames */
81#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
82#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
83#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
84
85/* Interrupt Mitigation - Timer threshold in us */
86#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
87#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
88#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +053089#endif
90
91#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
92#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
93
94#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
95#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
96
97#define WLAN_CFG_TX_RING_SIZE_MIN 512
98#define WLAN_CFG_TX_RING_SIZE_MAX 2048
99
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530100#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530101#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
102
103#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530104#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530105
106#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
107#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
108
109#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
110#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
111
112#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
113#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
114
115#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
116#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
117
118#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
119#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
120
121#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
122#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
123
124#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
125#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
126
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530127#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
128#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530129#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530130
131#ifdef QCA_LL_TX_FLOW_CONTROL_V2
132
133/* Per vdev pools */
134#define WLAN_CFG_NUM_TX_DESC_POOL 3
135#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
136
137#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
138
139#ifdef TX_PER_PDEV_DESC_POOL
140#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
141#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
142
143#else /* TX_PER_PDEV_DESC_POOL */
144
145#define WLAN_CFG_NUM_TX_DESC_POOL 3
146#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
147
148#endif /* TX_PER_PDEV_DESC_POOL */
149#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
150
151#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
152#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
153
154#define WLAN_CFG_HTT_PKT_TYPE 2
155#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
156#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
157
158#define WLAN_CFG_MAX_PEER_ID 64
159#define WLAN_CFG_MAX_PEER_ID_MIN 64
160#define WLAN_CFG_MAX_PEER_ID_MAX 64
161
162#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
163#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
164#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
165
166#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
167#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
168#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
169
170#define WLAN_CFG_NUM_REO_DEST_RING 4
171#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
172#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
173
174#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
175#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
176#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
177
178#define WLAN_CFG_TCL_CMD_RING_SIZE 32
179#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
180#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
181
182#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
183#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
184#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
185
186#if defined(QCA_WIFI_QCA6290)
187#define WLAN_CFG_REO_DST_RING_SIZE 1024
188#else
189#define WLAN_CFG_REO_DST_RING_SIZE 2048
190#endif
191
192#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
193#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
194
195#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
196#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
197#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
198
199#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530200#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530201#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530202#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530203#else
204#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
205#endif
Vivek126db5d2018-07-25 22:05:04 +0530206
207#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
208#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
209#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
210
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700211#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530212#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700213#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530214
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700215#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530216#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800217#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530218
219#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
220#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
221#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
222
223#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530224#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530225#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
226
227#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530228#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800229#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530230
231#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530232#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800233#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530234
235#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530236#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800237#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530238
239#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
240#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800241#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530242
243#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
244#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700245#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530246
247/* DP INI Declerations */
248#define CFG_DP_HTT_PACKET_TYPE \
249 CFG_INI_UINT("dp_htt_packet_type", \
250 WLAN_CFG_HTT_PKT_TYPE_MIN, \
251 WLAN_CFG_HTT_PKT_TYPE_MAX, \
252 WLAN_CFG_HTT_PKT_TYPE, \
253 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
254
255#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
256 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700257 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
258 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
259 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Vivek126db5d2018-07-25 22:05:04 +0530260 CFG_VALUE_OR_DEFAULT, "DP INT threshold Other")
261
262#define CFG_DP_INT_BATCH_THRESHOLD_RX \
263 CFG_INI_UINT("dp_int_batch_threshold_rx", \
264 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
265 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
266 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
267 CFG_VALUE_OR_DEFAULT, "DP INT threshold Rx")
268
269#define CFG_DP_INT_BATCH_THRESHOLD_TX \
270 CFG_INI_UINT("dp_int_batch_threshold_tx", \
271 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
272 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
273 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
274 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
275
276#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
277 CFG_INI_UINT("dp_int_timer_threshold_other", \
278 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
279 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
280 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
281 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
282
283#define CFG_DP_INT_TIMER_THRESHOLD_RX \
284 CFG_INI_UINT("dp_int_timer_threshold_rx", \
285 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
286 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
287 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
288 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
289
290#define CFG_DP_INT_TIMER_THRESHOLD_TX \
291 CFG_INI_UINT("dp_int_timer_threshold_tx", \
292 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
293 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
294 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
295 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
296
297#define CFG_DP_MAX_ALLOC_SIZE \
298 CFG_INI_UINT("dp_max_alloc_size", \
299 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
300 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
301 WLAN_CFG_MAX_ALLOC_SIZE, \
302 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
303
304#define CFG_DP_MAX_CLIENTS \
305 CFG_INI_UINT("dp_max_clients", \
306 WLAN_CFG_MAX_CLIENTS_MIN, \
307 WLAN_CFG_MAX_CLIENTS_MAX, \
308 WLAN_CFG_MAX_CLIENTS, \
309 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
310
311#define CFG_DP_MAX_PEER_ID \
312 CFG_INI_UINT("dp_max_peer_id", \
313 WLAN_CFG_MAX_PEER_ID_MIN, \
314 WLAN_CFG_MAX_PEER_ID_MAX, \
315 WLAN_CFG_MAX_PEER_ID, \
316 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
317
318#define CFG_DP_REO_DEST_RINGS \
319 CFG_INI_UINT("dp_reo_dest_rings", \
320 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
321 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
322 WLAN_CFG_NUM_REO_DEST_RING, \
323 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
324
325#define CFG_DP_TCL_DATA_RINGS \
326 CFG_INI_UINT("dp_tcl_data_rings", \
327 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
328 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
329 WLAN_CFG_NUM_TCL_DATA_RINGS, \
330 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
331
332#define CFG_DP_TX_DESC \
333 CFG_INI_UINT("dp_tx_desc", \
334 WLAN_CFG_NUM_TX_DESC_MIN, \
335 WLAN_CFG_NUM_TX_DESC_MAX, \
336 WLAN_CFG_NUM_TX_DESC, \
337 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
338
339#define CFG_DP_TX_EXT_DESC \
340 CFG_INI_UINT("dp_tx_ext_desc", \
341 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
342 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
343 WLAN_CFG_NUM_TX_EXT_DESC, \
344 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
345
346#define CFG_DP_TX_EXT_DESC_POOLS \
347 CFG_INI_UINT("dp_tx_ext_desc_pool", \
348 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
349 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
350 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
351 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
352
353#define CFG_DP_PDEV_RX_RING \
354 CFG_INI_UINT("dp_pdev_rx_ring", \
355 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
356 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
357 WLAN_CFG_PER_PDEV_RX_RING, \
358 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
359
360#define CFG_DP_PDEV_TX_RING \
361 CFG_INI_UINT("dp_pdev_tx_ring", \
362 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
363 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
364 WLAN_CFG_PER_PDEV_TX_RING, \
365 CFG_VALUE_OR_DEFAULT, \
366 "DP PDEV Tx Ring")
367
368#define CFG_DP_RX_DEFRAG_TIMEOUT \
369 CFG_INI_UINT("dp_rx_defrag_timeout", \
370 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
371 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
372 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
373 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
374
375#define CFG_DP_TX_COMPL_RING_SIZE \
376 CFG_INI_UINT("dp_tx_compl_ring_size", \
377 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
378 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
379 WLAN_CFG_TX_COMP_RING_SIZE, \
380 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
381
382#define CFG_DP_TX_RING_SIZE \
383 CFG_INI_UINT("dp_tx_ring_size", \
384 WLAN_CFG_TX_RING_SIZE_MIN,\
385 WLAN_CFG_TX_RING_SIZE_MAX,\
386 WLAN_CFG_TX_RING_SIZE,\
387 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
388
389#define CFG_DP_NSS_COMP_RING_SIZE \
390 CFG_INI_UINT("dp_nss_comp_ring_size", \
391 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
392 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
393 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
394 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
395
396#define CFG_DP_PDEV_LMAC_RING \
397 CFG_INI_UINT("dp_pdev_lmac_ring", \
398 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
399 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
400 WLAN_CFG_PER_PDEV_LMAC_RING, \
401 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
402
403#define CFG_DP_BASE_HW_MAC_ID \
404 CFG_INI_UINT("dp_base_hw_macid", \
405 0, 1, 1, \
406 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
407
Vivek126db5d2018-07-25 22:05:04 +0530408#define CFG_DP_RX_HASH \
409 CFG_INI_BOOL("dp_rx_hash", true, \
410 "DP Rx Hash")
411
412#define CFG_DP_TSO \
413 CFG_INI_BOOL("TSOEnable", false, \
414 "DP TSO Enabled")
415
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530416#define CFG_DP_LRO \
417 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
418 "DP LRO Enable")
419
420#define CFG_DP_SG \
421 CFG_INI_BOOL("dp_sg_support", false, \
422 "DP SG Enable")
423
424#define CFG_DP_GRO \
425 CFG_INI_BOOL("GROEnable", false, \
426 "DP GRO Enable")
427
428#define CFG_DP_OL_TX_CSUM \
429 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
430 "DP tx csum Enable")
431
432#define CFG_DP_OL_RX_CSUM \
433 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
434 "DP rx csum Enable")
435
436#define CFG_DP_RAWMODE \
437 CFG_INI_BOOL("dp_rawmode_support", false, \
438 "DP rawmode Enable")
439
440#define CFG_DP_PEER_FLOW_CTRL \
441 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
442 "DP peer flow ctrl Enable")
443
Vivek126db5d2018-07-25 22:05:04 +0530444#define CFG_DP_NAPI \
445 CFG_INI_BOOL("dp_napi_enabled", MCL_OR_WIN_VALUE(true, false), \
446 "DP Napi Enabled")
447
448#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530449 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530450 "DP TCP UDP Checksum Offload")
451
452#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
453 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
454 "DP Defrag Timeout Check")
455
456#define CFG_DP_WBM_RELEASE_RING \
457 CFG_INI_UINT("dp_wbm_release_ring", \
458 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
459 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
460 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
461 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
462
463#define CFG_DP_TCL_CMD_RING \
464 CFG_INI_UINT("dp_tcl_cmd_ring", \
465 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
466 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
467 WLAN_CFG_TCL_CMD_RING_SIZE, \
468 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
469
470#define CFG_DP_TCL_STATUS_RING \
471 CFG_INI_UINT("dp_tcl_status_ring",\
472 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
473 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
474 WLAN_CFG_TCL_STATUS_RING_SIZE, \
475 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
476
477#define CFG_DP_REO_REINJECT_RING \
478 CFG_INI_UINT("dp_reo_reinject_ring", \
479 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
480 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
481 WLAN_CFG_REO_REINJECT_RING_SIZE, \
482 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
483
484#define CFG_DP_RX_RELEASE_RING \
485 CFG_INI_UINT("dp_rx_release_ring", \
486 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
487 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
488 WLAN_CFG_RX_RELEASE_RING_SIZE, \
489 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
490
491#define CFG_DP_REO_EXCEPTION_RING \
492 CFG_INI_UINT("dp_reo_exception_ring", \
493 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
494 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
495 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
496 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
497
498#define CFG_DP_REO_CMD_RING \
499 CFG_INI_UINT("dp_reo_cmd_ring", \
500 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
501 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
502 WLAN_CFG_REO_CMD_RING_SIZE, \
503 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
504
505#define CFG_DP_REO_STATUS_RING \
506 CFG_INI_UINT("dp_reo_status_ring", \
507 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
508 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
509 WLAN_CFG_REO_STATUS_RING_SIZE, \
510 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
511
512#define CFG_DP_RXDMA_BUF_RING \
513 CFG_INI_UINT("dp_rxdma_buf_ring", \
514 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
515 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
516 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
517 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
518
519#define CFG_DP_RXDMA_REFILL_RING \
520 CFG_INI_UINT("dp_rxdma_refill_ring", \
521 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
522 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
523 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
524 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
525
526#define CFG_DP_RXDMA_MONITOR_BUF_RING \
527 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
528 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
529 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
530 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
531 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
532
533#define CFG_DP_RXDMA_MONITOR_DST_RING \
534 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
535 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
536 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
537 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
538 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
539
540#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
541 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
542 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
543 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
544 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
545 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
546
547#define CFG_DP_RXDMA_MONITOR_DESC_RING \
548 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
549 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
550 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
551 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
552 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
553
554#define CFG_DP_RXDMA_ERR_DST_RING \
555 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
556 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
557 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
558 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
559 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
560
Krunal Soni03ba0f52019-02-12 11:44:46 -0800561#define CFG_DP_PER_PKT_LOGGING \
562 CFG_INI_UINT("enable_verbose_debug", \
563 0, 0xffff, 0, \
564 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
565
jitiphil60ac9aa2018-10-05 19:54:04 +0530566#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
567 CFG_INI_UINT("TxFlowStartQueueOffset", \
568 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
569 CFG_VALUE_OR_DEFAULT, "Start queue offset")
570
571#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
572 CFG_INI_UINT("TxFlowStopQueueThreshold", \
573 0, 50, 15, \
574 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
575
576#define CFG_DP_IPA_UC_TX_BUF_SIZE \
577 CFG_INI_UINT("IpaUcTxBufSize", \
578 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
579 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
580
581#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
582 CFG_INI_UINT("IpaUcTxPartitionBase", \
583 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
584 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
585
586#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
587 CFG_INI_UINT("IpaUcRxIndRingCount", \
588 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
589 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
590
591#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
592 CFG_INI_UINT("gReorderOffloadSupported", \
593 0, 1, 1, \
594 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
595
596#define CFG_DP_AP_STA_SECURITY_SEPERATION \
597 CFG_INI_BOOL("gDisableIntraBssFwd", \
598 false, "Disable intrs BSS Rx packets")
599
600#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
601 CFG_INI_BOOL("gEnableDataStallDetection", \
602 true, "Enable/Disable Data stall detection")
603
Vivek126db5d2018-07-25 22:05:04 +0530604#define CFG_DP \
605 CFG(CFG_DP_HTT_PACKET_TYPE) \
606 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
607 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
608 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
609 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
610 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
611 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
612 CFG(CFG_DP_MAX_ALLOC_SIZE) \
613 CFG(CFG_DP_MAX_CLIENTS) \
614 CFG(CFG_DP_MAX_PEER_ID) \
615 CFG(CFG_DP_REO_DEST_RINGS) \
616 CFG(CFG_DP_TCL_DATA_RINGS) \
617 CFG(CFG_DP_TX_DESC) \
618 CFG(CFG_DP_TX_EXT_DESC) \
619 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
620 CFG(CFG_DP_PDEV_RX_RING) \
621 CFG(CFG_DP_PDEV_TX_RING) \
622 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
623 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
624 CFG(CFG_DP_TX_RING_SIZE) \
625 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
626 CFG(CFG_DP_PDEV_LMAC_RING) \
627 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530628 CFG(CFG_DP_RX_HASH) \
629 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530630 CFG(CFG_DP_LRO) \
631 CFG(CFG_DP_SG) \
632 CFG(CFG_DP_GRO) \
633 CFG(CFG_DP_OL_TX_CSUM) \
634 CFG(CFG_DP_OL_RX_CSUM) \
635 CFG(CFG_DP_RAWMODE) \
636 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530637 CFG(CFG_DP_NAPI) \
638 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
639 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
640 CFG(CFG_DP_WBM_RELEASE_RING) \
641 CFG(CFG_DP_TCL_CMD_RING) \
642 CFG(CFG_DP_TCL_STATUS_RING) \
643 CFG(CFG_DP_REO_REINJECT_RING) \
644 CFG(CFG_DP_RX_RELEASE_RING) \
645 CFG(CFG_DP_REO_EXCEPTION_RING) \
646 CFG(CFG_DP_REO_CMD_RING) \
647 CFG(CFG_DP_REO_STATUS_RING) \
648 CFG(CFG_DP_RXDMA_BUF_RING) \
649 CFG(CFG_DP_RXDMA_REFILL_RING) \
650 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
651 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
652 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
653 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530654 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800655 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530656 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
657 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
658 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
659 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
660 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
661 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
662 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
663 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION)
Vivek126db5d2018-07-25 22:05:04 +0530664
665#endif /* _CFG_DP_H_ */