Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1 | /* |
Mohit Khanna | 5f26348 | 2019-02-14 18:42:20 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | #ifndef _HAL_GENERIC_API_H_ |
| 19 | #define _HAL_GENERIC_API_H_ |
| 20 | |
| 21 | #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ |
| 22 | ((struct rx_msdu_desc_info *) \ |
| 23 | _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ |
| 24 | UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) |
| 25 | /** |
| 26 | * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr |
| 27 | * @msdu_details_ptr - Pointer to msdu_details_ptr |
| 28 | * Return - Pointer to rx_msdu_desc_info structure. |
| 29 | * |
| 30 | */ |
| 31 | static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr) |
| 32 | { |
| 33 | return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); |
| 34 | } |
| 35 | |
| 36 | |
| 37 | #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ |
| 38 | ((struct rx_msdu_details *) \ |
| 39 | _OFFSET_TO_BYTE_PTR((link_desc),\ |
| 40 | UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) |
| 41 | /** |
| 42 | * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details |
| 43 | * @link_desc - Pointer to link desc |
| 44 | * Return - Pointer to rx_msdu_details structure |
| 45 | * |
| 46 | */ |
| 47 | |
| 48 | static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc) |
| 49 | { |
| 50 | return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); |
| 51 | } |
| 52 | |
| 53 | /** |
| 54 | * hal_tx_comp_get_status() - TQM Release reason |
| 55 | * @hal_desc: completion ring Tx status |
| 56 | * |
| 57 | * This function will parse the WBM completion descriptor and populate in |
| 58 | * HAL structure |
| 59 | * |
| 60 | * Return: none |
| 61 | */ |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 62 | static inline void hal_tx_comp_get_status_generic(void *desc, |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 63 | void *ts1, void *hal) |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 64 | { |
| 65 | uint8_t rate_stats_valid = 0; |
| 66 | uint32_t rate_stats = 0; |
| 67 | struct hal_tx_completion_status *ts = |
| 68 | (struct hal_tx_completion_status *)ts1; |
| 69 | |
| 70 | ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, |
| 71 | TQM_STATUS_NUMBER); |
| 72 | ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, |
| 73 | ACK_FRAME_RSSI); |
| 74 | ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); |
| 75 | ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); |
| 76 | ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, |
| 77 | MSDU_PART_OF_AMSDU); |
| 78 | |
| 79 | ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); |
| 80 | ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); |
| 81 | ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, |
| 82 | TRANSMIT_COUNT); |
| 83 | |
| 84 | rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, |
| 85 | TX_RATE_STATS); |
| 86 | |
| 87 | rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, |
| 88 | TX_RATE_STATS_INFO_VALID, rate_stats); |
| 89 | |
| 90 | ts->valid = rate_stats_valid; |
| 91 | |
| 92 | if (rate_stats_valid) { |
| 93 | ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, |
| 94 | rate_stats); |
| 95 | ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, |
| 96 | TRANSMIT_PKT_TYPE, rate_stats); |
| 97 | ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, |
| 98 | TRANSMIT_STBC, rate_stats); |
| 99 | ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, |
| 100 | rate_stats); |
| 101 | ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, |
| 102 | rate_stats); |
| 103 | ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, |
| 104 | rate_stats); |
| 105 | ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, |
| 106 | rate_stats); |
| 107 | ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, |
| 108 | rate_stats); |
| 109 | } |
| 110 | |
| 111 | ts->release_src = hal_tx_comp_get_buffer_source(desc); |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 112 | ts->status = hal_tx_comp_get_release_reason(desc, hal); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 113 | |
| 114 | ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, |
| 115 | TX_RATE_STATS_INFO_TX_RATE_STATS); |
| 116 | } |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 117 | |
| 118 | /** |
| 119 | * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor |
| 120 | * @desc: Handle to Tx Descriptor |
| 121 | * @paddr: Physical Address |
| 122 | * @pool_id: Return Buffer Manager ID |
| 123 | * @desc_id: Descriptor ID |
| 124 | * @type: 0 - Address points to a MSDU buffer |
| 125 | * 1 - Address points to MSDU extension descriptor |
| 126 | * |
| 127 | * Return: void |
| 128 | */ |
| 129 | static inline void hal_tx_desc_set_buf_addr_generic(void *desc, |
| 130 | dma_addr_t paddr, uint8_t pool_id, |
| 131 | uint32_t desc_id, uint8_t type) |
| 132 | { |
| 133 | /* Set buffer_addr_info.buffer_addr_31_0 */ |
| 134 | HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = |
| 135 | HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); |
| 136 | |
| 137 | /* Set buffer_addr_info.buffer_addr_39_32 */ |
| 138 | HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, |
| 139 | BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= |
| 140 | HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, |
| 141 | (((uint64_t) paddr) >> 32)); |
| 142 | |
| 143 | /* Set buffer_addr_info.return_buffer_manager = pool id */ |
| 144 | HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, |
| 145 | BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= |
| 146 | HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, |
| 147 | RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); |
| 148 | |
| 149 | /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ |
| 150 | HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, |
| 151 | BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= |
| 152 | HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); |
| 153 | |
| 154 | /* Set Buffer or Ext Descriptor Type */ |
| 155 | HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, |
| 156 | BUF_OR_EXT_DESC_TYPE) |= |
| 157 | HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); |
| 158 | } |
| 159 | |
Vevek Venkatesan | 735d9fe | 2019-06-06 19:21:25 +0530 | [diff] [blame] | 160 | #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) |
chenguo | f51e922 | 2018-04-20 14:34:25 +0800 | [diff] [blame] | 161 | /** |
| 162 | * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL |
| 163 | * tlv_tag: Taf of the TLVs |
| 164 | * rx_tlv: the pointer to the TLVs |
| 165 | * @ppdu_info: pointer to ppdu_info |
| 166 | * |
| 167 | * Return: true if the tlv is handled, false if not |
| 168 | */ |
| 169 | static inline bool |
| 170 | hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, |
| 171 | struct hal_rx_ppdu_info *ppdu_info) |
| 172 | { |
| 173 | uint32_t value; |
| 174 | |
| 175 | switch (tlv_tag) { |
| 176 | case WIFIPHYRX_HE_SIG_A_MU_UL_E: |
| 177 | { |
| 178 | uint8_t *he_sig_a_mu_ul_info = |
| 179 | (uint8_t *)rx_tlv + |
| 180 | HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, |
| 181 | HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); |
| 182 | ppdu_info->rx_status.he_flags = 1; |
| 183 | |
| 184 | value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, |
| 185 | FORMAT_INDICATION); |
| 186 | if (value == 0) { |
| 187 | ppdu_info->rx_status.he_data1 = |
| 188 | QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; |
| 189 | } else { |
| 190 | ppdu_info->rx_status.he_data1 = |
| 191 | QDF_MON_STATUS_HE_SU_FORMAT_TYPE; |
| 192 | } |
chenguo | 35695dd | 2018-09-17 15:09:06 +0800 | [diff] [blame] | 193 | |
| 194 | /* data1 */ |
| 195 | ppdu_info->rx_status.he_data1 |= |
| 196 | QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | |
| 197 | QDF_MON_STATUS_HE_DL_UL_KNOWN | |
| 198 | QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; |
| 199 | |
| 200 | /* data2 */ |
| 201 | ppdu_info->rx_status.he_data2 |= |
| 202 | QDF_MON_STATUS_TXOP_KNOWN; |
| 203 | |
| 204 | /*data3*/ |
| 205 | value = HAL_RX_GET(he_sig_a_mu_ul_info, |
| 206 | HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); |
| 207 | ppdu_info->rx_status.he_data3 = value; |
| 208 | /* 1 for UL and 0 for DL */ |
| 209 | value = 1; |
| 210 | value = value << QDF_MON_STATUS_DL_UL_SHIFT; |
| 211 | ppdu_info->rx_status.he_data3 |= value; |
| 212 | |
| 213 | /*data4*/ |
| 214 | value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, |
| 215 | SPATIAL_REUSE); |
| 216 | ppdu_info->rx_status.he_data4 = value; |
| 217 | |
| 218 | /*data5*/ |
| 219 | value = HAL_RX_GET(he_sig_a_mu_ul_info, |
| 220 | HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); |
| 221 | ppdu_info->rx_status.he_data5 = value; |
| 222 | ppdu_info->rx_status.bw = value; |
| 223 | |
| 224 | /*data6*/ |
| 225 | value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, |
| 226 | TXOP_DURATION); |
| 227 | value = value << QDF_MON_STATUS_TXOP_SHIFT; |
| 228 | ppdu_info->rx_status.he_data6 |= value; |
chenguo | f51e922 | 2018-04-20 14:34:25 +0800 | [diff] [blame] | 229 | return true; |
| 230 | } |
| 231 | default: |
| 232 | return false; |
| 233 | } |
| 234 | } |
| 235 | #else |
| 236 | static inline bool |
| 237 | hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, |
| 238 | struct hal_rx_ppdu_info *ppdu_info) |
| 239 | { |
| 240 | return false; |
| 241 | } |
Vevek Venkatesan | 735d9fe | 2019-06-06 19:21:25 +0530 | [diff] [blame] | 242 | #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ |
chenguo | f51e922 | 2018-04-20 14:34:25 +0800 | [diff] [blame] | 243 | |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 244 | #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) |
| 245 | static inline void |
| 246 | hal_rx_handle_ofdma_info( |
| 247 | void *rx_tlv, |
| 248 | struct mon_rx_user_status *mon_rx_user_status) |
| 249 | { |
| 250 | mon_rx_user_status->ofdma_info_valid = |
| 251 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, |
| 252 | OFDMA_INFO_VALID); |
| 253 | mon_rx_user_status->dl_ofdma_ru_start_index = |
| 254 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, |
| 255 | DL_OFDMA_RU_START_INDEX); |
| 256 | mon_rx_user_status->dl_ofdma_ru_width = |
| 257 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, |
| 258 | DL_OFDMA_RU_WIDTH); |
| 259 | } |
| 260 | #else |
| 261 | static inline void |
| 262 | hal_rx_handle_ofdma_info(void *rx_tlv, |
| 263 | struct mon_rx_user_status *mon_rx_user_status) |
| 264 | { |
| 265 | } |
| 266 | #endif |
| 267 | |
Amir Patel | 1d4ac98 | 2019-04-25 11:49:01 +0530 | [diff] [blame] | 268 | #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ |
| 269 | ppdu_info, rssi_info_tlv) \ |
| 270 | { \ |
| 271 | ppdu_info->rx_status.rssi_chain[chain][0] = \ |
| 272 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ |
| 273 | RSSI_PRI20_CHAIN##chain); \ |
| 274 | ppdu_info->rx_status.rssi_chain[chain][1] = \ |
| 275 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ |
| 276 | RSSI_EXT20_CHAIN##chain); \ |
| 277 | ppdu_info->rx_status.rssi_chain[chain][2] = \ |
| 278 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ |
| 279 | RSSI_EXT40_LOW20_CHAIN##chain); \ |
| 280 | ppdu_info->rx_status.rssi_chain[chain][3] = \ |
| 281 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ |
| 282 | RSSI_EXT40_HIGH20_CHAIN##chain); \ |
| 283 | ppdu_info->rx_status.rssi_chain[chain][4] = \ |
| 284 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ |
| 285 | RSSI_EXT80_LOW20_CHAIN##chain); \ |
| 286 | ppdu_info->rx_status.rssi_chain[chain][5] = \ |
| 287 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ |
| 288 | RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ |
| 289 | ppdu_info->rx_status.rssi_chain[chain][6] = \ |
| 290 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ |
| 291 | RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ |
| 292 | ppdu_info->rx_status.rssi_chain[chain][7] = \ |
| 293 | HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ |
| 294 | RSSI_EXT80_HIGH20_CHAIN##chain); \ |
| 295 | } \ |
| 296 | |
| 297 | #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ |
| 298 | {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ |
| 299 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ |
| 300 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ |
| 301 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ |
| 302 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ |
| 303 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ |
| 304 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ |
| 305 | HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ |
| 306 | |
| 307 | static inline uint32_t |
| 308 | hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, |
| 309 | uint8_t *rssi_info_tlv) |
| 310 | { |
| 311 | HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) |
| 312 | return 0; |
| 313 | } |
| 314 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 315 | /** |
| 316 | * hal_rx_status_get_tlv_info() - process receive info TLV |
| 317 | * @rx_tlv_hdr: pointer to TLV header |
| 318 | * @ppdu_info: pointer to ppdu_info |
| 319 | * |
| 320 | * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv |
| 321 | */ |
| 322 | static inline uint32_t |
| 323 | hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo, |
| 324 | void *halsoc) |
| 325 | { |
| 326 | struct hal_soc *hal = (struct hal_soc *)halsoc; |
| 327 | uint32_t tlv_tag, user_id, tlv_len, value; |
| 328 | uint8_t group_id = 0; |
| 329 | uint8_t he_dcm = 0; |
| 330 | uint8_t he_stbc = 0; |
| 331 | uint16_t he_gi = 0; |
| 332 | uint16_t he_ltf = 0; |
| 333 | void *rx_tlv; |
| 334 | bool unhandled = false; |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 335 | struct mon_rx_user_status *mon_rx_user_status; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 336 | struct hal_rx_ppdu_info *ppdu_info = |
| 337 | (struct hal_rx_ppdu_info *)ppduinfo; |
| 338 | |
| 339 | tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); |
| 340 | user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); |
| 341 | tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); |
| 342 | |
| 343 | rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 344 | |
| 345 | qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
| 346 | rx_tlv, tlv_len); |
| 347 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 348 | switch (tlv_tag) { |
| 349 | |
| 350 | case WIFIRX_PPDU_START_E: |
| 351 | ppdu_info->com_info.ppdu_id = |
| 352 | HAL_RX_GET(rx_tlv, RX_PPDU_START_0, |
| 353 | PHY_PPDU_ID); |
| 354 | /* channel number is set in PHY meta data */ |
| 355 | ppdu_info->rx_status.chan_num = |
| 356 | HAL_RX_GET(rx_tlv, RX_PPDU_START_1, |
| 357 | SW_PHY_META_DATA); |
| 358 | ppdu_info->com_info.ppdu_timestamp = |
| 359 | HAL_RX_GET(rx_tlv, RX_PPDU_START_2, |
| 360 | PPDU_START_TIMESTAMP); |
Adil Saeed Musthafa | ae6a73d | 2018-10-30 16:24:18 -0700 | [diff] [blame] | 361 | ppdu_info->rx_status.ppdu_timestamp = |
| 362 | ppdu_info->com_info.ppdu_timestamp; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 363 | ppdu_info->rx_state = HAL_RX_MON_PPDU_START; |
| 364 | break; |
| 365 | |
| 366 | case WIFIRX_PPDU_START_USER_INFO_E: |
| 367 | break; |
| 368 | |
| 369 | case WIFIRX_PPDU_END_E: |
| 370 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
| 371 | "[%s][%d] ppdu_end_e len=%d", |
| 372 | __func__, __LINE__, tlv_len); |
| 373 | /* This is followed by sub-TLVs of PPDU_END */ |
| 374 | ppdu_info->rx_state = HAL_RX_MON_PPDU_END; |
| 375 | break; |
| 376 | |
| 377 | case WIFIRXPCU_PPDU_END_INFO_E: |
| 378 | ppdu_info->rx_status.tsft = |
| 379 | HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, |
| 380 | WB_TIMESTAMP_UPPER_32); |
| 381 | ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | |
| 382 | HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, |
| 383 | WB_TIMESTAMP_LOWER_32); |
| 384 | ppdu_info->rx_status.duration = |
| 385 | HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, |
| 386 | RX_PPDU_DURATION); |
| 387 | break; |
| 388 | |
| 389 | case WIFIRX_PPDU_END_USER_STATS_E: |
| 390 | { |
| 391 | unsigned long tid = 0; |
| 392 | uint16_t seq = 0; |
| 393 | |
| 394 | ppdu_info->rx_status.ast_index = |
| 395 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, |
| 396 | AST_INDEX); |
| 397 | |
| 398 | tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, |
| 399 | RECEIVED_QOS_DATA_TID_BITMAP); |
| 400 | ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8); |
| 401 | |
| 402 | if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) |
| 403 | ppdu_info->rx_status.tid = HAL_TID_INVALID; |
| 404 | |
| 405 | ppdu_info->rx_status.tcp_msdu_count = |
| 406 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, |
| 407 | TCP_MSDU_COUNT) + |
| 408 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, |
| 409 | TCP_ACK_MSDU_COUNT); |
| 410 | ppdu_info->rx_status.udp_msdu_count = |
| 411 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, |
| 412 | UDP_MSDU_COUNT); |
| 413 | ppdu_info->rx_status.other_msdu_count = |
| 414 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, |
| 415 | OTHER_MSDU_COUNT); |
| 416 | |
| 417 | ppdu_info->rx_status.frame_control_info_valid = |
| 418 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, |
Anish Nataraj | eb30aa7 | 2018-09-20 16:34:01 +0530 | [diff] [blame] | 419 | FRAME_CONTROL_INFO_VALID); |
| 420 | |
| 421 | if (ppdu_info->rx_status.frame_control_info_valid) |
| 422 | ppdu_info->rx_status.frame_control = |
| 423 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, |
| 424 | FRAME_CONTROL_FIELD); |
| 425 | |
| 426 | ppdu_info->rx_status.data_sequence_control_info_valid = |
| 427 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, |
| 428 | DATA_SEQUENCE_CONTROL_INFO_VALID); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 429 | |
| 430 | seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, |
Anish Nataraj | eb30aa7 | 2018-09-20 16:34:01 +0530 | [diff] [blame] | 431 | FIRST_DATA_SEQ_CTRL); |
| 432 | if (ppdu_info->rx_status.data_sequence_control_info_valid) |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 433 | ppdu_info->rx_status.first_data_seq_ctrl = seq; |
| 434 | |
| 435 | ppdu_info->rx_status.preamble_type = |
| 436 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, |
| 437 | HT_CONTROL_FIELD_PKT_TYPE); |
| 438 | switch (ppdu_info->rx_status.preamble_type) { |
| 439 | case HAL_RX_PKT_TYPE_11N: |
| 440 | ppdu_info->rx_status.ht_flags = 1; |
| 441 | ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; |
| 442 | break; |
| 443 | case HAL_RX_PKT_TYPE_11AC: |
| 444 | ppdu_info->rx_status.vht_flags = 1; |
| 445 | break; |
| 446 | case HAL_RX_PKT_TYPE_11AX: |
| 447 | ppdu_info->rx_status.he_flags = 1; |
| 448 | break; |
| 449 | default: |
| 450 | break; |
| 451 | } |
Kai Chen | e0dd94d | 2019-06-07 13:10:49 -0700 | [diff] [blame] | 452 | if (user_id < HAL_MAX_UL_MU_USERS) { |
| 453 | mon_rx_user_status = |
| 454 | &ppdu_info->rx_user_status[user_id]; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 455 | |
Kai Chen | e0dd94d | 2019-06-07 13:10:49 -0700 | [diff] [blame] | 456 | mon_rx_user_status->mcs = |
| 457 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, |
| 458 | MCS); |
| 459 | mon_rx_user_status->nss = |
| 460 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_1, |
| 461 | NSS); |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 462 | |
Kai Chen | e0dd94d | 2019-06-07 13:10:49 -0700 | [diff] [blame] | 463 | hal_rx_handle_ofdma_info(rx_tlv, mon_rx_user_status); |
| 464 | } |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 465 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 466 | ppdu_info->com_info.mpdu_cnt_fcs_ok = |
| 467 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, |
| 468 | MPDU_CNT_FCS_OK); |
| 469 | ppdu_info->com_info.mpdu_cnt_fcs_err = |
| 470 | HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, |
| 471 | MPDU_CNT_FCS_ERR); |
| 472 | if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | |
| 473 | ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) |
| 474 | ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; |
| 475 | else |
| 476 | ppdu_info->rx_status.rs_flags &= |
| 477 | (~IEEE80211_AMPDU_FLAG); |
| 478 | break; |
| 479 | } |
| 480 | |
| 481 | case WIFIRX_PPDU_END_USER_STATS_EXT_E: |
| 482 | break; |
| 483 | |
| 484 | case WIFIRX_PPDU_END_STATUS_DONE_E: |
| 485 | return HAL_TLV_STATUS_PPDU_DONE; |
| 486 | |
| 487 | case WIFIDUMMY_E: |
| 488 | return HAL_TLV_STATUS_BUF_DONE; |
| 489 | |
| 490 | case WIFIPHYRX_HT_SIG_E: |
| 491 | { |
| 492 | uint8_t *ht_sig_info = (uint8_t *)rx_tlv + |
| 493 | HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, |
| 494 | HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); |
| 495 | value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, |
| 496 | FEC_CODING); |
| 497 | ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? |
| 498 | 1 : 0; |
| 499 | ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, |
| 500 | HT_SIG_INFO_0, MCS); |
Keyur Parekh | f72cbe5 | 2018-11-15 15:56:07 -0800 | [diff] [blame] | 501 | ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 502 | ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, |
| 503 | HT_SIG_INFO_0, CBW); |
| 504 | ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, |
| 505 | HT_SIG_INFO_1, SHORT_GI); |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 506 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; |
Keyur Parekh | f72cbe5 | 2018-11-15 15:56:07 -0800 | [diff] [blame] | 507 | ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> |
| 508 | HT_SIG_SU_NSS_SHIFT) + 1; |
| 509 | ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 510 | break; |
| 511 | } |
| 512 | |
| 513 | case WIFIPHYRX_L_SIG_B_E: |
| 514 | { |
| 515 | uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + |
| 516 | HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, |
| 517 | L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); |
| 518 | |
| 519 | value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); |
Adil Saeed Musthafa | ae6a73d | 2018-10-30 16:24:18 -0700 | [diff] [blame] | 520 | ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 521 | switch (value) { |
| 522 | case 1: |
| 523 | ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 524 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 525 | break; |
| 526 | case 2: |
| 527 | ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 528 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 529 | break; |
| 530 | case 3: |
| 531 | ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 532 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 533 | break; |
| 534 | case 4: |
| 535 | ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 536 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 537 | break; |
| 538 | case 5: |
| 539 | ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 540 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 541 | break; |
| 542 | case 6: |
| 543 | ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 544 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 545 | break; |
| 546 | case 7: |
| 547 | ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 548 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 549 | break; |
| 550 | default: |
| 551 | break; |
| 552 | } |
| 553 | ppdu_info->rx_status.cck_flag = 1; |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 554 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 555 | break; |
| 556 | } |
| 557 | |
| 558 | case WIFIPHYRX_L_SIG_A_E: |
| 559 | { |
| 560 | uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + |
| 561 | HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, |
| 562 | L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); |
| 563 | |
| 564 | value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); |
Adil Saeed Musthafa | ae6a73d | 2018-10-30 16:24:18 -0700 | [diff] [blame] | 565 | ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 566 | switch (value) { |
| 567 | case 8: |
| 568 | ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 569 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 570 | break; |
| 571 | case 9: |
| 572 | ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 573 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 574 | break; |
| 575 | case 10: |
| 576 | ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 577 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 578 | break; |
| 579 | case 11: |
| 580 | ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 581 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 582 | break; |
| 583 | case 12: |
| 584 | ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 585 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 586 | break; |
| 587 | case 13: |
| 588 | ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 589 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 590 | break; |
| 591 | case 14: |
| 592 | ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 593 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 594 | break; |
| 595 | case 15: |
| 596 | ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; |
Keyur Parekh | 76eadf4 | 2018-08-23 12:00:20 -0700 | [diff] [blame] | 597 | ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 598 | break; |
| 599 | default: |
| 600 | break; |
| 601 | } |
| 602 | ppdu_info->rx_status.ofdm_flag = 1; |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 603 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 604 | break; |
| 605 | } |
| 606 | |
| 607 | case WIFIPHYRX_VHT_SIG_A_E: |
| 608 | { |
| 609 | uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + |
| 610 | HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, |
| 611 | VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); |
| 612 | |
| 613 | value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, |
| 614 | SU_MU_CODING); |
| 615 | ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? |
| 616 | 1 : 0; |
| 617 | group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID); |
| 618 | ppdu_info->rx_status.vht_flag_values5 = group_id; |
| 619 | ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, |
| 620 | VHT_SIG_A_INFO_1, MCS); |
| 621 | ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, |
| 622 | VHT_SIG_A_INFO_1, GI_SETTING); |
| 623 | |
| 624 | switch (hal->target_type) { |
| 625 | case TARGET_TYPE_QCA8074: |
| 626 | case TARGET_TYPE_QCA8074V2: |
Basamma Yakkanahalli | 5f7cfd4 | 2018-11-02 15:52:37 +0530 | [diff] [blame] | 627 | case TARGET_TYPE_QCA6018: |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 628 | ppdu_info->rx_status.is_stbc = |
| 629 | HAL_RX_GET(vht_sig_a_info, |
| 630 | VHT_SIG_A_INFO_0, STBC); |
| 631 | value = HAL_RX_GET(vht_sig_a_info, |
| 632 | VHT_SIG_A_INFO_0, N_STS); |
| 633 | if (ppdu_info->rx_status.is_stbc && (value > 0)) |
| 634 | value = ((value + 1) >> 1) - 1; |
| 635 | ppdu_info->rx_status.nss = |
| 636 | ((value & VHT_SIG_SU_NSS_MASK) + 1); |
| 637 | |
| 638 | break; |
| 639 | case TARGET_TYPE_QCA6290: |
| 640 | #if !defined(QCA_WIFI_QCA6290_11AX) |
| 641 | ppdu_info->rx_status.is_stbc = |
| 642 | HAL_RX_GET(vht_sig_a_info, |
| 643 | VHT_SIG_A_INFO_0, STBC); |
| 644 | value = HAL_RX_GET(vht_sig_a_info, |
| 645 | VHT_SIG_A_INFO_0, N_STS); |
| 646 | if (ppdu_info->rx_status.is_stbc && (value > 0)) |
| 647 | value = ((value + 1) >> 1) - 1; |
| 648 | ppdu_info->rx_status.nss = |
| 649 | ((value & VHT_SIG_SU_NSS_MASK) + 1); |
| 650 | #else |
| 651 | ppdu_info->rx_status.nss = 0; |
| 652 | #endif |
| 653 | break; |
| 654 | #ifdef QCA_WIFI_QCA6390 |
| 655 | case TARGET_TYPE_QCA6390: |
| 656 | ppdu_info->rx_status.nss = 0; |
| 657 | break; |
| 658 | #endif |
| 659 | default: |
| 660 | break; |
| 661 | } |
| 662 | ppdu_info->rx_status.vht_flag_values3[0] = |
| 663 | (((ppdu_info->rx_status.mcs) << 4) |
| 664 | | ppdu_info->rx_status.nss); |
| 665 | ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, |
| 666 | VHT_SIG_A_INFO_0, BANDWIDTH); |
| 667 | ppdu_info->rx_status.vht_flag_values2 = |
| 668 | ppdu_info->rx_status.bw; |
| 669 | ppdu_info->rx_status.vht_flag_values4 = |
| 670 | HAL_RX_GET(vht_sig_a_info, |
| 671 | VHT_SIG_A_INFO_1, SU_MU_CODING); |
| 672 | |
| 673 | ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, |
| 674 | VHT_SIG_A_INFO_1, BEAMFORMED); |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 675 | if (group_id == 0 || group_id == 63) |
| 676 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; |
| 677 | else |
| 678 | ppdu_info->rx_status.reception_type = |
| 679 | HAL_RX_TYPE_MU_MIMO; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 680 | |
| 681 | break; |
| 682 | } |
| 683 | case WIFIPHYRX_HE_SIG_A_SU_E: |
| 684 | { |
| 685 | uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + |
| 686 | HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, |
| 687 | HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); |
| 688 | ppdu_info->rx_status.he_flags = 1; |
| 689 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, |
| 690 | FORMAT_INDICATION); |
| 691 | if (value == 0) { |
| 692 | ppdu_info->rx_status.he_data1 = |
| 693 | QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; |
| 694 | } else { |
| 695 | ppdu_info->rx_status.he_data1 = |
| 696 | QDF_MON_STATUS_HE_SU_FORMAT_TYPE; |
| 697 | } |
| 698 | |
| 699 | /* data1 */ |
| 700 | ppdu_info->rx_status.he_data1 |= |
| 701 | QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | |
| 702 | QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | |
| 703 | QDF_MON_STATUS_HE_DL_UL_KNOWN | |
| 704 | QDF_MON_STATUS_HE_MCS_KNOWN | |
| 705 | QDF_MON_STATUS_HE_DCM_KNOWN | |
| 706 | QDF_MON_STATUS_HE_CODING_KNOWN | |
| 707 | QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | |
| 708 | QDF_MON_STATUS_HE_STBC_KNOWN | |
| 709 | QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | |
| 710 | QDF_MON_STATUS_HE_DOPPLER_KNOWN; |
| 711 | |
| 712 | /* data2 */ |
| 713 | ppdu_info->rx_status.he_data2 = |
| 714 | QDF_MON_STATUS_HE_GI_KNOWN; |
| 715 | ppdu_info->rx_status.he_data2 |= |
| 716 | QDF_MON_STATUS_TXBF_KNOWN | |
| 717 | QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | |
| 718 | QDF_MON_STATUS_TXOP_KNOWN | |
| 719 | QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | |
| 720 | QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | |
| 721 | QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; |
| 722 | |
| 723 | /* data3 */ |
| 724 | value = HAL_RX_GET(he_sig_a_su_info, |
| 725 | HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); |
| 726 | ppdu_info->rx_status.he_data3 = value; |
| 727 | value = HAL_RX_GET(he_sig_a_su_info, |
| 728 | HE_SIG_A_SU_INFO_0, BEAM_CHANGE); |
| 729 | value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; |
| 730 | ppdu_info->rx_status.he_data3 |= value; |
| 731 | value = HAL_RX_GET(he_sig_a_su_info, |
| 732 | HE_SIG_A_SU_INFO_0, DL_UL_FLAG); |
| 733 | value = value << QDF_MON_STATUS_DL_UL_SHIFT; |
| 734 | ppdu_info->rx_status.he_data3 |= value; |
| 735 | |
| 736 | value = HAL_RX_GET(he_sig_a_su_info, |
| 737 | HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); |
| 738 | ppdu_info->rx_status.mcs = value; |
| 739 | value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; |
| 740 | ppdu_info->rx_status.he_data3 |= value; |
| 741 | |
| 742 | value = HAL_RX_GET(he_sig_a_su_info, |
| 743 | HE_SIG_A_SU_INFO_0, DCM); |
| 744 | he_dcm = value; |
| 745 | value = value << QDF_MON_STATUS_DCM_SHIFT; |
| 746 | ppdu_info->rx_status.he_data3 |= value; |
| 747 | value = HAL_RX_GET(he_sig_a_su_info, |
| 748 | HE_SIG_A_SU_INFO_1, CODING); |
Keyur Parekh | 25ee316 | 2019-02-08 23:01:39 -0800 | [diff] [blame] | 749 | ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? |
| 750 | 1 : 0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 751 | value = value << QDF_MON_STATUS_CODING_SHIFT; |
| 752 | ppdu_info->rx_status.he_data3 |= value; |
| 753 | value = HAL_RX_GET(he_sig_a_su_info, |
| 754 | HE_SIG_A_SU_INFO_1, |
| 755 | LDPC_EXTRA_SYMBOL); |
| 756 | value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; |
| 757 | ppdu_info->rx_status.he_data3 |= value; |
| 758 | value = HAL_RX_GET(he_sig_a_su_info, |
| 759 | HE_SIG_A_SU_INFO_1, STBC); |
| 760 | he_stbc = value; |
| 761 | value = value << QDF_MON_STATUS_STBC_SHIFT; |
| 762 | ppdu_info->rx_status.he_data3 |= value; |
| 763 | |
| 764 | /* data4 */ |
| 765 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, |
| 766 | SPATIAL_REUSE); |
| 767 | ppdu_info->rx_status.he_data4 = value; |
| 768 | |
| 769 | /* data5 */ |
| 770 | value = HAL_RX_GET(he_sig_a_su_info, |
| 771 | HE_SIG_A_SU_INFO_0, TRANSMIT_BW); |
| 772 | ppdu_info->rx_status.he_data5 = value; |
| 773 | ppdu_info->rx_status.bw = value; |
| 774 | value = HAL_RX_GET(he_sig_a_su_info, |
| 775 | HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); |
| 776 | switch (value) { |
| 777 | case 0: |
| 778 | he_gi = HE_GI_0_8; |
| 779 | he_ltf = HE_LTF_1_X; |
| 780 | break; |
| 781 | case 1: |
| 782 | he_gi = HE_GI_0_8; |
| 783 | he_ltf = HE_LTF_2_X; |
| 784 | break; |
| 785 | case 2: |
| 786 | he_gi = HE_GI_1_6; |
| 787 | he_ltf = HE_LTF_2_X; |
| 788 | break; |
| 789 | case 3: |
| 790 | if (he_dcm && he_stbc) { |
| 791 | he_gi = HE_GI_0_8; |
| 792 | he_ltf = HE_LTF_4_X; |
| 793 | } else { |
| 794 | he_gi = HE_GI_3_2; |
| 795 | he_ltf = HE_LTF_4_X; |
| 796 | } |
| 797 | break; |
| 798 | } |
| 799 | ppdu_info->rx_status.sgi = he_gi; |
| 800 | value = he_gi << QDF_MON_STATUS_GI_SHIFT; |
| 801 | ppdu_info->rx_status.he_data5 |= value; |
| 802 | value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; |
Keyur Parekh | 44d8f8f | 2019-03-12 12:39:41 -0700 | [diff] [blame] | 803 | ppdu_info->rx_status.ltf_size = he_ltf; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 804 | ppdu_info->rx_status.he_data5 |= value; |
| 805 | |
| 806 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); |
| 807 | value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); |
| 808 | ppdu_info->rx_status.he_data5 |= value; |
| 809 | |
| 810 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, |
| 811 | PACKET_EXTENSION_A_FACTOR); |
| 812 | value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; |
| 813 | ppdu_info->rx_status.he_data5 |= value; |
| 814 | |
| 815 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); |
| 816 | value = value << QDF_MON_STATUS_TXBF_SHIFT; |
| 817 | ppdu_info->rx_status.he_data5 |= value; |
| 818 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, |
| 819 | PACKET_EXTENSION_PE_DISAMBIGUITY); |
| 820 | value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; |
| 821 | ppdu_info->rx_status.he_data5 |= value; |
| 822 | |
| 823 | /* data6 */ |
| 824 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); |
| 825 | value++; |
| 826 | ppdu_info->rx_status.nss = value; |
| 827 | ppdu_info->rx_status.he_data6 = value; |
| 828 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, |
| 829 | DOPPLER_INDICATION); |
| 830 | value = value << QDF_MON_STATUS_DOPPLER_SHIFT; |
| 831 | ppdu_info->rx_status.he_data6 |= value; |
| 832 | value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, |
| 833 | TXOP_DURATION); |
| 834 | value = value << QDF_MON_STATUS_TXOP_SHIFT; |
| 835 | ppdu_info->rx_status.he_data6 |= value; |
| 836 | |
| 837 | ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, |
| 838 | HE_SIG_A_SU_INFO_1, TXBF); |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 839 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 840 | break; |
| 841 | } |
| 842 | case WIFIPHYRX_HE_SIG_A_MU_DL_E: |
| 843 | { |
| 844 | uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + |
| 845 | HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, |
| 846 | HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); |
| 847 | |
| 848 | ppdu_info->rx_status.he_mu_flags = 1; |
| 849 | |
| 850 | /* HE Flags */ |
| 851 | /*data1*/ |
| 852 | ppdu_info->rx_status.he_data1 = |
| 853 | QDF_MON_STATUS_HE_MU_FORMAT_TYPE; |
| 854 | ppdu_info->rx_status.he_data1 |= |
| 855 | QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | |
| 856 | QDF_MON_STATUS_HE_DL_UL_KNOWN | |
| 857 | QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | |
| 858 | QDF_MON_STATUS_HE_STBC_KNOWN | |
| 859 | QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | |
| 860 | QDF_MON_STATUS_HE_DOPPLER_KNOWN; |
| 861 | |
| 862 | /* data2 */ |
| 863 | ppdu_info->rx_status.he_data2 = |
| 864 | QDF_MON_STATUS_HE_GI_KNOWN; |
| 865 | ppdu_info->rx_status.he_data2 |= |
| 866 | QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | |
| 867 | QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | |
| 868 | QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | |
| 869 | QDF_MON_STATUS_TXOP_KNOWN | |
| 870 | QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; |
| 871 | |
| 872 | /*data3*/ |
| 873 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 874 | HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); |
| 875 | ppdu_info->rx_status.he_data3 = value; |
| 876 | |
| 877 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 878 | HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); |
| 879 | value = value << QDF_MON_STATUS_DL_UL_SHIFT; |
| 880 | ppdu_info->rx_status.he_data3 |= value; |
| 881 | |
| 882 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 883 | HE_SIG_A_MU_DL_INFO_1, |
| 884 | LDPC_EXTRA_SYMBOL); |
| 885 | value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; |
| 886 | ppdu_info->rx_status.he_data3 |= value; |
| 887 | |
| 888 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 889 | HE_SIG_A_MU_DL_INFO_1, STBC); |
| 890 | he_stbc = value; |
| 891 | value = value << QDF_MON_STATUS_STBC_SHIFT; |
| 892 | ppdu_info->rx_status.he_data3 |= value; |
| 893 | |
| 894 | /*data4*/ |
| 895 | value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, |
| 896 | SPATIAL_REUSE); |
| 897 | ppdu_info->rx_status.he_data4 = value; |
| 898 | |
| 899 | /*data5*/ |
| 900 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 901 | HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); |
| 902 | ppdu_info->rx_status.he_data5 = value; |
| 903 | ppdu_info->rx_status.bw = value; |
| 904 | |
| 905 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 906 | HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); |
| 907 | switch (value) { |
| 908 | case 0: |
| 909 | he_gi = HE_GI_0_8; |
| 910 | he_ltf = HE_LTF_4_X; |
| 911 | break; |
| 912 | case 1: |
| 913 | he_gi = HE_GI_0_8; |
| 914 | he_ltf = HE_LTF_2_X; |
| 915 | break; |
| 916 | case 2: |
| 917 | he_gi = HE_GI_1_6; |
| 918 | he_ltf = HE_LTF_2_X; |
| 919 | break; |
| 920 | case 3: |
| 921 | he_gi = HE_GI_3_2; |
| 922 | he_ltf = HE_LTF_4_X; |
| 923 | break; |
| 924 | } |
| 925 | ppdu_info->rx_status.sgi = he_gi; |
| 926 | value = he_gi << QDF_MON_STATUS_GI_SHIFT; |
| 927 | ppdu_info->rx_status.he_data5 |= value; |
| 928 | |
| 929 | value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; |
| 930 | ppdu_info->rx_status.he_data5 |= value; |
| 931 | |
| 932 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 933 | HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); |
| 934 | value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); |
| 935 | ppdu_info->rx_status.he_data5 |= value; |
| 936 | |
| 937 | value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, |
| 938 | PACKET_EXTENSION_A_FACTOR); |
| 939 | value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; |
| 940 | ppdu_info->rx_status.he_data5 |= value; |
| 941 | |
| 942 | |
| 943 | value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, |
| 944 | PACKET_EXTENSION_PE_DISAMBIGUITY); |
| 945 | value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; |
| 946 | ppdu_info->rx_status.he_data5 |= value; |
| 947 | |
| 948 | /*data6*/ |
| 949 | value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, |
| 950 | DOPPLER_INDICATION); |
| 951 | value = value << QDF_MON_STATUS_DOPPLER_SHIFT; |
| 952 | ppdu_info->rx_status.he_data6 |= value; |
| 953 | |
| 954 | value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, |
| 955 | TXOP_DURATION); |
| 956 | value = value << QDF_MON_STATUS_TXOP_SHIFT; |
| 957 | ppdu_info->rx_status.he_data6 |= value; |
| 958 | |
| 959 | /* HE-MU Flags */ |
| 960 | /* HE-MU-flags1 */ |
| 961 | ppdu_info->rx_status.he_flags1 = |
| 962 | QDF_MON_STATUS_SIG_B_MCS_KNOWN | |
| 963 | QDF_MON_STATUS_SIG_B_DCM_KNOWN | |
| 964 | QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | |
| 965 | QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | |
| 966 | QDF_MON_STATUS_RU_0_KNOWN; |
| 967 | |
| 968 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 969 | HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); |
| 970 | ppdu_info->rx_status.he_flags1 |= value; |
| 971 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 972 | HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); |
| 973 | value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; |
| 974 | ppdu_info->rx_status.he_flags1 |= value; |
| 975 | |
| 976 | /* HE-MU-flags2 */ |
| 977 | ppdu_info->rx_status.he_flags2 = |
| 978 | QDF_MON_STATUS_BW_KNOWN; |
| 979 | |
| 980 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 981 | HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); |
| 982 | ppdu_info->rx_status.he_flags2 |= value; |
| 983 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 984 | HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); |
| 985 | value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; |
| 986 | ppdu_info->rx_status.he_flags2 |= value; |
| 987 | value = HAL_RX_GET(he_sig_a_mu_dl_info, |
| 988 | HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); |
| 989 | value = value - 1; |
| 990 | value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; |
| 991 | ppdu_info->rx_status.he_flags2 |= value; |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 992 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 993 | break; |
| 994 | } |
| 995 | case WIFIPHYRX_HE_SIG_B1_MU_E: |
| 996 | { |
| 997 | |
| 998 | uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + |
| 999 | HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, |
| 1000 | HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); |
| 1001 | |
| 1002 | ppdu_info->rx_status.he_sig_b_common_known |= |
| 1003 | QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; |
| 1004 | /* TODO: Check on the availability of other fields in |
| 1005 | * sig_b_common |
| 1006 | */ |
| 1007 | |
| 1008 | value = HAL_RX_GET(he_sig_b1_mu_info, |
| 1009 | HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); |
| 1010 | ppdu_info->rx_status.he_RU[0] = value; |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 1011 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1012 | break; |
| 1013 | } |
| 1014 | case WIFIPHYRX_HE_SIG_B2_MU_E: |
| 1015 | { |
| 1016 | uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + |
| 1017 | HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, |
| 1018 | HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); |
| 1019 | /* |
| 1020 | * Not all "HE" fields can be updated from |
| 1021 | * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E |
| 1022 | * to populate rest of the "HE" fields for MU scenarios. |
| 1023 | */ |
| 1024 | |
| 1025 | /* HE-data1 */ |
| 1026 | ppdu_info->rx_status.he_data1 |= |
| 1027 | QDF_MON_STATUS_HE_MCS_KNOWN | |
| 1028 | QDF_MON_STATUS_HE_CODING_KNOWN; |
| 1029 | |
| 1030 | /* HE-data2 */ |
| 1031 | |
| 1032 | /* HE-data3 */ |
| 1033 | value = HAL_RX_GET(he_sig_b2_mu_info, |
| 1034 | HE_SIG_B2_MU_INFO_0, STA_MCS); |
| 1035 | ppdu_info->rx_status.mcs = value; |
| 1036 | value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; |
| 1037 | ppdu_info->rx_status.he_data3 |= value; |
| 1038 | |
| 1039 | |
| 1040 | value = HAL_RX_GET(he_sig_b2_mu_info, |
| 1041 | HE_SIG_B2_MU_INFO_0, STA_CODING); |
| 1042 | value = value << QDF_MON_STATUS_CODING_SHIFT; |
| 1043 | ppdu_info->rx_status.he_data3 |= value; |
| 1044 | |
| 1045 | /* HE-data4 */ |
| 1046 | value = HAL_RX_GET(he_sig_b2_mu_info, |
| 1047 | HE_SIG_B2_MU_INFO_0, STA_ID); |
| 1048 | value = value << QDF_MON_STATUS_STA_ID_SHIFT; |
| 1049 | ppdu_info->rx_status.he_data4 |= value; |
| 1050 | |
| 1051 | /* HE-data5 */ |
| 1052 | |
| 1053 | /* HE-data6 */ |
| 1054 | value = HAL_RX_GET(he_sig_b2_mu_info, |
| 1055 | HE_SIG_B2_MU_INFO_0, NSTS); |
| 1056 | /* value n indicates n+1 spatial streams */ |
| 1057 | value++; |
| 1058 | ppdu_info->rx_status.nss = value; |
| 1059 | ppdu_info->rx_status.he_data6 |= value; |
| 1060 | |
| 1061 | break; |
| 1062 | |
| 1063 | } |
| 1064 | case WIFIPHYRX_HE_SIG_B2_OFDMA_E: |
| 1065 | { |
| 1066 | uint8_t *he_sig_b2_ofdma_info = |
| 1067 | (uint8_t *)rx_tlv + |
| 1068 | HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, |
| 1069 | HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); |
| 1070 | |
| 1071 | /* |
| 1072 | * Not all "HE" fields can be updated from |
| 1073 | * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E |
| 1074 | * to populate rest of "HE" fields for MU OFDMA scenarios. |
| 1075 | */ |
| 1076 | |
| 1077 | /* HE-data1 */ |
| 1078 | ppdu_info->rx_status.he_data1 |= |
| 1079 | QDF_MON_STATUS_HE_MCS_KNOWN | |
| 1080 | QDF_MON_STATUS_HE_DCM_KNOWN | |
| 1081 | QDF_MON_STATUS_HE_CODING_KNOWN; |
| 1082 | |
| 1083 | /* HE-data2 */ |
| 1084 | ppdu_info->rx_status.he_data2 |= |
| 1085 | QDF_MON_STATUS_TXBF_KNOWN; |
| 1086 | |
| 1087 | /* HE-data3 */ |
| 1088 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1089 | HE_SIG_B2_OFDMA_INFO_0, STA_MCS); |
| 1090 | ppdu_info->rx_status.mcs = value; |
| 1091 | value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; |
| 1092 | ppdu_info->rx_status.he_data3 |= value; |
| 1093 | |
| 1094 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1095 | HE_SIG_B2_OFDMA_INFO_0, STA_DCM); |
| 1096 | he_dcm = value; |
| 1097 | value = value << QDF_MON_STATUS_DCM_SHIFT; |
| 1098 | ppdu_info->rx_status.he_data3 |= value; |
| 1099 | |
| 1100 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1101 | HE_SIG_B2_OFDMA_INFO_0, STA_CODING); |
| 1102 | value = value << QDF_MON_STATUS_CODING_SHIFT; |
| 1103 | ppdu_info->rx_status.he_data3 |= value; |
| 1104 | |
| 1105 | /* HE-data4 */ |
| 1106 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1107 | HE_SIG_B2_OFDMA_INFO_0, STA_ID); |
| 1108 | value = value << QDF_MON_STATUS_STA_ID_SHIFT; |
| 1109 | ppdu_info->rx_status.he_data4 |= value; |
| 1110 | |
| 1111 | /* HE-data5 */ |
| 1112 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1113 | HE_SIG_B2_OFDMA_INFO_0, TXBF); |
| 1114 | value = value << QDF_MON_STATUS_TXBF_SHIFT; |
| 1115 | ppdu_info->rx_status.he_data5 |= value; |
| 1116 | |
| 1117 | /* HE-data6 */ |
| 1118 | value = HAL_RX_GET(he_sig_b2_ofdma_info, |
| 1119 | HE_SIG_B2_OFDMA_INFO_0, NSTS); |
| 1120 | /* value n indicates n+1 spatial streams */ |
| 1121 | value++; |
| 1122 | ppdu_info->rx_status.nss = value; |
| 1123 | ppdu_info->rx_status.he_data6 |= value; |
Keyur Parekh | ba75857 | 2018-08-06 15:00:40 -0700 | [diff] [blame] | 1124 | ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1125 | break; |
| 1126 | } |
| 1127 | case WIFIPHYRX_RSSI_LEGACY_E: |
| 1128 | { |
chenguo | 33f505a | 2018-10-15 17:17:46 +0800 | [diff] [blame] | 1129 | uint8_t reception_type; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1130 | uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1131 | HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, |
| 1132 | RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1133 | |
| 1134 | ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, |
| 1135 | PHYRX_RSSI_LEGACY_35, RSSI_COMB); |
| 1136 | ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); |
| 1137 | ppdu_info->rx_status.he_re = 0; |
| 1138 | |
chenguo | 33f505a | 2018-10-15 17:17:46 +0800 | [diff] [blame] | 1139 | reception_type = HAL_RX_GET(rx_tlv, |
| 1140 | PHYRX_RSSI_LEGACY_0, |
| 1141 | RECEPTION_TYPE); |
| 1142 | switch (reception_type) { |
| 1143 | case QDF_RECEPTION_TYPE_ULOFMDA: |
| 1144 | ppdu_info->rx_status.ulofdma_flag = 1; |
| 1145 | ppdu_info->rx_status.he_data1 = |
| 1146 | QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; |
| 1147 | break; |
| 1148 | case QDF_RECEPTION_TYPE_ULMIMO: |
| 1149 | ppdu_info->rx_status.he_data1 = |
| 1150 | QDF_MON_STATUS_HE_MU_FORMAT_TYPE; |
| 1151 | break; |
| 1152 | default: |
| 1153 | break; |
| 1154 | } |
Amir Patel | 1d4ac98 | 2019-04-25 11:49:01 +0530 | [diff] [blame] | 1155 | hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1156 | value = HAL_RX_GET(rssi_info_tlv, |
| 1157 | RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1158 | ppdu_info->rx_status.rssi[0] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1159 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
| 1160 | "RSSI_PRI20_CHAIN0: %d\n", value); |
| 1161 | |
| 1162 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1163 | RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); |
| 1164 | ppdu_info->rx_status.rssi[1] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1165 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1166 | "RSSI_PRI20_CHAIN1: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1167 | |
| 1168 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1169 | RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); |
| 1170 | ppdu_info->rx_status.rssi[2] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1171 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1172 | "RSSI_PRI20_CHAIN2: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1173 | |
| 1174 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1175 | RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); |
| 1176 | ppdu_info->rx_status.rssi[3] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1177 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1178 | "RSSI_PRI20_CHAIN3: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1179 | |
| 1180 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1181 | RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); |
| 1182 | ppdu_info->rx_status.rssi[4] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1183 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1184 | "RSSI_PRI20_CHAIN4: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1185 | |
| 1186 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1187 | RECEIVE_RSSI_INFO_10, RSSI_PRI20_CHAIN5); |
| 1188 | ppdu_info->rx_status.rssi[5] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1189 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1190 | "RSSI_PRI20_CHAIN5: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1191 | |
| 1192 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1193 | RECEIVE_RSSI_INFO_12, RSSI_PRI20_CHAIN6); |
| 1194 | ppdu_info->rx_status.rssi[6] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1195 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1196 | "RSSI_PRI20_CHAIN1: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1197 | |
| 1198 | value = HAL_RX_GET(rssi_info_tlv, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1199 | RECEIVE_RSSI_INFO_14, RSSI_PRI20_CHAIN7); |
| 1200 | ppdu_info->rx_status.rssi[7] = value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1201 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1202 | "RSSI_PRI20_CHAIN7: %d\n", value); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1203 | break; |
| 1204 | } |
| 1205 | case WIFIPHYRX_OTHER_RECEIVE_INFO_E: |
| 1206 | hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, |
| 1207 | ppdu_info); |
| 1208 | break; |
| 1209 | case WIFIRX_HEADER_E: |
| 1210 | ppdu_info->msdu_info.first_msdu_payload = rx_tlv; |
| 1211 | ppdu_info->msdu_info.payload_len = tlv_len; |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1212 | ppdu_info->user_id = user_id; |
| 1213 | ppdu_info->hdr_len = tlv_len; |
| 1214 | ppdu_info->data = rx_tlv; |
| 1215 | ppdu_info->data += 4; |
| 1216 | return HAL_TLV_STATUS_HEADER; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1217 | case WIFIRX_MPDU_START_E: |
| 1218 | { |
| 1219 | uint8_t *rx_mpdu_start = |
| 1220 | (uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0, |
| 1221 | RX_MPDU_INFO_RX_MPDU_INFO_DETAILS); |
| 1222 | uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, |
| 1223 | PHY_PPDU_ID); |
sumedh baikady | 59a2d33 | 2018-05-22 01:50:38 -0700 | [diff] [blame] | 1224 | uint8_t filter_category = 0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1225 | |
| 1226 | ppdu_info->nac_info.fc_valid = |
| 1227 | HAL_RX_GET(rx_mpdu_start, |
| 1228 | RX_MPDU_INFO_2, |
| 1229 | MPDU_FRAME_CONTROL_VALID); |
| 1230 | |
| 1231 | ppdu_info->nac_info.to_ds_flag = |
| 1232 | HAL_RX_GET(rx_mpdu_start, |
| 1233 | RX_MPDU_INFO_2, |
| 1234 | TO_DS); |
| 1235 | |
Karunakar Dasineni | acc8b56 | 2019-05-07 07:00:24 -0700 | [diff] [blame] | 1236 | ppdu_info->nac_info.frame_control = |
| 1237 | HAL_RX_GET(rx_mpdu_start, |
| 1238 | RX_MPDU_INFO_14, |
| 1239 | MPDU_FRAME_CONTROL_FIELD); |
| 1240 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1241 | ppdu_info->nac_info.mac_addr2_valid = |
| 1242 | HAL_RX_GET(rx_mpdu_start, |
| 1243 | RX_MPDU_INFO_2, |
| 1244 | MAC_ADDR_AD2_VALID); |
| 1245 | |
| 1246 | *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = |
| 1247 | HAL_RX_GET(rx_mpdu_start, |
| 1248 | RX_MPDU_INFO_16, |
| 1249 | MAC_ADDR_AD2_15_0); |
| 1250 | |
| 1251 | *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = |
| 1252 | HAL_RX_GET(rx_mpdu_start, |
| 1253 | RX_MPDU_INFO_17, |
| 1254 | MAC_ADDR_AD2_47_16); |
| 1255 | |
| 1256 | if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { |
| 1257 | ppdu_info->rx_status.prev_ppdu_id = ppdu_id; |
| 1258 | ppdu_info->rx_status.ppdu_len = |
| 1259 | HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, |
| 1260 | MPDU_LENGTH); |
| 1261 | } else { |
| 1262 | ppdu_info->rx_status.ppdu_len += |
| 1263 | HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, |
| 1264 | MPDU_LENGTH); |
| 1265 | } |
sumedh baikady | 59a2d33 | 2018-05-22 01:50:38 -0700 | [diff] [blame] | 1266 | |
| 1267 | filter_category = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, |
| 1268 | RXPCU_MPDU_FILTER_IN_CATEGORY); |
Karunakar Dasineni | 142f9ba | 2019-03-19 23:04:59 -0700 | [diff] [blame] | 1269 | |
| 1270 | if (filter_category == 0) |
| 1271 | ppdu_info->rx_status.rxpcu_filter_pass = 1; |
| 1272 | else if (filter_category == 1) |
sumedh baikady | 59a2d33 | 2018-05-22 01:50:38 -0700 | [diff] [blame] | 1273 | ppdu_info->rx_status.monitor_direct_used = 1; |
Karunakar Dasineni | 142f9ba | 2019-03-19 23:04:59 -0700 | [diff] [blame] | 1274 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1275 | break; |
| 1276 | } |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 1277 | case WIFIRX_MPDU_END_E: |
| 1278 | ppdu_info->user_id = user_id; |
| 1279 | ppdu_info->fcs_err = |
| 1280 | HAL_RX_GET(rx_tlv, RX_MPDU_END_1, |
| 1281 | FCS_ERR); |
| 1282 | return HAL_TLV_STATUS_MPDU_END; |
Karunakar Dasineni | acc8b56 | 2019-05-07 07:00:24 -0700 | [diff] [blame] | 1283 | case WIFIRX_MSDU_END_E: |
| 1284 | ppdu_info->rx_msdu_info[user_id].cce_metadata = |
| 1285 | HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); |
| 1286 | return HAL_TLV_STATUS_MSDU_END; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1287 | case 0: |
| 1288 | return HAL_TLV_STATUS_PPDU_DONE; |
| 1289 | |
| 1290 | default: |
chenguo | f51e922 | 2018-04-20 14:34:25 +0800 | [diff] [blame] | 1291 | if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) |
| 1292 | unhandled = false; |
| 1293 | else |
| 1294 | unhandled = true; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1295 | break; |
| 1296 | } |
| 1297 | |
| 1298 | if (!unhandled) |
| 1299 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
| 1300 | "%s TLV type: %d, TLV len:%d %s", |
| 1301 | __func__, tlv_tag, tlv_len, |
| 1302 | unhandled == true ? "unhandled" : ""); |
| 1303 | |
| 1304 | qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, |
| 1305 | rx_tlv, tlv_len); |
| 1306 | |
| 1307 | return HAL_TLV_STATUS_PPDU_NOT_DONE; |
| 1308 | } |
| 1309 | /** |
| 1310 | * hal_reo_status_get_header_generic - Process reo desc info |
| 1311 | * @d - Pointer to reo descriptior |
| 1312 | * @b - tlv type info |
| 1313 | * @h1 - Pointer to hal_reo_status_header where info to be stored |
| 1314 | * |
| 1315 | * Return - none. |
| 1316 | * |
| 1317 | */ |
| 1318 | static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1) |
| 1319 | { |
| 1320 | |
| 1321 | uint32_t val1 = 0; |
| 1322 | struct hal_reo_status_header *h = |
| 1323 | (struct hal_reo_status_header *)h1; |
| 1324 | |
| 1325 | switch (b) { |
| 1326 | case HAL_REO_QUEUE_STATS_STATUS_TLV: |
| 1327 | val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, |
| 1328 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1329 | break; |
| 1330 | case HAL_REO_FLUSH_QUEUE_STATUS_TLV: |
| 1331 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, |
| 1332 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1333 | break; |
| 1334 | case HAL_REO_FLUSH_CACHE_STATUS_TLV: |
| 1335 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, |
| 1336 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1337 | break; |
| 1338 | case HAL_REO_UNBLK_CACHE_STATUS_TLV: |
| 1339 | val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, |
| 1340 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1341 | break; |
| 1342 | case HAL_REO_TIMOUT_LIST_STATUS_TLV: |
| 1343 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, |
| 1344 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1345 | break; |
| 1346 | case HAL_REO_DESC_THRES_STATUS_TLV: |
| 1347 | val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, |
| 1348 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1349 | break; |
| 1350 | case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: |
| 1351 | val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, |
| 1352 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 1353 | break; |
| 1354 | default: |
| 1355 | pr_err("ERROR: Unknown tlv\n"); |
| 1356 | break; |
| 1357 | } |
| 1358 | h->cmd_num = |
| 1359 | HAL_GET_FIELD( |
| 1360 | UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, |
| 1361 | val1); |
| 1362 | h->exec_time = |
| 1363 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, |
| 1364 | CMD_EXECUTION_TIME, val1); |
| 1365 | h->status = |
| 1366 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, |
| 1367 | REO_CMD_EXECUTION_STATUS, val1); |
| 1368 | switch (b) { |
| 1369 | case HAL_REO_QUEUE_STATS_STATUS_TLV: |
| 1370 | val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, |
| 1371 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1372 | break; |
| 1373 | case HAL_REO_FLUSH_QUEUE_STATUS_TLV: |
| 1374 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, |
| 1375 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1376 | break; |
| 1377 | case HAL_REO_FLUSH_CACHE_STATUS_TLV: |
| 1378 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, |
| 1379 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1380 | break; |
| 1381 | case HAL_REO_UNBLK_CACHE_STATUS_TLV: |
| 1382 | val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, |
| 1383 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1384 | break; |
| 1385 | case HAL_REO_TIMOUT_LIST_STATUS_TLV: |
| 1386 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, |
| 1387 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1388 | break; |
| 1389 | case HAL_REO_DESC_THRES_STATUS_TLV: |
| 1390 | val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, |
| 1391 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1392 | break; |
| 1393 | case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: |
| 1394 | val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, |
| 1395 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 1396 | break; |
| 1397 | default: |
| 1398 | pr_err("ERROR: Unknown tlv\n"); |
| 1399 | break; |
| 1400 | } |
| 1401 | h->tstamp = |
| 1402 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); |
| 1403 | } |
| 1404 | |
| 1405 | /** |
| 1406 | * hal_reo_setup - Initialize HW REO block |
| 1407 | * |
| 1408 | * @hal_soc: Opaque HAL SOC handle |
| 1409 | * @reo_params: parameters needed by HAL for REO config |
| 1410 | */ |
| 1411 | static void hal_reo_setup_generic(void *hal_soc, |
| 1412 | void *reoparams) |
| 1413 | { |
| 1414 | struct hal_soc *soc = (struct hal_soc *)hal_soc; |
| 1415 | uint32_t reg_val; |
| 1416 | struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; |
| 1417 | |
| 1418 | reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( |
| 1419 | SEQ_WCSS_UMAC_REO_REG_OFFSET)); |
| 1420 | |
| 1421 | reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK | |
| 1422 | HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | |
| 1423 | HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); |
| 1424 | |
| 1425 | reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, |
| 1426 | FRAGMENT_DEST_RING, reo_params->frag_dst_ring) | |
| 1427 | HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) | |
| 1428 | HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1); |
| 1429 | |
| 1430 | HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( |
| 1431 | SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); |
| 1432 | |
| 1433 | /* Other ring enable bits and REO_ENABLE will be set by FW */ |
| 1434 | |
| 1435 | /* TODO: Setup destination ring mapping if enabled */ |
| 1436 | |
| 1437 | /* TODO: Error destination ring setting is left to default. |
| 1438 | * Default setting is to send all errors to release ring. |
| 1439 | */ |
| 1440 | |
| 1441 | HAL_REG_WRITE(soc, |
| 1442 | HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( |
| 1443 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 1444 | HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1445 | |
| 1446 | HAL_REG_WRITE(soc, |
| 1447 | HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( |
| 1448 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 1449 | (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1450 | |
| 1451 | HAL_REG_WRITE(soc, |
| 1452 | HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( |
| 1453 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 1454 | (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1455 | |
| 1456 | HAL_REG_WRITE(soc, |
| 1457 | HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( |
| 1458 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 1459 | (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1460 | |
| 1461 | /* |
| 1462 | * When hash based routing is enabled, routing of the rx packet |
| 1463 | * is done based on the following value: 1 _ _ _ _ The last 4 |
| 1464 | * bits are based on hash[3:0]. This means the possible values |
| 1465 | * are 0x10 to 0x1f. This value is used to look-up the |
| 1466 | * ring ID configured in Destination_Ring_Ctrl_IX_* register. |
| 1467 | * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 |
| 1468 | * registers need to be configured to set-up the 16 entries to |
| 1469 | * map the hash values to a ring number. There are 3 bits per |
| 1470 | * hash entry which are mapped as follows: |
| 1471 | * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), |
| 1472 | * 7: NOT_USED. |
| 1473 | */ |
| 1474 | if (reo_params->rx_hash_enabled) { |
| 1475 | HAL_REG_WRITE(soc, |
| 1476 | HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( |
| 1477 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1478 | reo_params->remap1); |
| 1479 | |
| 1480 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, |
| 1481 | FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"), |
| 1482 | HAL_REG_READ(soc, |
| 1483 | HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( |
| 1484 | SEQ_WCSS_UMAC_REO_REG_OFFSET))); |
| 1485 | |
| 1486 | HAL_REG_WRITE(soc, |
| 1487 | HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( |
| 1488 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1489 | reo_params->remap2); |
| 1490 | |
| 1491 | QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, |
| 1492 | FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"), |
| 1493 | HAL_REG_READ(soc, |
| 1494 | HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( |
| 1495 | SEQ_WCSS_UMAC_REO_REG_OFFSET))); |
| 1496 | } |
| 1497 | |
| 1498 | |
| 1499 | /* TODO: Check if the following registers shoould be setup by host: |
| 1500 | * AGING_CONTROL |
| 1501 | * HIGH_MEMORY_THRESHOLD |
| 1502 | * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] |
| 1503 | * GLOBAL_LINK_DESC_COUNT_CTRL |
| 1504 | */ |
| 1505 | } |
| 1506 | |
| 1507 | /** |
Venkata Sharath Chandra Manchala | 443b9b4 | 2018-10-10 12:04:54 -0700 | [diff] [blame] | 1508 | * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring |
| 1509 | * @hal_soc: Opaque HAL SOC handle |
| 1510 | * @hal_ring: Source ring pointer |
| 1511 | * @headp: Head Pointer |
| 1512 | * @tailp: Tail Pointer |
| 1513 | * @ring: Ring type |
| 1514 | * |
| 1515 | * Return: Update tail pointer and head pointer in arguments. |
| 1516 | */ |
| 1517 | static inline |
| 1518 | void hal_get_hw_hptp_generic(struct hal_soc *soc, void *hal_ring, |
| 1519 | uint32_t *headp, uint32_t *tailp, |
| 1520 | uint8_t ring) |
| 1521 | { |
| 1522 | struct hal_srng *srng = (struct hal_srng *)hal_ring; |
| 1523 | struct hal_hw_srng_config *ring_config; |
| 1524 | enum hal_ring_type ring_type = (enum hal_ring_type)ring; |
| 1525 | |
| 1526 | if (!soc || !srng) { |
| 1527 | QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_ERROR, |
| 1528 | "%s: Context is Null", __func__); |
| 1529 | return; |
| 1530 | } |
| 1531 | |
| 1532 | ring_config = HAL_SRNG_CONFIG(soc, ring_type); |
| 1533 | if (!ring_config->lmac_ring) { |
| 1534 | if (srng->ring_dir == HAL_SRNG_SRC_RING) { |
Rakesh Pillai | 56320c1 | 2019-06-05 00:25:48 +0530 | [diff] [blame] | 1535 | *headp = SRNG_SRC_REG_READ(srng, HP); |
| 1536 | *tailp = SRNG_SRC_REG_READ(srng, TP); |
Venkata Sharath Chandra Manchala | 443b9b4 | 2018-10-10 12:04:54 -0700 | [diff] [blame] | 1537 | } else { |
Rakesh Pillai | 56320c1 | 2019-06-05 00:25:48 +0530 | [diff] [blame] | 1538 | *headp = SRNG_DST_REG_READ(srng, HP); |
| 1539 | *tailp = SRNG_DST_REG_READ(srng, TP); |
Venkata Sharath Chandra Manchala | 443b9b4 | 2018-10-10 12:04:54 -0700 | [diff] [blame] | 1540 | } |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | /** |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1545 | * hal_srng_src_hw_init - Private function to initialize SRNG |
| 1546 | * source ring HW |
| 1547 | * @hal_soc: HAL SOC handle |
| 1548 | * @srng: SRNG ring pointer |
| 1549 | */ |
| 1550 | static inline void hal_srng_src_hw_init_generic(void *halsoc, |
| 1551 | struct hal_srng *srng) |
| 1552 | { |
| 1553 | struct hal_soc *hal = (struct hal_soc *)halsoc; |
| 1554 | uint32_t reg_val = 0; |
| 1555 | uint64_t tp_addr = 0; |
| 1556 | |
| 1557 | HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); |
| 1558 | |
| 1559 | if (srng->flags & HAL_SRNG_MSI_INTR) { |
| 1560 | SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB, |
| 1561 | srng->msi_addr & 0xffffffff); |
| 1562 | reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR), |
| 1563 | (uint64_t)(srng->msi_addr) >> 32) | |
| 1564 | SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, |
| 1565 | MSI1_ENABLE), 1); |
| 1566 | SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); |
| 1567 | SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data); |
| 1568 | } |
| 1569 | |
| 1570 | SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); |
| 1571 | reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB), |
| 1572 | ((uint64_t)(srng->ring_base_paddr) >> 32)) | |
| 1573 | SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), |
| 1574 | srng->entry_size * srng->num_entries); |
| 1575 | SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val); |
| 1576 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1577 | reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1578 | SRNG_SRC_REG_WRITE(srng, ID, reg_val); |
| 1579 | |
| 1580 | /** |
| 1581 | * Interrupt setup: |
| 1582 | * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE |
| 1583 | * if level mode is required |
| 1584 | */ |
| 1585 | reg_val = 0; |
| 1586 | |
| 1587 | /* |
| 1588 | * WAR - Hawkeye v1 has a hardware bug which requires timer value to be |
| 1589 | * programmed in terms of 1us resolution instead of 8us resolution as |
| 1590 | * given in MLD. |
| 1591 | */ |
| 1592 | if (srng->intr_timer_thres_us) { |
| 1593 | reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, |
| 1594 | INTERRUPT_TIMER_THRESHOLD), |
| 1595 | srng->intr_timer_thres_us); |
| 1596 | /* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */ |
| 1597 | } |
| 1598 | |
| 1599 | if (srng->intr_batch_cntr_thres_entries) { |
| 1600 | reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0, |
| 1601 | BATCH_COUNTER_THRESHOLD), |
| 1602 | srng->intr_batch_cntr_thres_entries * |
| 1603 | srng->entry_size); |
| 1604 | } |
| 1605 | SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val); |
| 1606 | |
| 1607 | reg_val = 0; |
| 1608 | if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) { |
| 1609 | reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1, |
| 1610 | LOW_THRESHOLD), srng->u.src_ring.low_threshold); |
| 1611 | } |
| 1612 | |
| 1613 | SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val); |
| 1614 | |
| 1615 | /* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should |
| 1616 | * remain 0 to avoid some WBM stability issues. Remote head/tail |
| 1617 | * pointers are not required since this ring is completely managed |
| 1618 | * by WBM HW |
| 1619 | */ |
Mohit Khanna | 5f26348 | 2019-02-14 18:42:20 -0800 | [diff] [blame] | 1620 | reg_val = 0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1621 | if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) { |
| 1622 | tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + |
| 1623 | ((unsigned long)(srng->u.src_ring.tp_addr) - |
| 1624 | (unsigned long)(hal->shadow_rdptr_mem_vaddr))); |
| 1625 | SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff); |
| 1626 | SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32); |
Mohit Khanna | 5f26348 | 2019-02-14 18:42:20 -0800 | [diff] [blame] | 1627 | } else { |
| 1628 | reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, RING_ID_DISABLE), 1); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1629 | } |
| 1630 | |
| 1631 | /* Initilaize head and tail pointers to indicate ring is empty */ |
| 1632 | SRNG_SRC_REG_WRITE(srng, HP, 0); |
| 1633 | SRNG_SRC_REG_WRITE(srng, TP, 0); |
| 1634 | *(srng->u.src_ring.tp_addr) = 0; |
| 1635 | |
Mohit Khanna | 5f26348 | 2019-02-14 18:42:20 -0800 | [diff] [blame] | 1636 | reg_val |= ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1637 | SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | |
| 1638 | ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? |
| 1639 | SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | |
| 1640 | ((srng->flags & HAL_SRNG_MSI_SWAP) ? |
| 1641 | SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0); |
| 1642 | |
| 1643 | /* Loop count is not used for SRC rings */ |
| 1644 | reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1); |
| 1645 | |
| 1646 | /* |
| 1647 | * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); |
| 1648 | * todo: update fw_api and replace with above line |
| 1649 | * (when SRNG_ENABLE field for the MISC register is available in fw_api) |
| 1650 | * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) |
| 1651 | */ |
| 1652 | reg_val |= 0x40; |
| 1653 | |
| 1654 | SRNG_SRC_REG_WRITE(srng, MISC, reg_val); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1655 | } |
| 1656 | |
| 1657 | /** |
| 1658 | * hal_srng_dst_hw_init - Private function to initialize SRNG |
| 1659 | * destination ring HW |
| 1660 | * @hal_soc: HAL SOC handle |
| 1661 | * @srng: SRNG ring pointer |
| 1662 | */ |
| 1663 | static inline void hal_srng_dst_hw_init_generic(void *halsoc, |
| 1664 | struct hal_srng *srng) |
| 1665 | { |
| 1666 | struct hal_soc *hal = (struct hal_soc *)halsoc; |
| 1667 | uint32_t reg_val = 0; |
| 1668 | uint64_t hp_addr = 0; |
| 1669 | |
| 1670 | HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id); |
| 1671 | |
| 1672 | if (srng->flags & HAL_SRNG_MSI_INTR) { |
| 1673 | SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB, |
| 1674 | srng->msi_addr & 0xffffffff); |
| 1675 | reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR), |
| 1676 | (uint64_t)(srng->msi_addr) >> 32) | |
| 1677 | SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, |
| 1678 | MSI1_ENABLE), 1); |
| 1679 | SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val); |
| 1680 | SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data); |
| 1681 | } |
| 1682 | |
| 1683 | SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff); |
| 1684 | reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB), |
| 1685 | ((uint64_t)(srng->ring_base_paddr) >> 32)) | |
| 1686 | SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE), |
| 1687 | srng->entry_size * srng->num_entries); |
| 1688 | SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val); |
| 1689 | |
| 1690 | reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) | |
| 1691 | SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size); |
| 1692 | SRNG_DST_REG_WRITE(srng, ID, reg_val); |
| 1693 | |
| 1694 | |
| 1695 | /** |
| 1696 | * Interrupt setup: |
| 1697 | * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE |
| 1698 | * if level mode is required |
| 1699 | */ |
| 1700 | reg_val = 0; |
| 1701 | if (srng->intr_timer_thres_us) { |
| 1702 | reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, |
| 1703 | INTERRUPT_TIMER_THRESHOLD), |
| 1704 | srng->intr_timer_thres_us >> 3); |
| 1705 | } |
| 1706 | |
| 1707 | if (srng->intr_batch_cntr_thres_entries) { |
| 1708 | reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP, |
| 1709 | BATCH_COUNTER_THRESHOLD), |
| 1710 | srng->intr_batch_cntr_thres_entries * |
| 1711 | srng->entry_size); |
| 1712 | } |
| 1713 | |
| 1714 | SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val); |
| 1715 | hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr + |
| 1716 | ((unsigned long)(srng->u.dst_ring.hp_addr) - |
| 1717 | (unsigned long)(hal->shadow_rdptr_mem_vaddr))); |
| 1718 | SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff); |
| 1719 | SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32); |
| 1720 | |
| 1721 | /* Initilaize head and tail pointers to indicate ring is empty */ |
| 1722 | SRNG_DST_REG_WRITE(srng, HP, 0); |
| 1723 | SRNG_DST_REG_WRITE(srng, TP, 0); |
| 1724 | *(srng->u.dst_ring.hp_addr) = 0; |
| 1725 | |
| 1726 | reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ? |
| 1727 | SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) | |
| 1728 | ((srng->flags & HAL_SRNG_RING_PTR_SWAP) ? |
| 1729 | SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) | |
| 1730 | ((srng->flags & HAL_SRNG_MSI_SWAP) ? |
| 1731 | SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0); |
| 1732 | |
| 1733 | /* |
| 1734 | * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1); |
| 1735 | * todo: update fw_api and replace with above line |
| 1736 | * (when SRNG_ENABLE field for the MISC register is available in fw_api) |
| 1737 | * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC) |
| 1738 | */ |
| 1739 | reg_val |= 0x40; |
| 1740 | |
| 1741 | SRNG_DST_REG_WRITE(srng, MISC, reg_val); |
| 1742 | |
| 1743 | } |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 1744 | |
| 1745 | #define HAL_RX_WBM_ERR_SRC_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ |
| 1746 | (WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ |
| 1747 | WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> \ |
| 1748 | WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB) |
| 1749 | |
| 1750 | #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ |
| 1751 | (WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET >> 2))) & \ |
| 1752 | WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK) >> \ |
| 1753 | WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB) |
| 1754 | |
| 1755 | #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \ |
| 1756 | (WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET >> 2))) & \ |
| 1757 | WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK) >> \ |
| 1758 | WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB) |
| 1759 | |
| 1760 | #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ |
| 1761 | (((*(((uint32_t *) wbm_desc) + \ |
| 1762 | (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ |
| 1763 | WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ |
| 1764 | WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) |
| 1765 | |
| 1766 | #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ |
| 1767 | (((*(((uint32_t *) wbm_desc) + \ |
| 1768 | (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ |
| 1769 | WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ |
| 1770 | WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) |
| 1771 | |
| 1772 | /** |
| 1773 | * hal_rx_wbm_err_info_get_generic(): Retrieves WBM error code and reason and |
| 1774 | * save it to hal_wbm_err_desc_info structure passed by caller |
| 1775 | * @wbm_desc: wbm ring descriptor |
| 1776 | * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. |
| 1777 | * Return: void |
| 1778 | */ |
| 1779 | static inline void hal_rx_wbm_err_info_get_generic(void *wbm_desc, |
| 1780 | void *wbm_er_info1) |
| 1781 | { |
| 1782 | struct hal_wbm_err_desc_info *wbm_er_info = |
| 1783 | (struct hal_wbm_err_desc_info *)wbm_er_info1; |
| 1784 | |
| 1785 | wbm_er_info->wbm_err_src = HAL_RX_WBM_ERR_SRC_GET(wbm_desc); |
| 1786 | wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); |
| 1787 | wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); |
| 1788 | wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); |
| 1789 | wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); |
| 1790 | } |
| 1791 | |
| 1792 | /** |
| 1793 | * hal_tx_comp_get_release_reason_generic() - TQM Release reason |
| 1794 | * @hal_desc: completion ring descriptor pointer |
| 1795 | * |
| 1796 | * This function will return the type of pointer - buffer or descriptor |
| 1797 | * |
| 1798 | * Return: buffer type |
| 1799 | */ |
| 1800 | static inline uint8_t hal_tx_comp_get_release_reason_generic(void *hal_desc) |
| 1801 | { |
| 1802 | uint32_t comp_desc = |
| 1803 | *(uint32_t *) (((uint8_t *) hal_desc) + |
| 1804 | WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); |
| 1805 | |
| 1806 | return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> |
| 1807 | WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; |
| 1808 | } |
| 1809 | |
| 1810 | /** |
| 1811 | * hal_rx_dump_mpdu_start_tlv_generic: dump RX mpdu_start TLV in structured |
| 1812 | * human readable format. |
| 1813 | * @mpdu_start: pointer the rx_attention TLV in pkt. |
| 1814 | * @dbg_level: log level. |
| 1815 | * |
| 1816 | * Return: void |
| 1817 | */ |
| 1818 | static inline void hal_rx_dump_mpdu_start_tlv_generic(void *mpdustart, |
| 1819 | uint8_t dbg_level) |
| 1820 | { |
| 1821 | struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; |
| 1822 | struct rx_mpdu_info *mpdu_info = |
| 1823 | (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; |
| 1824 | |
Krunal Soni | 9911b44 | 2019-02-22 15:39:03 -0800 | [diff] [blame] | 1825 | hal_verbose_debug( |
| 1826 | "rx_mpdu_start tlv (1/5) - " |
| 1827 | "rxpcu_mpdu_filter_in_category: %x " |
| 1828 | "sw_frame_group_id: %x " |
| 1829 | "ndp_frame: %x " |
| 1830 | "phy_err: %x " |
| 1831 | "phy_err_during_mpdu_header: %x " |
| 1832 | "protocol_version_err: %x " |
| 1833 | "ast_based_lookup_valid: %x " |
| 1834 | "phy_ppdu_id: %x " |
| 1835 | "ast_index: %x " |
| 1836 | "sw_peer_id: %x " |
| 1837 | "mpdu_frame_control_valid: %x " |
| 1838 | "mpdu_duration_valid: %x " |
| 1839 | "mac_addr_ad1_valid: %x " |
| 1840 | "mac_addr_ad2_valid: %x " |
| 1841 | "mac_addr_ad3_valid: %x " |
| 1842 | "mac_addr_ad4_valid: %x " |
| 1843 | "mpdu_sequence_control_valid: %x " |
| 1844 | "mpdu_qos_control_valid: %x " |
| 1845 | "mpdu_ht_control_valid: %x " |
| 1846 | "frame_encryption_info_valid: %x ", |
| 1847 | mpdu_info->rxpcu_mpdu_filter_in_category, |
| 1848 | mpdu_info->sw_frame_group_id, |
| 1849 | mpdu_info->ndp_frame, |
| 1850 | mpdu_info->phy_err, |
| 1851 | mpdu_info->phy_err_during_mpdu_header, |
| 1852 | mpdu_info->protocol_version_err, |
| 1853 | mpdu_info->ast_based_lookup_valid, |
| 1854 | mpdu_info->phy_ppdu_id, |
| 1855 | mpdu_info->ast_index, |
| 1856 | mpdu_info->sw_peer_id, |
| 1857 | mpdu_info->mpdu_frame_control_valid, |
| 1858 | mpdu_info->mpdu_duration_valid, |
| 1859 | mpdu_info->mac_addr_ad1_valid, |
| 1860 | mpdu_info->mac_addr_ad2_valid, |
| 1861 | mpdu_info->mac_addr_ad3_valid, |
| 1862 | mpdu_info->mac_addr_ad4_valid, |
| 1863 | mpdu_info->mpdu_sequence_control_valid, |
| 1864 | mpdu_info->mpdu_qos_control_valid, |
| 1865 | mpdu_info->mpdu_ht_control_valid, |
| 1866 | mpdu_info->frame_encryption_info_valid); |
Mohit Khanna | 5868efa | 2018-12-18 16:50:20 -0800 | [diff] [blame] | 1867 | |
Krunal Soni | 9911b44 | 2019-02-22 15:39:03 -0800 | [diff] [blame] | 1868 | hal_verbose_debug( |
| 1869 | "rx_mpdu_start tlv (2/5) - " |
| 1870 | "fr_ds: %x " |
| 1871 | "to_ds: %x " |
| 1872 | "encrypted: %x " |
| 1873 | "mpdu_retry: %x " |
| 1874 | "mpdu_sequence_number: %x " |
| 1875 | "epd_en: %x " |
| 1876 | "all_frames_shall_be_encrypted: %x " |
| 1877 | "encrypt_type: %x " |
| 1878 | "mesh_sta: %x " |
| 1879 | "bssid_hit: %x " |
| 1880 | "bssid_number: %x " |
| 1881 | "tid: %x " |
| 1882 | "pn_31_0: %x " |
| 1883 | "pn_63_32: %x " |
| 1884 | "pn_95_64: %x " |
| 1885 | "pn_127_96: %x " |
| 1886 | "peer_meta_data: %x " |
| 1887 | "rxpt_classify_info.reo_destination_indication: %x " |
| 1888 | "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " |
| 1889 | "rx_reo_queue_desc_addr_31_0: %x ", |
| 1890 | mpdu_info->fr_ds, |
| 1891 | mpdu_info->to_ds, |
| 1892 | mpdu_info->encrypted, |
| 1893 | mpdu_info->mpdu_retry, |
| 1894 | mpdu_info->mpdu_sequence_number, |
| 1895 | mpdu_info->epd_en, |
| 1896 | mpdu_info->all_frames_shall_be_encrypted, |
| 1897 | mpdu_info->encrypt_type, |
| 1898 | mpdu_info->mesh_sta, |
| 1899 | mpdu_info->bssid_hit, |
| 1900 | mpdu_info->bssid_number, |
| 1901 | mpdu_info->tid, |
| 1902 | mpdu_info->pn_31_0, |
| 1903 | mpdu_info->pn_63_32, |
| 1904 | mpdu_info->pn_95_64, |
| 1905 | mpdu_info->pn_127_96, |
| 1906 | mpdu_info->peer_meta_data, |
| 1907 | mpdu_info->rxpt_classify_info_details.reo_destination_indication, |
| 1908 | mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, |
| 1909 | mpdu_info->rx_reo_queue_desc_addr_31_0); |
Mohit Khanna | 5868efa | 2018-12-18 16:50:20 -0800 | [diff] [blame] | 1910 | |
Krunal Soni | 9911b44 | 2019-02-22 15:39:03 -0800 | [diff] [blame] | 1911 | hal_verbose_debug( |
| 1912 | "rx_mpdu_start tlv (3/5) - " |
| 1913 | "rx_reo_queue_desc_addr_39_32: %x " |
| 1914 | "receive_queue_number: %x " |
| 1915 | "pre_delim_err_warning: %x " |
| 1916 | "first_delim_err: %x " |
| 1917 | "key_id_octet: %x " |
| 1918 | "new_peer_entry: %x " |
| 1919 | "decrypt_needed: %x " |
| 1920 | "decap_type: %x " |
| 1921 | "rx_insert_vlan_c_tag_padding: %x " |
| 1922 | "rx_insert_vlan_s_tag_padding: %x " |
| 1923 | "strip_vlan_c_tag_decap: %x " |
| 1924 | "strip_vlan_s_tag_decap: %x " |
| 1925 | "pre_delim_count: %x " |
| 1926 | "ampdu_flag: %x " |
| 1927 | "bar_frame: %x " |
| 1928 | "mpdu_length: %x " |
| 1929 | "first_mpdu: %x " |
| 1930 | "mcast_bcast: %x " |
| 1931 | "ast_index_not_found: %x " |
| 1932 | "ast_index_timeout: %x ", |
| 1933 | mpdu_info->rx_reo_queue_desc_addr_39_32, |
| 1934 | mpdu_info->receive_queue_number, |
| 1935 | mpdu_info->pre_delim_err_warning, |
| 1936 | mpdu_info->first_delim_err, |
| 1937 | mpdu_info->key_id_octet, |
| 1938 | mpdu_info->new_peer_entry, |
| 1939 | mpdu_info->decrypt_needed, |
| 1940 | mpdu_info->decap_type, |
| 1941 | mpdu_info->rx_insert_vlan_c_tag_padding, |
| 1942 | mpdu_info->rx_insert_vlan_s_tag_padding, |
| 1943 | mpdu_info->strip_vlan_c_tag_decap, |
| 1944 | mpdu_info->strip_vlan_s_tag_decap, |
| 1945 | mpdu_info->pre_delim_count, |
| 1946 | mpdu_info->ampdu_flag, |
| 1947 | mpdu_info->bar_frame, |
| 1948 | mpdu_info->mpdu_length, |
| 1949 | mpdu_info->first_mpdu, |
| 1950 | mpdu_info->mcast_bcast, |
| 1951 | mpdu_info->ast_index_not_found, |
| 1952 | mpdu_info->ast_index_timeout); |
Mohit Khanna | 5868efa | 2018-12-18 16:50:20 -0800 | [diff] [blame] | 1953 | |
Krunal Soni | 9911b44 | 2019-02-22 15:39:03 -0800 | [diff] [blame] | 1954 | hal_verbose_debug( |
| 1955 | "rx_mpdu_start tlv (4/5) - " |
| 1956 | "power_mgmt: %x " |
| 1957 | "non_qos: %x " |
| 1958 | "null_data: %x " |
| 1959 | "mgmt_type: %x " |
| 1960 | "ctrl_type: %x " |
| 1961 | "more_data: %x " |
| 1962 | "eosp: %x " |
| 1963 | "fragment_flag: %x " |
| 1964 | "order: %x " |
| 1965 | "u_apsd_trigger: %x " |
| 1966 | "encrypt_required: %x " |
| 1967 | "directed: %x " |
| 1968 | "mpdu_frame_control_field: %x " |
| 1969 | "mpdu_duration_field: %x " |
| 1970 | "mac_addr_ad1_31_0: %x " |
| 1971 | "mac_addr_ad1_47_32: %x " |
| 1972 | "mac_addr_ad2_15_0: %x " |
| 1973 | "mac_addr_ad2_47_16: %x " |
| 1974 | "mac_addr_ad3_31_0: %x " |
| 1975 | "mac_addr_ad3_47_32: %x ", |
| 1976 | mpdu_info->power_mgmt, |
| 1977 | mpdu_info->non_qos, |
| 1978 | mpdu_info->null_data, |
| 1979 | mpdu_info->mgmt_type, |
| 1980 | mpdu_info->ctrl_type, |
| 1981 | mpdu_info->more_data, |
| 1982 | mpdu_info->eosp, |
| 1983 | mpdu_info->fragment_flag, |
| 1984 | mpdu_info->order, |
| 1985 | mpdu_info->u_apsd_trigger, |
| 1986 | mpdu_info->encrypt_required, |
| 1987 | mpdu_info->directed, |
| 1988 | mpdu_info->mpdu_frame_control_field, |
| 1989 | mpdu_info->mpdu_duration_field, |
| 1990 | mpdu_info->mac_addr_ad1_31_0, |
| 1991 | mpdu_info->mac_addr_ad1_47_32, |
| 1992 | mpdu_info->mac_addr_ad2_15_0, |
| 1993 | mpdu_info->mac_addr_ad2_47_16, |
| 1994 | mpdu_info->mac_addr_ad3_31_0, |
| 1995 | mpdu_info->mac_addr_ad3_47_32); |
Mohit Khanna | 5868efa | 2018-12-18 16:50:20 -0800 | [diff] [blame] | 1996 | |
Krunal Soni | 9911b44 | 2019-02-22 15:39:03 -0800 | [diff] [blame] | 1997 | hal_verbose_debug( |
| 1998 | "rx_mpdu_start tlv (5/5) - " |
| 1999 | "mpdu_sequence_control_field: %x " |
| 2000 | "mac_addr_ad4_31_0: %x " |
| 2001 | "mac_addr_ad4_47_32: %x " |
| 2002 | "mpdu_qos_control_field: %x " |
| 2003 | "mpdu_ht_control_field: %x ", |
| 2004 | mpdu_info->mpdu_sequence_control_field, |
| 2005 | mpdu_info->mac_addr_ad4_31_0, |
| 2006 | mpdu_info->mac_addr_ad4_47_32, |
| 2007 | mpdu_info->mpdu_qos_control_field, |
| 2008 | mpdu_info->mpdu_ht_control_field); |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 2009 | } |
Chaithanya Garrepalli | 710e295 | 2018-09-12 00:44:27 +0530 | [diff] [blame] | 2010 | |
| 2011 | /** |
| 2012 | * hal_tx_desc_set_search_type - Set the search type value |
| 2013 | * @desc: Handle to Tx Descriptor |
| 2014 | * @search_type: search type |
| 2015 | * 0 – Normal search |
| 2016 | * 1 – Index based address search |
| 2017 | * 2 – Index based flow search |
| 2018 | * |
| 2019 | * Return: void |
| 2020 | */ |
| 2021 | #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET |
| 2022 | static void hal_tx_desc_set_search_type_generic(void *desc, |
| 2023 | uint8_t search_type) |
| 2024 | { |
| 2025 | HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= |
| 2026 | HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); |
| 2027 | } |
| 2028 | #else |
| 2029 | static void hal_tx_desc_set_search_type_generic(void *desc, |
| 2030 | uint8_t search_type) |
| 2031 | { |
| 2032 | } |
| 2033 | |
| 2034 | #endif |
| 2035 | |
| 2036 | /** |
| 2037 | * hal_tx_desc_set_search_index - Set the search index value |
| 2038 | * @desc: Handle to Tx Descriptor |
| 2039 | * @search_index: The index that will be used for index based address or |
| 2040 | * flow search. The field is valid when 'search_type' is |
| 2041 | * 1 0r 2 |
| 2042 | * |
| 2043 | * Return: void |
| 2044 | */ |
| 2045 | #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET |
| 2046 | static void hal_tx_desc_set_search_index_generic(void *desc, |
| 2047 | uint32_t search_index) |
| 2048 | { |
| 2049 | HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= |
| 2050 | HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); |
| 2051 | } |
| 2052 | #else |
| 2053 | static void hal_tx_desc_set_search_index_generic(void *desc, |
| 2054 | uint32_t search_index) |
| 2055 | { |
| 2056 | } |
| 2057 | #endif |
Debasis Das | c39a68d | 2019-01-28 17:02:06 +0530 | [diff] [blame] | 2058 | |
| 2059 | /** |
| 2060 | * hal_tx_set_pcp_tid_map_generic() - Configure default PCP to TID map table |
| 2061 | * @soc: HAL SoC context |
| 2062 | * @map: PCP-TID mapping table |
| 2063 | * |
| 2064 | * PCP are mapped to 8 TID values using TID values programmed |
| 2065 | * in one set of mapping registers PCP_TID_MAP_<0 to 6> |
| 2066 | * The mapping register has TID mapping for 8 PCP values |
| 2067 | * |
| 2068 | * Return: none |
| 2069 | */ |
| 2070 | static void hal_tx_set_pcp_tid_map_generic(void *hal_soc, uint8_t *map) |
| 2071 | { |
| 2072 | uint32_t addr, value; |
| 2073 | |
| 2074 | struct hal_soc *soc = (struct hal_soc *)hal_soc; |
| 2075 | |
| 2076 | addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( |
| 2077 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); |
| 2078 | |
| 2079 | value = (map[0] | |
| 2080 | (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | |
| 2081 | (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | |
| 2082 | (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | |
| 2083 | (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | |
| 2084 | (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | |
| 2085 | (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | |
| 2086 | (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); |
| 2087 | |
| 2088 | HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); |
| 2089 | } |
| 2090 | |
| 2091 | /** |
| 2092 | * hal_tx_update_pcp_tid_generic() - Update the pcp tid map table with |
| 2093 | * value received from user-space |
| 2094 | * @soc: HAL SoC context |
| 2095 | * @pcp: pcp value |
| 2096 | * @tid : tid value |
| 2097 | * |
| 2098 | * Return: void |
| 2099 | */ |
| 2100 | static |
| 2101 | void hal_tx_update_pcp_tid_generic(void *hal_soc, uint8_t pcp, uint8_t tid) |
| 2102 | { |
| 2103 | uint32_t addr, value, regval; |
| 2104 | |
| 2105 | struct hal_soc *soc = (struct hal_soc *)hal_soc; |
| 2106 | |
| 2107 | addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( |
| 2108 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); |
| 2109 | |
| 2110 | value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); |
| 2111 | |
| 2112 | /* Read back previous PCP TID config and update |
| 2113 | * with new config. |
| 2114 | */ |
| 2115 | regval = HAL_REG_READ(soc, addr); |
| 2116 | regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); |
| 2117 | regval |= value; |
| 2118 | |
| 2119 | HAL_REG_WRITE(soc, addr, |
| 2120 | (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); |
| 2121 | } |
| 2122 | |
| 2123 | /** |
| 2124 | * hal_tx_update_tidmap_prty_generic() - Update the tid map priority |
| 2125 | * @soc: HAL SoC context |
| 2126 | * @val: priority value |
| 2127 | * |
| 2128 | * Return: void |
| 2129 | */ |
| 2130 | static |
| 2131 | void hal_tx_update_tidmap_prty_generic(void *hal_soc, uint8_t value) |
| 2132 | { |
| 2133 | uint32_t addr; |
| 2134 | |
| 2135 | struct hal_soc *soc = (struct hal_soc *)hal_soc; |
| 2136 | |
| 2137 | addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( |
| 2138 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); |
| 2139 | |
| 2140 | HAL_REG_WRITE(soc, addr, |
| 2141 | (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); |
| 2142 | } |
| 2143 | #endif /* _HAL_GENERIC_API_H_ */ |