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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000018#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000019#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000020#include "llvm/Target/TargetSubtargetInfo.h"
21
22using namespace llvm;
23
Quentin Colombet000b5802016-03-11 17:27:51 +000024void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000025 this->MF = &MF;
26 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000027 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000028 this->TII = MF.getSubtarget().getInstrInfo();
29 this->DL = DebugLoc();
30 this->MI = nullptr;
Tim Northover438c77c2016-08-25 17:37:32 +000031 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000032}
33
Quentin Colombet91ebd712016-03-11 17:27:47 +000034void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000035 this->MBB = &MBB;
36 Before = Beginning;
37 assert(&getMF() == MBB.getParent() &&
38 "Basic block is in a different function");
39}
40
41void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
42 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000043 setMBB(*MI.getParent());
Quentin Colombet2ad1f852016-02-11 17:44:59 +000044 this->MI = &MI;
45 this->Before = Before;
46}
47
48MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
49 if (MI) {
50 if (Before)
51 return MI;
52 if (!MI->getNextNode())
53 return getMBB().end();
54 return MI->getNextNode();
55 }
56 return Before ? getMBB().begin() : getMBB().end();
57}
58
Tim Northover438c77c2016-08-25 17:37:32 +000059void MachineIRBuilder::recordInsertions(
60 std::function<void(MachineInstr *)> Inserted) {
61 InsertedInstr = Inserted;
62}
63
64void MachineIRBuilder::stopRecordingInsertions() {
65 InsertedInstr = nullptr;
66}
67
Quentin Colombetf9b49342016-03-11 17:27:58 +000068//------------------------------------------------------------------------------
69// Build instruction variants.
70//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000071
Tim Northover0f140c72016-09-09 11:46:34 +000072MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000073 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera51575f2016-07-29 17:43:52 +000074 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000075 if (InsertedInstr)
76 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000077 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000078}
79
Tim Northover0f140c72016-09-09 11:46:34 +000080MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +000081 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +000082 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +000083 .addDef(Res)
84 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +000085}
Tim Northover33b07d62016-07-22 20:03:43 +000086
Tim Northover032548f2016-09-12 12:10:41 +000087MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
88 const GlobalValue *GV) {
89 assert(MRI->getType(Res).isPointer() && "invalid operand type");
90 assert(MRI->getType(Res).getAddressSpace() ==
91 GV->getType()->getAddressSpace() &&
92 "address space mismatch");
93
94 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
95 .addDef(Res)
96 .addGlobalAddress(GV);
97}
98
Tim Northover0f140c72016-09-09 11:46:34 +000099MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
100 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000101 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
102 "invalid operand type");
103 assert(MRI->getType(Res) == MRI->getType(Op0) &&
104 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
105
Tim Northover0f140c72016-09-09 11:46:34 +0000106 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +0000107 .addDef(Res)
108 .addUse(Op0)
109 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000110}
111
Tim Northovera7653b32016-09-12 11:20:22 +0000112MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
113 unsigned Op1) {
114 assert(MRI->getType(Res).isPointer() &&
115 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
116 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
117
118 return buildInstr(TargetOpcode::G_GEP)
119 .addDef(Res)
120 .addUse(Op0)
121 .addUse(Op1);
122}
123
Tim Northover0f140c72016-09-09 11:46:34 +0000124MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
125 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000126 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
127 "invalid operand type");
128 assert(MRI->getType(Res) == MRI->getType(Op0) &&
129 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
130
Tim Northover0f140c72016-09-09 11:46:34 +0000131 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000132 .addDef(Res)
133 .addUse(Op0)
134 .addUse(Op1);
135}
136
Tim Northover0f140c72016-09-09 11:46:34 +0000137MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
138 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000139 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
140 "invalid operand type");
141 assert(MRI->getType(Res) == MRI->getType(Op0) &&
142 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
143
Tim Northover0f140c72016-09-09 11:46:34 +0000144 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000145 .addDef(Res)
146 .addUse(Op0)
147 .addUse(Op1);
148}
149
Tim Northovera51575f2016-07-29 17:43:52 +0000150MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000151 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000152}
153
Tim Northovera51575f2016-07-29 17:43:52 +0000154MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
155 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000156}
157
Tim Northover0f140c72016-09-09 11:46:34 +0000158MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, int64_t Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000159 assert(MRI->getType(Res).isScalar() && "invalid operand type");
160
Tim Northover0f140c72016-09-09 11:46:34 +0000161 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addImm(Val);
Tim Northover9656f142016-08-04 20:54:13 +0000162}
163
Tim Northover0f140c72016-09-09 11:46:34 +0000164MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
165 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000166 assert(MRI->getType(Res).isScalar() && "invalid operand type");
167
Tim Northover0f140c72016-09-09 11:46:34 +0000168 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000169}
170
Tim Northover0f140c72016-09-09 11:46:34 +0000171MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000172 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000173 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
174
Tim Northover0f140c72016-09-09 11:46:34 +0000175 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000176}
177
Tim Northover0f140c72016-09-09 11:46:34 +0000178MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
179 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000180 assert(MRI->getType(Res).isValid() && "invalid operand type");
181 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
182
Tim Northover0f140c72016-09-09 11:46:34 +0000183 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000184 .addDef(Res)
185 .addUse(Addr)
186 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000187}
188
Tim Northover0f140c72016-09-09 11:46:34 +0000189MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
190 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000191 assert(MRI->getType(Val).isValid() && "invalid operand type");
192 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
193
Tim Northover0f140c72016-09-09 11:46:34 +0000194 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000195 .addUse(Val)
196 .addUse(Addr)
197 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000198}
199
Tim Northover0f140c72016-09-09 11:46:34 +0000200MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
201 unsigned CarryOut,
202 unsigned Op0, unsigned Op1,
203 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000204 assert(MRI->getType(Res).isScalar() && "invalid operand type");
205 assert(MRI->getType(Res) == MRI->getType(Op0) &&
206 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
207 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
208 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
209
Tim Northover0f140c72016-09-09 11:46:34 +0000210 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000211 .addDef(Res)
212 .addDef(CarryOut)
213 .addUse(Op0)
214 .addUse(Op1)
215 .addUse(CarryIn);
216}
217
Tim Northover0f140c72016-09-09 11:46:34 +0000218MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
219 validateTruncExt(Res, Op, true);
220 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000221}
222
Tim Northover0f140c72016-09-09 11:46:34 +0000223MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
224 validateTruncExt(Res, Op, true);
225 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000226}
227
Tim Northover0f140c72016-09-09 11:46:34 +0000228MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
229 validateTruncExt(Res, Op, true);
230 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000231}
232
Tim Northovera7653b32016-09-12 11:20:22 +0000233MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
234 unsigned Op) {
235 unsigned Opcode = TargetOpcode::COPY;
236 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
237 Opcode = TargetOpcode::G_SEXT;
238 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
239 Opcode = TargetOpcode::G_TRUNC;
240
241 return buildInstr(Opcode).addDef(Res).addUse(Op);
242}
243
Tim Northover0f140c72016-09-09 11:46:34 +0000244MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results,
Tim Northover26b76f22016-08-19 18:32:14 +0000245 ArrayRef<uint64_t> Indices,
Tim Northover0f140c72016-09-09 11:46:34 +0000246 unsigned Src) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000247#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000248 assert(Results.size() == Indices.size() && "inconsistent number of regs");
Tim Northover26b76f22016-08-19 18:32:14 +0000249 assert(!Results.empty() && "invalid trivial extract");
Tim Northover991b12b2016-08-30 20:51:25 +0000250 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
251 "extract offsets must be in ascending order");
Tim Northover33b07d62016-07-22 20:03:43 +0000252
Tim Northover1f8b1db2016-09-09 11:46:58 +0000253 assert(MRI->getType(Src).isValid() && "invalid operand type");
254 for (auto Res : Results)
255 assert(MRI->getType(Res).isValid() && "invalid operand type");
256#endif
257
Tim Northover26b76f22016-08-19 18:32:14 +0000258 auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
Tim Northover33b07d62016-07-22 20:03:43 +0000259 for (auto Res : Results)
Tim Northovera51575f2016-07-29 17:43:52 +0000260 MIB.addDef(Res);
Tim Northover33b07d62016-07-22 20:03:43 +0000261
Tim Northovera51575f2016-07-29 17:43:52 +0000262 MIB.addUse(Src);
Tim Northover33b07d62016-07-22 20:03:43 +0000263
Tim Northover26b76f22016-08-19 18:32:14 +0000264 for (auto Idx : Indices)
Tim Northover33b07d62016-07-22 20:03:43 +0000265 MIB.addImm(Idx);
Tim Northover26b76f22016-08-19 18:32:14 +0000266
267 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +0000268 if (InsertedInstr)
269 InsertedInstr(MIB);
Tim Northover26b76f22016-08-19 18:32:14 +0000270
Tim Northovera51575f2016-07-29 17:43:52 +0000271 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000272}
273
Tim Northover91c81732016-08-19 17:17:06 +0000274MachineInstrBuilder
Tim Northover0f140c72016-09-09 11:46:34 +0000275MachineIRBuilder::buildSequence(unsigned Res,
Tim Northover91c81732016-08-19 17:17:06 +0000276 ArrayRef<unsigned> Ops,
Tim Northover26b76f22016-08-19 18:32:14 +0000277 ArrayRef<unsigned> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000278#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000279 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000280 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000281 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
282 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000283
Tim Northover1f8b1db2016-09-09 11:46:58 +0000284 assert(MRI->getType(Res).isValid() && "invalid operand type");
285 for (auto Op : Ops)
286 assert(MRI->getType(Op).isValid() && "invalid operand type");
287#endif
288
Tim Northover0f140c72016-09-09 11:46:34 +0000289 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE);
Tim Northovera51575f2016-07-29 17:43:52 +0000290 MIB.addDef(Res);
Tim Northover91c81732016-08-19 17:17:06 +0000291 for (unsigned i = 0; i < Ops.size(); ++i) {
292 MIB.addUse(Ops[i]);
Tim Northover26b76f22016-08-19 18:32:14 +0000293 MIB.addImm(Indices[i]);
Tim Northover91c81732016-08-19 17:17:06 +0000294 }
Tim Northovera51575f2016-07-29 17:43:52 +0000295 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000296}
Tim Northover5fb414d2016-07-29 22:32:36 +0000297
Tim Northover0f140c72016-09-09 11:46:34 +0000298MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000299 unsigned Res,
300 bool HasSideEffects) {
301 auto MIB =
302 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000303 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000304 if (Res)
305 MIB.addDef(Res);
306 MIB.addIntrinsicID(ID);
307 return MIB;
308}
Tim Northover32335812016-08-04 18:35:11 +0000309
Tim Northover0f140c72016-09-09 11:46:34 +0000310MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
311 validateTruncExt(Res, Op, false);
312 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000313}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000314
Tim Northover0f140c72016-09-09 11:46:34 +0000315MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
316 validateTruncExt(Res, Op, false);
317 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000318}
319
Tim Northover0f140c72016-09-09 11:46:34 +0000320MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000321 unsigned Res, unsigned Op0,
322 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000323#ifndef NDEBUG
324 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
325 "invalid operand type");
326 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
327 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
328 if (MRI->getType(Op0).isScalar())
329 assert(MRI->getType(Res).isScalar() && "type mismatch");
330 else
331 assert(MRI->getType(Res).isVector() &&
332 MRI->getType(Res).getNumElements() ==
333 MRI->getType(Op0).getNumElements() &&
334 "type mismatch");
335#endif
336
Tim Northover0f140c72016-09-09 11:46:34 +0000337 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000338 .addDef(Res)
339 .addPredicate(Pred)
340 .addUse(Op0)
341 .addUse(Op1);
342}
Tim Northover5a28c362016-08-19 20:09:07 +0000343
Tim Northover0f140c72016-09-09 11:46:34 +0000344MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000345 unsigned Res, unsigned Op0,
346 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000347#ifndef NDEBUG
348 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
349 "invalid operand type");
350 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
351 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
352 if (MRI->getType(Op0).isScalar())
353 assert(MRI->getType(Res).isScalar() && "type mismatch");
354 else
355 assert(MRI->getType(Res).isVector() &&
356 MRI->getType(Res).getNumElements() ==
357 MRI->getType(Op0).getNumElements() &&
358 "type mismatch");
359#endif
360
Tim Northover0f140c72016-09-09 11:46:34 +0000361 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000362 .addDef(Res)
363 .addPredicate(Pred)
364 .addUse(Op0)
365 .addUse(Op1);
366}
367
Tim Northover0f140c72016-09-09 11:46:34 +0000368MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000369 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000370#ifndef NDEBUG
371 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
372 "invalid operand type");
373 assert(MRI->getType(Res) == MRI->getType(Op0) &&
374 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
375 if (MRI->getType(Res).isScalar())
376 assert(MRI->getType(Tst).isScalar() && "type mismatch");
377 else
378 assert(MRI->getType(Tst).isVector() &&
379 MRI->getType(Tst).getNumElements() ==
380 MRI->getType(Op0).getNumElements() &&
381 "type mismatch");
382#endif
383
Tim Northover0f140c72016-09-09 11:46:34 +0000384 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000385 .addDef(Res)
386 .addUse(Tst)
387 .addUse(Op0)
388 .addUse(Op1);
389}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000390
Tim Northover0f140c72016-09-09 11:46:34 +0000391void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
392 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000393#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000394 LLT SrcTy = MRI->getType(Src);
395 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000396
397 if (DstTy.isVector()) {
398 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
399 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
400 "different number of elements in a trunc/ext");
401 } else
402 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
403
404 if (IsExtend)
405 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
406 "invalid narrowing extend");
407 else
408 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
409 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000410#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000411}