Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the MachineIRBuidler class. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" |
| 13 | |
| 14 | #include "llvm/CodeGen/MachineFunction.h" |
| 15 | #include "llvm/CodeGen/MachineInstr.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetInstrInfo.h" |
Quentin Colombet | 8fd6718 | 2016-02-11 21:16:56 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetOpcodes.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetSubtargetInfo.h" |
| 21 | |
| 22 | using namespace llvm; |
| 23 | |
Quentin Colombet | 000b580 | 2016-03-11 17:27:51 +0000 | [diff] [blame] | 24 | void MachineIRBuilder::setMF(MachineFunction &MF) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 25 | this->MF = &MF; |
| 26 | this->MBB = nullptr; |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 27 | this->MRI = &MF.getRegInfo(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 28 | this->TII = MF.getSubtarget().getInstrInfo(); |
| 29 | this->DL = DebugLoc(); |
| 30 | this->MI = nullptr; |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 31 | this->InsertedInstr = nullptr; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 34 | void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 35 | this->MBB = &MBB; |
| 36 | Before = Beginning; |
| 37 | assert(&getMF() == MBB.getParent() && |
| 38 | "Basic block is in a different function"); |
| 39 | } |
| 40 | |
| 41 | void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) { |
| 42 | assert(MI.getParent() && "Instruction is not part of a basic block"); |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 43 | setMBB(*MI.getParent()); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 44 | this->MI = &MI; |
| 45 | this->Before = Before; |
| 46 | } |
| 47 | |
| 48 | MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() { |
| 49 | if (MI) { |
| 50 | if (Before) |
| 51 | return MI; |
| 52 | if (!MI->getNextNode()) |
| 53 | return getMBB().end(); |
| 54 | return MI->getNextNode(); |
| 55 | } |
| 56 | return Before ? getMBB().begin() : getMBB().end(); |
| 57 | } |
| 58 | |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 59 | void MachineIRBuilder::recordInsertions( |
| 60 | std::function<void(MachineInstr *)> Inserted) { |
| 61 | InsertedInstr = Inserted; |
| 62 | } |
| 63 | |
| 64 | void MachineIRBuilder::stopRecordingInsertions() { |
| 65 | InsertedInstr = nullptr; |
| 66 | } |
| 67 | |
Quentin Colombet | f9b4934 | 2016-03-11 17:27:58 +0000 | [diff] [blame] | 68 | //------------------------------------------------------------------------------ |
| 69 | // Build instruction variants. |
| 70 | //------------------------------------------------------------------------------ |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 71 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 72 | MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 73 | MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode)); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 74 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 75 | if (InsertedInstr) |
| 76 | InsertedInstr(MIB); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 77 | return MIB; |
Quentin Colombet | 74d7d2f | 2016-02-11 18:53:28 +0000 | [diff] [blame] | 78 | } |
| 79 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 80 | MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 81 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 82 | return buildInstr(TargetOpcode::G_FRAME_INDEX) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 83 | .addDef(Res) |
| 84 | .addFrameIndex(Idx); |
Tim Northover | bd50546 | 2016-07-22 16:59:52 +0000 | [diff] [blame] | 85 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 86 | |
Tim Northover | 032548f | 2016-09-12 12:10:41 +0000 | [diff] [blame^] | 87 | MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res, |
| 88 | const GlobalValue *GV) { |
| 89 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
| 90 | assert(MRI->getType(Res).getAddressSpace() == |
| 91 | GV->getType()->getAddressSpace() && |
| 92 | "address space mismatch"); |
| 93 | |
| 94 | return buildInstr(TargetOpcode::G_GLOBAL_VALUE) |
| 95 | .addDef(Res) |
| 96 | .addGlobalAddress(GV); |
| 97 | } |
| 98 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 99 | MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0, |
| 100 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 101 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 102 | "invalid operand type"); |
| 103 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 104 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 105 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 106 | return buildInstr(TargetOpcode::G_ADD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 107 | .addDef(Res) |
| 108 | .addUse(Op0) |
| 109 | .addUse(Op1); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 112 | MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, |
| 113 | unsigned Op1) { |
| 114 | assert(MRI->getType(Res).isPointer() && |
| 115 | MRI->getType(Res) == MRI->getType(Op0) && "type mismatch"); |
| 116 | assert(MRI->getType(Op1).isScalar() && "invalid offset type"); |
| 117 | |
| 118 | return buildInstr(TargetOpcode::G_GEP) |
| 119 | .addDef(Res) |
| 120 | .addUse(Op0) |
| 121 | .addUse(Op1); |
| 122 | } |
| 123 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 124 | MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0, |
| 125 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 126 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 127 | "invalid operand type"); |
| 128 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 129 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 130 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 131 | return buildInstr(TargetOpcode::G_SUB) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 132 | .addDef(Res) |
| 133 | .addUse(Op0) |
| 134 | .addUse(Op1); |
| 135 | } |
| 136 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 137 | MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0, |
| 138 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 139 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 140 | "invalid operand type"); |
| 141 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 142 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 143 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 144 | return buildInstr(TargetOpcode::G_MUL) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 145 | .addDef(Res) |
| 146 | .addUse(Op0) |
| 147 | .addUse(Op1); |
| 148 | } |
| 149 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 150 | MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 151 | return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 152 | } |
| 153 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 154 | MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) { |
| 155 | return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); |
Tim Northover | 756eca3 | 2016-07-26 16:45:30 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 158 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, int64_t Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 159 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 160 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 161 | return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addImm(Val); |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 162 | } |
| 163 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 164 | MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res, |
| 165 | const ConstantFP &Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 166 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 167 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 168 | return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); |
Tim Northover | b16734f | 2016-08-19 20:09:15 +0000 | [diff] [blame] | 169 | } |
| 170 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 171 | MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 172 | MachineBasicBlock &Dest) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 173 | assert(MRI->getType(Tst).isScalar() && "invalid operand type"); |
| 174 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 175 | return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 176 | } |
| 177 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 178 | MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, |
| 179 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 180 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 181 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 182 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 183 | return buildInstr(TargetOpcode::G_LOAD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 184 | .addDef(Res) |
| 185 | .addUse(Addr) |
| 186 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 187 | } |
| 188 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 189 | MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, |
| 190 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 191 | assert(MRI->getType(Val).isValid() && "invalid operand type"); |
| 192 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 193 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 194 | return buildInstr(TargetOpcode::G_STORE) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 195 | .addUse(Val) |
| 196 | .addUse(Addr) |
| 197 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 198 | } |
| 199 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 200 | MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res, |
| 201 | unsigned CarryOut, |
| 202 | unsigned Op0, unsigned Op1, |
| 203 | unsigned CarryIn) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 204 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 205 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 206 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 207 | assert(MRI->getType(CarryOut).isScalar() && "invalid operand type"); |
| 208 | assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch"); |
| 209 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 210 | return buildInstr(TargetOpcode::G_UADDE) |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 211 | .addDef(Res) |
| 212 | .addDef(CarryOut) |
| 213 | .addUse(Op0) |
| 214 | .addUse(Op1) |
| 215 | .addUse(CarryIn); |
| 216 | } |
| 217 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 218 | MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) { |
| 219 | validateTruncExt(Res, Op, true); |
| 220 | return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 221 | } |
| 222 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 223 | MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) { |
| 224 | validateTruncExt(Res, Op, true); |
| 225 | return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 228 | MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) { |
| 229 | validateTruncExt(Res, Op, true); |
| 230 | return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 231 | } |
| 232 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 233 | MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res, |
| 234 | unsigned Op) { |
| 235 | unsigned Opcode = TargetOpcode::COPY; |
| 236 | if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits()) |
| 237 | Opcode = TargetOpcode::G_SEXT; |
| 238 | else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits()) |
| 239 | Opcode = TargetOpcode::G_TRUNC; |
| 240 | |
| 241 | return buildInstr(Opcode).addDef(Res).addUse(Op); |
| 242 | } |
| 243 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 244 | MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results, |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 245 | ArrayRef<uint64_t> Indices, |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 246 | unsigned Src) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 247 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 248 | assert(Results.size() == Indices.size() && "inconsistent number of regs"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 249 | assert(!Results.empty() && "invalid trivial extract"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 250 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 251 | "extract offsets must be in ascending order"); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 252 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 253 | assert(MRI->getType(Src).isValid() && "invalid operand type"); |
| 254 | for (auto Res : Results) |
| 255 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 256 | #endif |
| 257 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 258 | auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT)); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 259 | for (auto Res : Results) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 260 | MIB.addDef(Res); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 261 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 262 | MIB.addUse(Src); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 263 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 264 | for (auto Idx : Indices) |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 265 | MIB.addImm(Idx); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 266 | |
| 267 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 268 | if (InsertedInstr) |
| 269 | InsertedInstr(MIB); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 270 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 271 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 272 | } |
| 273 | |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 274 | MachineInstrBuilder |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 275 | MachineIRBuilder::buildSequence(unsigned Res, |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 276 | ArrayRef<unsigned> Ops, |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 277 | ArrayRef<unsigned> Indices) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 278 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 279 | assert(Ops.size() == Indices.size() && "incompatible args"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 280 | assert(!Ops.empty() && "invalid trivial sequence"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 281 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 282 | "sequence offsets must be in ascending order"); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 283 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 284 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 285 | for (auto Op : Ops) |
| 286 | assert(MRI->getType(Op).isValid() && "invalid operand type"); |
| 287 | #endif |
| 288 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 289 | MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 290 | MIB.addDef(Res); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 291 | for (unsigned i = 0; i < Ops.size(); ++i) { |
| 292 | MIB.addUse(Ops[i]); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 293 | MIB.addImm(Indices[i]); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 294 | } |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 295 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 296 | } |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 297 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 298 | MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 299 | unsigned Res, |
| 300 | bool HasSideEffects) { |
| 301 | auto MIB = |
| 302 | buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 303 | : TargetOpcode::G_INTRINSIC); |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 304 | if (Res) |
| 305 | MIB.addDef(Res); |
| 306 | MIB.addIntrinsicID(ID); |
| 307 | return MIB; |
| 308 | } |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 309 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 310 | MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) { |
| 311 | validateTruncExt(Res, Op, false); |
| 312 | return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 313 | } |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 314 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 315 | MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) { |
| 316 | validateTruncExt(Res, Op, false); |
| 317 | return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); |
Tim Northover | a11be04 | 2016-08-19 22:40:08 +0000 | [diff] [blame] | 318 | } |
| 319 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 320 | MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 321 | unsigned Res, unsigned Op0, |
| 322 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 323 | #ifndef NDEBUG |
| 324 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 325 | "invalid operand type"); |
| 326 | assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch"); |
| 327 | assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); |
| 328 | if (MRI->getType(Op0).isScalar()) |
| 329 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 330 | else |
| 331 | assert(MRI->getType(Res).isVector() && |
| 332 | MRI->getType(Res).getNumElements() == |
| 333 | MRI->getType(Op0).getNumElements() && |
| 334 | "type mismatch"); |
| 335 | #endif |
| 336 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 337 | return buildInstr(TargetOpcode::G_ICMP) |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 338 | .addDef(Res) |
| 339 | .addPredicate(Pred) |
| 340 | .addUse(Op0) |
| 341 | .addUse(Op1); |
| 342 | } |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 343 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 344 | MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 345 | unsigned Res, unsigned Op0, |
| 346 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 347 | #ifndef NDEBUG |
| 348 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 349 | "invalid operand type"); |
| 350 | assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch"); |
| 351 | assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); |
| 352 | if (MRI->getType(Op0).isScalar()) |
| 353 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 354 | else |
| 355 | assert(MRI->getType(Res).isVector() && |
| 356 | MRI->getType(Res).getNumElements() == |
| 357 | MRI->getType(Op0).getNumElements() && |
| 358 | "type mismatch"); |
| 359 | #endif |
| 360 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 361 | return buildInstr(TargetOpcode::G_FCMP) |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 362 | .addDef(Res) |
| 363 | .addPredicate(Pred) |
| 364 | .addUse(Op0) |
| 365 | .addUse(Op1); |
| 366 | } |
| 367 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 368 | MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst, |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 369 | unsigned Op0, unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 370 | #ifndef NDEBUG |
| 371 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 372 | "invalid operand type"); |
| 373 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 374 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 375 | if (MRI->getType(Res).isScalar()) |
| 376 | assert(MRI->getType(Tst).isScalar() && "type mismatch"); |
| 377 | else |
| 378 | assert(MRI->getType(Tst).isVector() && |
| 379 | MRI->getType(Tst).getNumElements() == |
| 380 | MRI->getType(Op0).getNumElements() && |
| 381 | "type mismatch"); |
| 382 | #endif |
| 383 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 384 | return buildInstr(TargetOpcode::G_SELECT) |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 385 | .addDef(Res) |
| 386 | .addUse(Tst) |
| 387 | .addUse(Op0) |
| 388 | .addUse(Op1); |
| 389 | } |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 390 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 391 | void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src, |
| 392 | bool IsExtend) { |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 393 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 394 | LLT SrcTy = MRI->getType(Src); |
| 395 | LLT DstTy = MRI->getType(Dst); |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 396 | |
| 397 | if (DstTy.isVector()) { |
| 398 | assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector"); |
| 399 | assert(SrcTy.getNumElements() == DstTy.getNumElements() && |
| 400 | "different number of elements in a trunc/ext"); |
| 401 | } else |
| 402 | assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc"); |
| 403 | |
| 404 | if (IsExtend) |
| 405 | assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() && |
| 406 | "invalid narrowing extend"); |
| 407 | else |
| 408 | assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() && |
| 409 | "invalid widening trunc"); |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 410 | #endif |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 411 | } |