Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the MachineIRBuidler class. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" |
| 13 | |
| 14 | #include "llvm/CodeGen/MachineFunction.h" |
| 15 | #include "llvm/CodeGen/MachineInstr.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetInstrInfo.h" |
Quentin Colombet | 8fd6718 | 2016-02-11 21:16:56 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetOpcodes.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetSubtargetInfo.h" |
| 21 | |
| 22 | using namespace llvm; |
| 23 | |
Quentin Colombet | 000b580 | 2016-03-11 17:27:51 +0000 | [diff] [blame] | 24 | void MachineIRBuilder::setMF(MachineFunction &MF) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 25 | this->MF = &MF; |
| 26 | this->MBB = nullptr; |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 27 | this->MRI = &MF.getRegInfo(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 28 | this->TII = MF.getSubtarget().getInstrInfo(); |
| 29 | this->DL = DebugLoc(); |
| 30 | this->MI = nullptr; |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 31 | this->InsertedInstr = nullptr; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 34 | void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 35 | this->MBB = &MBB; |
| 36 | Before = Beginning; |
| 37 | assert(&getMF() == MBB.getParent() && |
| 38 | "Basic block is in a different function"); |
| 39 | } |
| 40 | |
| 41 | void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) { |
| 42 | assert(MI.getParent() && "Instruction is not part of a basic block"); |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 43 | setMBB(*MI.getParent()); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 44 | this->MI = &MI; |
| 45 | this->Before = Before; |
| 46 | } |
| 47 | |
| 48 | MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() { |
| 49 | if (MI) { |
| 50 | if (Before) |
| 51 | return MI; |
| 52 | if (!MI->getNextNode()) |
| 53 | return getMBB().end(); |
| 54 | return MI->getNextNode(); |
| 55 | } |
| 56 | return Before ? getMBB().begin() : getMBB().end(); |
| 57 | } |
| 58 | |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 59 | void MachineIRBuilder::recordInsertions( |
| 60 | std::function<void(MachineInstr *)> Inserted) { |
| 61 | InsertedInstr = Inserted; |
| 62 | } |
| 63 | |
| 64 | void MachineIRBuilder::stopRecordingInsertions() { |
| 65 | InsertedInstr = nullptr; |
| 66 | } |
| 67 | |
Quentin Colombet | f9b4934 | 2016-03-11 17:27:58 +0000 | [diff] [blame] | 68 | //------------------------------------------------------------------------------ |
| 69 | // Build instruction variants. |
| 70 | //------------------------------------------------------------------------------ |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 71 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 72 | MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 73 | MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode)); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 74 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 75 | if (InsertedInstr) |
| 76 | InsertedInstr(MIB); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 77 | return MIB; |
Quentin Colombet | 74d7d2f | 2016-02-11 18:53:28 +0000 | [diff] [blame] | 78 | } |
| 79 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 80 | MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 81 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 82 | return buildInstr(TargetOpcode::G_FRAME_INDEX) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 83 | .addDef(Res) |
| 84 | .addFrameIndex(Idx); |
Tim Northover | bd50546 | 2016-07-22 16:59:52 +0000 | [diff] [blame] | 85 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 86 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 87 | MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0, |
| 88 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 89 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 90 | "invalid operand type"); |
| 91 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 92 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 93 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 94 | return buildInstr(TargetOpcode::G_ADD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 95 | .addDef(Res) |
| 96 | .addUse(Op0) |
| 97 | .addUse(Op1); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame^] | 100 | MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, |
| 101 | unsigned Op1) { |
| 102 | assert(MRI->getType(Res).isPointer() && |
| 103 | MRI->getType(Res) == MRI->getType(Op0) && "type mismatch"); |
| 104 | assert(MRI->getType(Op1).isScalar() && "invalid offset type"); |
| 105 | |
| 106 | return buildInstr(TargetOpcode::G_GEP) |
| 107 | .addDef(Res) |
| 108 | .addUse(Op0) |
| 109 | .addUse(Op1); |
| 110 | } |
| 111 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 112 | MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0, |
| 113 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 114 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 115 | "invalid operand type"); |
| 116 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 117 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 118 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 119 | return buildInstr(TargetOpcode::G_SUB) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 120 | .addDef(Res) |
| 121 | .addUse(Op0) |
| 122 | .addUse(Op1); |
| 123 | } |
| 124 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 125 | MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0, |
| 126 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 127 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 128 | "invalid operand type"); |
| 129 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 130 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 131 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 132 | return buildInstr(TargetOpcode::G_MUL) |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 133 | .addDef(Res) |
| 134 | .addUse(Op0) |
| 135 | .addUse(Op1); |
| 136 | } |
| 137 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 138 | MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 139 | return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 140 | } |
| 141 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 142 | MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) { |
| 143 | return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); |
Tim Northover | 756eca3 | 2016-07-26 16:45:30 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 146 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, int64_t Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 147 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 148 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 149 | return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addImm(Val); |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 150 | } |
| 151 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 152 | MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res, |
| 153 | const ConstantFP &Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 154 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 155 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 156 | return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); |
Tim Northover | b16734f | 2016-08-19 20:09:15 +0000 | [diff] [blame] | 157 | } |
| 158 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 159 | MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 160 | MachineBasicBlock &Dest) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 161 | assert(MRI->getType(Tst).isScalar() && "invalid operand type"); |
| 162 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 163 | return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 164 | } |
| 165 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 166 | MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, |
| 167 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 168 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 169 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 170 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 171 | return buildInstr(TargetOpcode::G_LOAD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 172 | .addDef(Res) |
| 173 | .addUse(Addr) |
| 174 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 175 | } |
| 176 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 177 | MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, |
| 178 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 179 | assert(MRI->getType(Val).isValid() && "invalid operand type"); |
| 180 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 181 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 182 | return buildInstr(TargetOpcode::G_STORE) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 183 | .addUse(Val) |
| 184 | .addUse(Addr) |
| 185 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 186 | } |
| 187 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 188 | MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res, |
| 189 | unsigned CarryOut, |
| 190 | unsigned Op0, unsigned Op1, |
| 191 | unsigned CarryIn) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 192 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 193 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 194 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 195 | assert(MRI->getType(CarryOut).isScalar() && "invalid operand type"); |
| 196 | assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch"); |
| 197 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 198 | return buildInstr(TargetOpcode::G_UADDE) |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 199 | .addDef(Res) |
| 200 | .addDef(CarryOut) |
| 201 | .addUse(Op0) |
| 202 | .addUse(Op1) |
| 203 | .addUse(CarryIn); |
| 204 | } |
| 205 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 206 | MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) { |
| 207 | validateTruncExt(Res, Op, true); |
| 208 | return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 211 | MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) { |
| 212 | validateTruncExt(Res, Op, true); |
| 213 | return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 214 | } |
| 215 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 216 | MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) { |
| 217 | validateTruncExt(Res, Op, true); |
| 218 | return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame^] | 221 | MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res, |
| 222 | unsigned Op) { |
| 223 | unsigned Opcode = TargetOpcode::COPY; |
| 224 | if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits()) |
| 225 | Opcode = TargetOpcode::G_SEXT; |
| 226 | else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits()) |
| 227 | Opcode = TargetOpcode::G_TRUNC; |
| 228 | |
| 229 | return buildInstr(Opcode).addDef(Res).addUse(Op); |
| 230 | } |
| 231 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 232 | MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results, |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 233 | ArrayRef<uint64_t> Indices, |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 234 | unsigned Src) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 235 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 236 | assert(Results.size() == Indices.size() && "inconsistent number of regs"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 237 | assert(!Results.empty() && "invalid trivial extract"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 238 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 239 | "extract offsets must be in ascending order"); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 240 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 241 | assert(MRI->getType(Src).isValid() && "invalid operand type"); |
| 242 | for (auto Res : Results) |
| 243 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 244 | #endif |
| 245 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 246 | auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT)); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 247 | for (auto Res : Results) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 248 | MIB.addDef(Res); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 249 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 250 | MIB.addUse(Src); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 251 | |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 252 | for (auto Idx : Indices) |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 253 | MIB.addImm(Idx); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 254 | |
| 255 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 256 | if (InsertedInstr) |
| 257 | InsertedInstr(MIB); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 258 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 259 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 262 | MachineInstrBuilder |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 263 | MachineIRBuilder::buildSequence(unsigned Res, |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 264 | ArrayRef<unsigned> Ops, |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 265 | ArrayRef<unsigned> Indices) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 266 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 267 | assert(Ops.size() == Indices.size() && "incompatible args"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 268 | assert(!Ops.empty() && "invalid trivial sequence"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 269 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 270 | "sequence offsets must be in ascending order"); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 271 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 272 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 273 | for (auto Op : Ops) |
| 274 | assert(MRI->getType(Op).isValid() && "invalid operand type"); |
| 275 | #endif |
| 276 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 277 | MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 278 | MIB.addDef(Res); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 279 | for (unsigned i = 0; i < Ops.size(); ++i) { |
| 280 | MIB.addUse(Ops[i]); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 281 | MIB.addImm(Indices[i]); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 282 | } |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 283 | return MIB; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 284 | } |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 285 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 286 | MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 287 | unsigned Res, |
| 288 | bool HasSideEffects) { |
| 289 | auto MIB = |
| 290 | buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 291 | : TargetOpcode::G_INTRINSIC); |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 292 | if (Res) |
| 293 | MIB.addDef(Res); |
| 294 | MIB.addIntrinsicID(ID); |
| 295 | return MIB; |
| 296 | } |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 297 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 298 | MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) { |
| 299 | validateTruncExt(Res, Op, false); |
| 300 | return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 301 | } |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 302 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 303 | MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) { |
| 304 | validateTruncExt(Res, Op, false); |
| 305 | return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); |
Tim Northover | a11be04 | 2016-08-19 22:40:08 +0000 | [diff] [blame] | 306 | } |
| 307 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 308 | MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 309 | unsigned Res, unsigned Op0, |
| 310 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 311 | #ifndef NDEBUG |
| 312 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 313 | "invalid operand type"); |
| 314 | assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch"); |
| 315 | assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); |
| 316 | if (MRI->getType(Op0).isScalar()) |
| 317 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 318 | else |
| 319 | assert(MRI->getType(Res).isVector() && |
| 320 | MRI->getType(Res).getNumElements() == |
| 321 | MRI->getType(Op0).getNumElements() && |
| 322 | "type mismatch"); |
| 323 | #endif |
| 324 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 325 | return buildInstr(TargetOpcode::G_ICMP) |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 326 | .addDef(Res) |
| 327 | .addPredicate(Pred) |
| 328 | .addUse(Op0) |
| 329 | .addUse(Op1); |
| 330 | } |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 331 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 332 | MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 333 | unsigned Res, unsigned Op0, |
| 334 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 335 | #ifndef NDEBUG |
| 336 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 337 | "invalid operand type"); |
| 338 | assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch"); |
| 339 | assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); |
| 340 | if (MRI->getType(Op0).isScalar()) |
| 341 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 342 | else |
| 343 | assert(MRI->getType(Res).isVector() && |
| 344 | MRI->getType(Res).getNumElements() == |
| 345 | MRI->getType(Op0).getNumElements() && |
| 346 | "type mismatch"); |
| 347 | #endif |
| 348 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 349 | return buildInstr(TargetOpcode::G_FCMP) |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 350 | .addDef(Res) |
| 351 | .addPredicate(Pred) |
| 352 | .addUse(Op0) |
| 353 | .addUse(Op1); |
| 354 | } |
| 355 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 356 | MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst, |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 357 | unsigned Op0, unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 358 | #ifndef NDEBUG |
| 359 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 360 | "invalid operand type"); |
| 361 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 362 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 363 | if (MRI->getType(Res).isScalar()) |
| 364 | assert(MRI->getType(Tst).isScalar() && "type mismatch"); |
| 365 | else |
| 366 | assert(MRI->getType(Tst).isVector() && |
| 367 | MRI->getType(Tst).getNumElements() == |
| 368 | MRI->getType(Op0).getNumElements() && |
| 369 | "type mismatch"); |
| 370 | #endif |
| 371 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 372 | return buildInstr(TargetOpcode::G_SELECT) |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 373 | .addDef(Res) |
| 374 | .addUse(Tst) |
| 375 | .addUse(Op0) |
| 376 | .addUse(Op1); |
| 377 | } |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 378 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 379 | void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src, |
| 380 | bool IsExtend) { |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 381 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 382 | LLT SrcTy = MRI->getType(Src); |
| 383 | LLT DstTy = MRI->getType(Dst); |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 384 | |
| 385 | if (DstTy.isVector()) { |
| 386 | assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector"); |
| 387 | assert(SrcTy.getNumElements() == DstTy.getNumElements() && |
| 388 | "different number of elements in a trunc/ext"); |
| 389 | } else |
| 390 | assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc"); |
| 391 | |
| 392 | if (IsExtend) |
| 393 | assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() && |
| 394 | "invalid narrowing extend"); |
| 395 | else |
| 396 | assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() && |
| 397 | "invalid widening trunc"); |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 398 | #endif |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 399 | } |