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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000018#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000019#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000020#include "llvm/Target/TargetSubtargetInfo.h"
21
22using namespace llvm;
23
Quentin Colombet000b5802016-03-11 17:27:51 +000024void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000025 this->MF = &MF;
26 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000027 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000028 this->TII = MF.getSubtarget().getInstrInfo();
29 this->DL = DebugLoc();
30 this->MI = nullptr;
Tim Northover438c77c2016-08-25 17:37:32 +000031 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000032}
33
Quentin Colombet91ebd712016-03-11 17:27:47 +000034void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000035 this->MBB = &MBB;
36 Before = Beginning;
37 assert(&getMF() == MBB.getParent() &&
38 "Basic block is in a different function");
39}
40
41void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
42 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000043 setMBB(*MI.getParent());
Quentin Colombet2ad1f852016-02-11 17:44:59 +000044 this->MI = &MI;
45 this->Before = Before;
46}
47
48MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
49 if (MI) {
50 if (Before)
51 return MI;
52 if (!MI->getNextNode())
53 return getMBB().end();
54 return MI->getNextNode();
55 }
56 return Before ? getMBB().begin() : getMBB().end();
57}
58
Tim Northover438c77c2016-08-25 17:37:32 +000059void MachineIRBuilder::recordInsertions(
60 std::function<void(MachineInstr *)> Inserted) {
61 InsertedInstr = Inserted;
62}
63
64void MachineIRBuilder::stopRecordingInsertions() {
65 InsertedInstr = nullptr;
66}
67
Quentin Colombetf9b49342016-03-11 17:27:58 +000068//------------------------------------------------------------------------------
69// Build instruction variants.
70//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000071
Tim Northover0f140c72016-09-09 11:46:34 +000072MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000073 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera51575f2016-07-29 17:43:52 +000074 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000075 if (InsertedInstr)
76 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000077 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000078}
79
Tim Northover0f140c72016-09-09 11:46:34 +000080MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +000081 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +000082 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +000083 .addDef(Res)
84 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +000085}
Tim Northover33b07d62016-07-22 20:03:43 +000086
Tim Northover0f140c72016-09-09 11:46:34 +000087MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
88 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +000089 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
90 "invalid operand type");
91 assert(MRI->getType(Res) == MRI->getType(Op0) &&
92 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
93
Tim Northover0f140c72016-09-09 11:46:34 +000094 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +000095 .addDef(Res)
96 .addUse(Op0)
97 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +000098}
99
Tim Northovera7653b32016-09-12 11:20:22 +0000100MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
101 unsigned Op1) {
102 assert(MRI->getType(Res).isPointer() &&
103 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
104 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
105
106 return buildInstr(TargetOpcode::G_GEP)
107 .addDef(Res)
108 .addUse(Op0)
109 .addUse(Op1);
110}
111
Tim Northover0f140c72016-09-09 11:46:34 +0000112MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
113 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000114 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
115 "invalid operand type");
116 assert(MRI->getType(Res) == MRI->getType(Op0) &&
117 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
118
Tim Northover0f140c72016-09-09 11:46:34 +0000119 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000120 .addDef(Res)
121 .addUse(Op0)
122 .addUse(Op1);
123}
124
Tim Northover0f140c72016-09-09 11:46:34 +0000125MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
126 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000127 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
128 "invalid operand type");
129 assert(MRI->getType(Res) == MRI->getType(Op0) &&
130 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
131
Tim Northover0f140c72016-09-09 11:46:34 +0000132 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000133 .addDef(Res)
134 .addUse(Op0)
135 .addUse(Op1);
136}
137
Tim Northovera51575f2016-07-29 17:43:52 +0000138MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000139 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000140}
141
Tim Northovera51575f2016-07-29 17:43:52 +0000142MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
143 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000144}
145
Tim Northover0f140c72016-09-09 11:46:34 +0000146MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, int64_t Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000147 assert(MRI->getType(Res).isScalar() && "invalid operand type");
148
Tim Northover0f140c72016-09-09 11:46:34 +0000149 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addImm(Val);
Tim Northover9656f142016-08-04 20:54:13 +0000150}
151
Tim Northover0f140c72016-09-09 11:46:34 +0000152MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
153 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000154 assert(MRI->getType(Res).isScalar() && "invalid operand type");
155
Tim Northover0f140c72016-09-09 11:46:34 +0000156 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000157}
158
Tim Northover0f140c72016-09-09 11:46:34 +0000159MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000160 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000161 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
162
Tim Northover0f140c72016-09-09 11:46:34 +0000163 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000164}
165
Tim Northover0f140c72016-09-09 11:46:34 +0000166MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
167 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000168 assert(MRI->getType(Res).isValid() && "invalid operand type");
169 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
170
Tim Northover0f140c72016-09-09 11:46:34 +0000171 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000172 .addDef(Res)
173 .addUse(Addr)
174 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000175}
176
Tim Northover0f140c72016-09-09 11:46:34 +0000177MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
178 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000179 assert(MRI->getType(Val).isValid() && "invalid operand type");
180 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
181
Tim Northover0f140c72016-09-09 11:46:34 +0000182 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000183 .addUse(Val)
184 .addUse(Addr)
185 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000186}
187
Tim Northover0f140c72016-09-09 11:46:34 +0000188MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
189 unsigned CarryOut,
190 unsigned Op0, unsigned Op1,
191 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000192 assert(MRI->getType(Res).isScalar() && "invalid operand type");
193 assert(MRI->getType(Res) == MRI->getType(Op0) &&
194 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
195 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
196 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
197
Tim Northover0f140c72016-09-09 11:46:34 +0000198 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000199 .addDef(Res)
200 .addDef(CarryOut)
201 .addUse(Op0)
202 .addUse(Op1)
203 .addUse(CarryIn);
204}
205
Tim Northover0f140c72016-09-09 11:46:34 +0000206MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
207 validateTruncExt(Res, Op, true);
208 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000209}
210
Tim Northover0f140c72016-09-09 11:46:34 +0000211MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
212 validateTruncExt(Res, Op, true);
213 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000214}
215
Tim Northover0f140c72016-09-09 11:46:34 +0000216MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
217 validateTruncExt(Res, Op, true);
218 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000219}
220
Tim Northovera7653b32016-09-12 11:20:22 +0000221MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
222 unsigned Op) {
223 unsigned Opcode = TargetOpcode::COPY;
224 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
225 Opcode = TargetOpcode::G_SEXT;
226 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
227 Opcode = TargetOpcode::G_TRUNC;
228
229 return buildInstr(Opcode).addDef(Res).addUse(Op);
230}
231
Tim Northover0f140c72016-09-09 11:46:34 +0000232MachineInstrBuilder MachineIRBuilder::buildExtract(ArrayRef<unsigned> Results,
Tim Northover26b76f22016-08-19 18:32:14 +0000233 ArrayRef<uint64_t> Indices,
Tim Northover0f140c72016-09-09 11:46:34 +0000234 unsigned Src) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000235#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000236 assert(Results.size() == Indices.size() && "inconsistent number of regs");
Tim Northover26b76f22016-08-19 18:32:14 +0000237 assert(!Results.empty() && "invalid trivial extract");
Tim Northover991b12b2016-08-30 20:51:25 +0000238 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
239 "extract offsets must be in ascending order");
Tim Northover33b07d62016-07-22 20:03:43 +0000240
Tim Northover1f8b1db2016-09-09 11:46:58 +0000241 assert(MRI->getType(Src).isValid() && "invalid operand type");
242 for (auto Res : Results)
243 assert(MRI->getType(Res).isValid() && "invalid operand type");
244#endif
245
Tim Northover26b76f22016-08-19 18:32:14 +0000246 auto MIB = BuildMI(getMF(), DL, getTII().get(TargetOpcode::G_EXTRACT));
Tim Northover33b07d62016-07-22 20:03:43 +0000247 for (auto Res : Results)
Tim Northovera51575f2016-07-29 17:43:52 +0000248 MIB.addDef(Res);
Tim Northover33b07d62016-07-22 20:03:43 +0000249
Tim Northovera51575f2016-07-29 17:43:52 +0000250 MIB.addUse(Src);
Tim Northover33b07d62016-07-22 20:03:43 +0000251
Tim Northover26b76f22016-08-19 18:32:14 +0000252 for (auto Idx : Indices)
Tim Northover33b07d62016-07-22 20:03:43 +0000253 MIB.addImm(Idx);
Tim Northover26b76f22016-08-19 18:32:14 +0000254
255 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +0000256 if (InsertedInstr)
257 InsertedInstr(MIB);
Tim Northover26b76f22016-08-19 18:32:14 +0000258
Tim Northovera51575f2016-07-29 17:43:52 +0000259 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000260}
261
Tim Northover91c81732016-08-19 17:17:06 +0000262MachineInstrBuilder
Tim Northover0f140c72016-09-09 11:46:34 +0000263MachineIRBuilder::buildSequence(unsigned Res,
Tim Northover91c81732016-08-19 17:17:06 +0000264 ArrayRef<unsigned> Ops,
Tim Northover26b76f22016-08-19 18:32:14 +0000265 ArrayRef<unsigned> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000266#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000267 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000268 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000269 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
270 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000271
Tim Northover1f8b1db2016-09-09 11:46:58 +0000272 assert(MRI->getType(Res).isValid() && "invalid operand type");
273 for (auto Op : Ops)
274 assert(MRI->getType(Op).isValid() && "invalid operand type");
275#endif
276
Tim Northover0f140c72016-09-09 11:46:34 +0000277 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE);
Tim Northovera51575f2016-07-29 17:43:52 +0000278 MIB.addDef(Res);
Tim Northover91c81732016-08-19 17:17:06 +0000279 for (unsigned i = 0; i < Ops.size(); ++i) {
280 MIB.addUse(Ops[i]);
Tim Northover26b76f22016-08-19 18:32:14 +0000281 MIB.addImm(Indices[i]);
Tim Northover91c81732016-08-19 17:17:06 +0000282 }
Tim Northovera51575f2016-07-29 17:43:52 +0000283 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000284}
Tim Northover5fb414d2016-07-29 22:32:36 +0000285
Tim Northover0f140c72016-09-09 11:46:34 +0000286MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000287 unsigned Res,
288 bool HasSideEffects) {
289 auto MIB =
290 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000291 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000292 if (Res)
293 MIB.addDef(Res);
294 MIB.addIntrinsicID(ID);
295 return MIB;
296}
Tim Northover32335812016-08-04 18:35:11 +0000297
Tim Northover0f140c72016-09-09 11:46:34 +0000298MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
299 validateTruncExt(Res, Op, false);
300 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000301}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000302
Tim Northover0f140c72016-09-09 11:46:34 +0000303MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
304 validateTruncExt(Res, Op, false);
305 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000306}
307
Tim Northover0f140c72016-09-09 11:46:34 +0000308MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000309 unsigned Res, unsigned Op0,
310 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000311#ifndef NDEBUG
312 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
313 "invalid operand type");
314 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
315 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
316 if (MRI->getType(Op0).isScalar())
317 assert(MRI->getType(Res).isScalar() && "type mismatch");
318 else
319 assert(MRI->getType(Res).isVector() &&
320 MRI->getType(Res).getNumElements() ==
321 MRI->getType(Op0).getNumElements() &&
322 "type mismatch");
323#endif
324
Tim Northover0f140c72016-09-09 11:46:34 +0000325 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000326 .addDef(Res)
327 .addPredicate(Pred)
328 .addUse(Op0)
329 .addUse(Op1);
330}
Tim Northover5a28c362016-08-19 20:09:07 +0000331
Tim Northover0f140c72016-09-09 11:46:34 +0000332MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000333 unsigned Res, unsigned Op0,
334 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000335#ifndef NDEBUG
336 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
337 "invalid operand type");
338 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
339 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
340 if (MRI->getType(Op0).isScalar())
341 assert(MRI->getType(Res).isScalar() && "type mismatch");
342 else
343 assert(MRI->getType(Res).isVector() &&
344 MRI->getType(Res).getNumElements() ==
345 MRI->getType(Op0).getNumElements() &&
346 "type mismatch");
347#endif
348
Tim Northover0f140c72016-09-09 11:46:34 +0000349 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000350 .addDef(Res)
351 .addPredicate(Pred)
352 .addUse(Op0)
353 .addUse(Op1);
354}
355
Tim Northover0f140c72016-09-09 11:46:34 +0000356MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000357 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000358#ifndef NDEBUG
359 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
360 "invalid operand type");
361 assert(MRI->getType(Res) == MRI->getType(Op0) &&
362 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
363 if (MRI->getType(Res).isScalar())
364 assert(MRI->getType(Tst).isScalar() && "type mismatch");
365 else
366 assert(MRI->getType(Tst).isVector() &&
367 MRI->getType(Tst).getNumElements() ==
368 MRI->getType(Op0).getNumElements() &&
369 "type mismatch");
370#endif
371
Tim Northover0f140c72016-09-09 11:46:34 +0000372 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000373 .addDef(Res)
374 .addUse(Tst)
375 .addUse(Op0)
376 .addUse(Op1);
377}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000378
Tim Northover0f140c72016-09-09 11:46:34 +0000379void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
380 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000381#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000382 LLT SrcTy = MRI->getType(Src);
383 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000384
385 if (DstTy.isVector()) {
386 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
387 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
388 "different number of elements in a trunc/ext");
389 } else
390 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
391
392 if (IsExtend)
393 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
394 "invalid narrowing extend");
395 else
396 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
397 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000398#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000399}