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Jia Liub22310f2012-02-18 12:03:15 +00001//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicum1213a7a2011-12-12 21:14:40 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000014#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
Tony Linthicum1213a7a2011-12-12 21:14:40 +000016
Craig Topperb25fda92012-03-17 18:46:09 +000017#include "HexagonRegisterInfo.h"
Brendon Cahoon6f358372012-02-08 18:25:47 +000018#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma1d297502013-05-02 15:39:30 +000019#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +000020#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicum1213a7a2011-12-12 21:14:40 +000022
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
Patrik Hagglund8d09a6c2014-03-15 09:11:41 +000028struct EVT;
Eric Christopher234a1ec2015-03-12 06:07:16 +000029class HexagonSubtarget;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000030class HexagonInstrInfo : public HexagonGenInstrInfo {
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +000031 virtual void anchor();
Tony Linthicum1213a7a2011-12-12 21:14:40 +000032 const HexagonRegisterInfo RI;
Bill Wendling4a7a4082013-06-07 06:19:56 +000033 const HexagonSubtarget &Subtarget;
Jyotsna Verma5ed51812013-05-01 21:37:34 +000034 typedef unsigned Opcode_t;
35
Tony Linthicum1213a7a2011-12-12 21:14:40 +000036public:
37 explicit HexagonInstrInfo(HexagonSubtarget &ST);
38
39 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
40 /// such, whenever a client has an instance of instruction info, it should
41 /// always be able to get register info as well (through this method).
42 ///
Craig Topper906c2cd2014-04-29 07:58:16 +000043 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
Tony Linthicum1213a7a2011-12-12 21:14:40 +000044
45 /// isLoadFromStackSlot - If the specified machine instruction is a direct
46 /// load from a stack slot, return the virtual or physical register number of
47 /// the destination along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than loading from the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +000050 unsigned isLoadFromStackSlot(const MachineInstr *MI,
51 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000052
53 /// isStoreToStackSlot - If the specified machine instruction is a direct
54 /// store to a stack slot, return the virtual or physical register number of
55 /// the source reg along with the FrameIndex of the loaded stack slot. If
56 /// not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than storing to the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +000058 unsigned isStoreToStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000060
61
Craig Topper906c2cd2014-04-29 07:58:16 +000062 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
63 MachineBasicBlock *&FBB,
64 SmallVectorImpl<MachineOperand> &Cond,
65 bool AllowModify) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000066
Craig Topper906c2cd2014-04-29 07:58:16 +000067 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000068
Craig Topper906c2cd2014-04-29 07:58:16 +000069 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
70 MachineBasicBlock *FBB,
71 const SmallVectorImpl<MachineOperand> &Cond,
72 DebugLoc DL) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000073
Craig Topper906c2cd2014-04-29 07:58:16 +000074 bool analyzeCompare(const MachineInstr *MI,
75 unsigned &SrcReg, unsigned &SrcReg2,
76 int &Mask, int &Value) const override;
Krzysztof Parzyszekcfe285e2013-02-11 20:04:29 +000077
Craig Topper906c2cd2014-04-29 07:58:16 +000078 void copyPhysReg(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator I, DebugLoc DL,
80 unsigned DestReg, unsigned SrcReg,
81 bool KillSrc) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000082
Craig Topper906c2cd2014-04-29 07:58:16 +000083 void storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned SrcReg, bool isKill, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000088
Craig Topper906c2cd2014-04-29 07:58:16 +000089 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
90 SmallVectorImpl<MachineOperand> &Addr,
91 const TargetRegisterClass *RC,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000093
Craig Topper906c2cd2014-04-29 07:58:16 +000094 void loadRegFromStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI,
96 unsigned DestReg, int FrameIndex,
97 const TargetRegisterClass *RC,
98 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +000099
Craig Topper906c2cd2014-04-29 07:58:16 +0000100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
101 SmallVectorImpl<MachineOperand> &Addr,
102 const TargetRegisterClass *RC,
103 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000104
Colin LeMahieu7b1799c2015-03-09 22:05:21 +0000105 /// expandPostRAPseudo - This function is called for all pseudo instructions
106 /// that remain after register allocation. Many pseudo instructions are
107 /// created to help register allocation. This is the place to convert them
108 /// into real instructions. The target can edit MI in place, or it can insert
109 /// new instructions and erase MI. The function should return true if
110 /// anything was changed.
111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
112
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000113 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
114 ArrayRef<unsigned> Ops,
Craig Topper906c2cd2014-04-29 07:58:16 +0000115 int FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000116
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000117 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
118 ArrayRef<unsigned> Ops,
119 MachineInstr *LoadMI) const override {
Craig Toppere73658d2014-04-28 04:05:08 +0000120 return nullptr;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000121 }
122
123 unsigned createVR(MachineFunction* MF, MVT VT) const;
124
Craig Topper906c2cd2014-04-29 07:58:16 +0000125 bool isBranch(const MachineInstr *MI) const;
126 bool isPredicable(MachineInstr *MI) const override;
127 bool PredicateInstruction(MachineInstr *MI,
128 const SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000129
Craig Topper906c2cd2014-04-29 07:58:16 +0000130 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
131 unsigned ExtraPredCycles,
132 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000133
Craig Topper906c2cd2014-04-29 07:58:16 +0000134 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
135 unsigned NumTCycles, unsigned ExtraTCycles,
136 MachineBasicBlock &FMBB,
137 unsigned NumFCycles, unsigned ExtraFCycles,
138 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000139
Craig Topper906c2cd2014-04-29 07:58:16 +0000140 bool isPredicated(const MachineInstr *MI) const override;
141 bool isPredicated(unsigned Opcode) const;
142 bool isPredicatedTrue(const MachineInstr *MI) const;
143 bool isPredicatedTrue(unsigned Opcode) const;
144 bool isPredicatedNew(const MachineInstr *MI) const;
145 bool isPredicatedNew(unsigned Opcode) const;
146 bool DefinesPredicate(MachineInstr *MI,
147 std::vector<MachineOperand> &Pred) const override;
148 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
149 const SmallVectorImpl<MachineOperand> &Pred2) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000150
Craig Topper906c2cd2014-04-29 07:58:16 +0000151 bool
152 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000153
Craig Topper906c2cd2014-04-29 07:58:16 +0000154 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
155 const BranchProbability &Probability) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000156
Eric Christopher143f02c2014-10-09 01:59:35 +0000157 DFAPacketizer *
158 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
Andrew Trickd06df962012-02-01 22:13:57 +0000159
Craig Topper906c2cd2014-04-29 07:58:16 +0000160 bool isSchedulingBoundary(const MachineInstr *MI,
161 const MachineBasicBlock *MBB,
162 const MachineFunction &MF) const override;
Krzysztof Parzyszek05902162015-04-22 17:51:26 +0000163 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000164 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
165 bool isMemOp(const MachineInstr *MI) const;
166 bool isSpillPredRegOp(const MachineInstr *MI) const;
167 bool isU6_3Immediate(const int value) const;
168 bool isU6_2Immediate(const int value) const;
169 bool isU6_1Immediate(const int value) const;
170 bool isU6_0Immediate(const int value) const;
171 bool isS4_3Immediate(const int value) const;
172 bool isS4_2Immediate(const int value) const;
173 bool isS4_1Immediate(const int value) const;
174 bool isS4_0Immediate(const int value) const;
175 bool isS12_Immediate(const int value) const;
176 bool isU6_Immediate(const int value) const;
177 bool isS8_Immediate(const int value) const;
178 bool isS6_Immediate(const int value) const;
179
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000180 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
181 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000182 bool isConditionalALU32 (const MachineInstr* MI) const;
183 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000184 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Vermaf1214a82013-03-05 18:51:42 +0000185 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000186 bool isNewValue(const MachineInstr* MI) const;
Jyotsna Vermaa46059b2013-03-28 19:44:04 +0000187 bool isDotNewInst(const MachineInstr* MI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000188 int GetDotOldOp(const int opc) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000189 int GetDotNewOp(const MachineInstr* MI) const;
Jyotsna Verma00681dc2013-05-09 19:16:07 +0000190 int GetDotNewPredOp(MachineInstr *MI,
191 const MachineBranchProbabilityInfo
192 *MBPI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000193 bool mayBeNewStore(const MachineInstr* MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000194 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000195 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000196 bool isExtendable(const MachineInstr* MI) const;
197 bool isExtended(const MachineInstr* MI) const;
198 bool isPostIncrement(const MachineInstr* MI) const;
199 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000200 bool isNewValueStore(unsigned Opcode) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000201 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pande4bd20c52012-05-12 05:10:30 +0000202 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000203
Jyotsna Verma84256432013-03-01 17:37:13 +0000204
205 void immediateExtend(MachineInstr *MI) const;
206 bool isConstExtended(MachineInstr *MI) const;
Jyotsna Verma1d297502013-05-02 15:39:30 +0000207 int getDotNewPredJumpOp(MachineInstr *MI,
208 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Verma84256432013-03-01 17:37:13 +0000209 unsigned getAddrMode(const MachineInstr* MI) const;
210 bool isOperandExtended(const MachineInstr *MI,
211 unsigned short OperandNum) const;
212 unsigned short getCExtOpNum(const MachineInstr *MI) const;
213 int getMinValue(const MachineInstr *MI) const;
214 int getMaxValue(const MachineInstr *MI) const;
215 bool NonExtEquivalentExists (const MachineInstr *MI) const;
216 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000217 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
218 bool PredOpcodeHasNot(Opcode_t Opcode) const;
Krzysztof Parzyszekc05dff12015-03-31 13:35:12 +0000219 int getCondOpcode(int Opc, bool sense) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000220
221};
222
223}
224
225#endif