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gerrit-public.fairphone.software / toolchain / llvm-project / 15f349f76f076202a8569ffdf15db153168bf4a2 / . / llvm / test / CodeGen / RISCV / rem.ll
blob: f9ef4c9c8e63aaa3b8ebd2be73d06a1c9251e92d [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury92138382018-01-18 12:36:38 +0000[diff] [blame]3; RUN: | FileCheck -check-prefix=RV32I %s
4; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
5; RUN: | FileCheck -check-prefix=RV32IM %s
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]6
7define i32 @urem(i32 %a, i32 %b) nounwind {
8; RV32I-LABEL: urem:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]11; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]12; RV32I-NEXT: lui a2, %hi(__umodsi3)
13; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame]14; RV32I-NEXT: jalr a2
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]15; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]16; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame]17; RV32I-NEXT: ret
Alex Bradbury92138382018-01-18 12:36:38 +0000[diff] [blame]18;
19; RV32IM-LABEL: urem:
20; RV32IM: # %bb.0:
21; RV32IM-NEXT: remu a0, a0, a1
22; RV32IM-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]23 %1 = urem i32 %a, %b
24 ret i32 %1
25}
26
27define i32 @srem(i32 %a, i32 %b) nounwind {
28; RV32I-LABEL: srem:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]29; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]30; RV32I-NEXT: addi sp, sp, -16
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]31; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]32; RV32I-NEXT: lui a2, %hi(__modsi3)
33; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame]34; RV32I-NEXT: jalr a2
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]35; RV32I-NEXT: lw ra, 12(sp)
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]36; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame]37; RV32I-NEXT: ret
Alex Bradbury92138382018-01-18 12:36:38 +0000[diff] [blame]38;
39; RV32IM-LABEL: srem:
40; RV32IM: # %bb.0:
41; RV32IM-NEXT: rem a0, a0, a1
42; RV32IM-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]43 %1 = srem i32 %a, %b
44 ret i32 %1
45}