Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 1e1b05db246e69d9a2496feea184325dea57574e / . / llvm / test / CodeGen / AMDGPU / hsa.ll
blob: ab87fdbc00da2d3dcfba6ac5ee8c1ef7e9cf4829 [file] [log] [blame]
Tom Stellard4694ed02015-06-26 21:58:42 +0000[diff] [blame]1; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI --check-prefix=HSA %s
2; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI --check-prefix=HSA %s
Tom Stellard1e1b05d2015-11-06 11:45:14 +0000[diff] [blame^]3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
Tom Stellard347ac792015-06-26 21:15:07 +0000[diff] [blame]5
6; The SHT_NOTE section contains the output from the .hsa_code_object_*
7; directives.
8
Tom Stellarde135ffd2015-09-25 21:41:28 +0000[diff] [blame]9; ELF: Section {
10; ELF: Name: .hsatext
11; ELF: Type: SHT_PROGBITS (0x1)
12; ELF: Flags [ (0xC00007)
13; ELF: SHF_ALLOC (0x2)
14; ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
15; ELF: SHF_AMDGPU_HSA_CODE (0x400000)
16; ELF: SHF_EXECINSTR (0x4)
17; ELF: SHF_WRITE (0x1)
18; ELF: }
19
Tom Stellard347ac792015-06-26 21:15:07 +0000[diff] [blame]20; ELF: SHT_NOTE
21; ELF: 0000: 04000000 08000000 01000000 414D4400
22; ELF: 0010: 01000000 00000000 04000000 1B000000
23; ELF: 0020: 03000000 414D4400 04000700 07000000
24; ELF: 0030: 00000000 00000000 414D4400 414D4447
25; ELF: 0040: 50550000
26
Tom Stellard1e1b05d2015-11-06 11:45:14 +0000[diff] [blame^]27; ELF: Symbol {
28; ELF: Name: simple
29; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
30; ELF: }
31
Tom Stellard347ac792015-06-26 21:15:07 +0000[diff] [blame]32; HSA: .hsa_code_object_version 1,0
Tom Stellard4694ed02015-06-26 21:58:42 +0000[diff] [blame]33; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
34; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
Tom Stellard794c8c02014-12-02 17:05:41 +0000[diff] [blame]35
Tom Stellarde135ffd2015-09-25 21:41:28 +0000[diff] [blame]36; HSA: .hsatext
37
Tom Stellard1e1b05d2015-11-06 11:45:14 +0000[diff] [blame^]38; HSA: .amdgpu_hsa_kernel simple
Tom Stellardf151a452015-06-26 21:14:58 +0000[diff] [blame]39; HSA: {{^}}simple:
Tom Stellardff7416b2015-06-26 21:58:31 +0000[diff] [blame]40; HSA: .amd_kernel_code_t
41; HSA: .end_amd_kernel_code_t
Tom Stellardb5798b02015-06-26 21:15:03 +0000[diff] [blame]42; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0
Tom Stellard4694ed02015-06-26 21:58:42 +0000[diff] [blame]43
Tom Stellard794c8c02014-12-02 17:05:41 +0000[diff] [blame]44; Make sure we are setting the ATC bit:
Tom Stellard4694ed02015-06-26 21:58:42 +0000[diff] [blame]45; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
46; On VI+ we also need to set MTYPE = 2
47; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
Tom Stellard794c8c02014-12-02 17:05:41 +0000[diff] [blame]48; HSA: buffer_store_dword v{{[0-9]+}}, s[0:[[HI]]], 0
49
50define void @simple(i32 addrspace(1)* %out) {
51entry:
52 store i32 0, i32 addrspace(1)* %out
53 ret void
54}