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gerrit-public.fairphone.software / toolchain / llvm-project / 268b51a188b718debaaa7f758200246f1039cfb9 / . / llvm / lib / Target / PowerPC / PPCScheduleE500mc.td
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Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]1//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Freescale e500mc 32-bit
11// Power processor.
12//
13// All information is derived from the "e500mc Core Reference Manual",
14// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
15//
16//===----------------------------------------------------------------------===//
17// Relevant functional units in the Freescale e500mc core:
18//
19// * Decode & Dispatch
20// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
21// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]22def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
23def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]24
25// * Execute
26// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
27// Some instructions can only execute in SFX0 but not SFX1.
28// The CFX has a bypass path, allowing non-divide instructions to execute
29// while a divide instruction is executed.
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]30def E500_SFX0 : FuncUnit; // Simple unit 0
31def E500_SFX1 : FuncUnit; // Simple unit 1
32def E500_BU : FuncUnit; // Branch unit
33def E500_CFX_DivBypass
34 : FuncUnit; // CFX divide bypass path
35def E500_CFX_0 : FuncUnit; // CFX pipeline
36def E500_LSU_0 : FuncUnit; // LSU pipeline
37def E500_FPU_0 : FuncUnit; // FPU pipeline
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]39def E500_GPR_Bypass : Bypass;
40def E500_FPR_Bypass : Bypass;
41def E500_CR_Bypass : Bypass;
Hal Finkelf574c272013-09-11 23:25:21 +0000[diff] [blame]42
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]43def PPCE500mcItineraries : ProcessorItineraries<
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]44 [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
45 E500_CFX_0, E500_LSU_0, E500_FPU_0],
46 [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
47 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
48 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]49 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]50 [E500_GPR_Bypass,
51 E500_GPR_Bypass, E500_GPR_Bypass]>,
52 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
53 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]54 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]55 [E500_GPR_Bypass,
56 E500_GPR_Bypass, E500_GPR_Bypass]>,
Hal Finkel11d3c562015-02-01 17:52:16 +0000[diff] [blame]57 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
58 InstrStage<1, [E500_SFX0, E500_SFX1]>],
59 [4, 1, 1, 1], // Latency = 1
60 [E500_GPR_Bypass,
61 E500_GPR_Bypass, E500_GPR_Bypass,
62 E500_CR_Bypass]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]63 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
64 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]65 [5, 1, 1], // Latency = 1 or 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]66 [E500_CR_Bypass,
67 E500_GPR_Bypass, E500_GPR_Bypass]>,
68 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
69 InstrStage<1, [E500_CFX_0], 0>,
70 InstrStage<14, [E500_CFX_DivBypass]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]71 [17, 1, 1], // Latency=4..35, Repeat= 4..35
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]72 [E500_GPR_Bypass,
73 E500_GPR_Bypass, E500_GPR_Bypass]>,
74 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
75 InstrStage<8, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]76 [11], // Latency = 8
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]77 [E500_FPR_Bypass]>,
78 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
79 InstrStage<8, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]80 [11, 1, 1], // Latency = 8
81 [NoBypass, NoBypass, NoBypass]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]82 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
83 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]84 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]85 [E500_GPR_Bypass,
86 E500_GPR_Bypass, E500_GPR_Bypass]>,
87 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
88 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]89 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]90 [E500_GPR_Bypass,
91 E500_GPR_Bypass, E500_GPR_Bypass]>,
92 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
93 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]94 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]95 [E500_GPR_Bypass,
96 E500_GPR_Bypass, E500_GPR_Bypass]>,
97 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
98 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]99 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]100 [E500_GPR_Bypass,
101 E500_GPR_Bypass, E500_GPR_Bypass]>,
102 InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
103 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]104 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]105 [E500_GPR_Bypass,
106 E500_GPR_Bypass, E500_GPR_Bypass]>,
107 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
108 InstrStage<2, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]109 [5, 1], // Latency = 2, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]110 [E500_GPR_Bypass, E500_GPR_Bypass]>,
111 InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
112 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]113 [4, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]114 [NoBypass, E500_GPR_Bypass]>,
115 InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
116 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]117 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]118 [E500_CR_Bypass,
119 E500_CR_Bypass, E500_CR_Bypass]>,
120 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
121 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]122 [4, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]123 [E500_CR_Bypass, E500_CR_Bypass]>,
124 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
125 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]126 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]127 [E500_CR_Bypass, E500_GPR_Bypass]>,
128 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
129 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]130 [6, 1], // Latency = 3, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]131 [E500_GPR_Bypass, E500_GPR_Bypass]>,
132 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
133 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]134 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]135 [E500_GPR_Bypass, E500_GPR_Bypass]>,
136 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
137 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]138 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]139 [E500_GPR_Bypass, E500_GPR_Bypass]>,
140 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
141 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]142 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]143 [E500_GPR_Bypass, E500_GPR_Bypass]>,
144 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
145 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
146 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]147 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]148 [E500_GPR_Bypass, E500_GPR_Bypass],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]149 2>, // 2 micro-ops
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]150 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
151 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
152 InstrStage<1, [E500_LSU_0]>],
153 [6, 1], // Latency = 3
154 [E500_GPR_Bypass, E500_GPR_Bypass],
155 2>, // 2 micro-ops
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]156 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
157 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]158 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]159 [NoBypass, E500_GPR_Bypass]>,
160 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
161 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
162 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]163 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]164 [NoBypass, E500_GPR_Bypass],
165 2>, // 2 micro-ops
166 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
167 InstrStage<1, [E500_LSU_0]>],
168 [6, 1], // Latency = 3
169 [NoBypass, E500_GPR_Bypass]>,
170 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
171 InstrStage<1, [E500_LSU_0]>],
172 [6, 1, 1], // Latency = 3
173 [E500_GPR_Bypass,
174 E500_GPR_Bypass, E500_GPR_Bypass]>,
175 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
176 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
177 InstrStage<1, [E500_LSU_0]>],
178 [6, 1, 1], // Latency = 3
179 [E500_GPR_Bypass,
180 E500_GPR_Bypass, E500_GPR_Bypass],
181 2>, // 2 micro-ops
182 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
183 InstrStage<1, [E500_LSU_0]>],
184 [7, 1, 1], // Latency = 4
185 [E500_FPR_Bypass,
186 E500_GPR_Bypass, E500_GPR_Bypass]>,
187 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
188 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
189 InstrStage<1, [E500_LSU_0]>],
190 [7, 1, 1], // Latency = 4
191 [E500_FPR_Bypass,
192 E500_GPR_Bypass, E500_GPR_Bypass],
193 2>, // 2 micro-ops
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]194 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
195 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
196 InstrStage<1, [E500_LSU_0]>],
197 [7, 1, 1], // Latency = 4
198 [E500_FPR_Bypass,
199 E500_GPR_Bypass, E500_GPR_Bypass],
200 2>, // 2 micro-ops
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]201 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
202 InstrStage<1, [E500_LSU_0]>],
203 [6, 1], // Latency = 3
204 [E500_GPR_Bypass, E500_GPR_Bypass]>,
205 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
206 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
207 InstrStage<1, [E500_LSU_0]>],
208 [6, 1], // Latency = 3
209 [E500_GPR_Bypass, E500_GPR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]210 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
211 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
212 InstrStage<1, [E500_LSU_0]>],
213 [6, 1], // Latency = 3
214 [E500_GPR_Bypass, E500_GPR_Bypass]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]215 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
216 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]217 [7, 1], // Latency = r+3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]218 [NoBypass, E500_GPR_Bypass]>,
219 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
220 InstrStage<3, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]221 [6, 1, 1], // Latency = 3, Repeat rate = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]222 [E500_GPR_Bypass,
223 E500_GPR_Bypass, E500_GPR_Bypass]>,
224 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
225 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]226 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]227 [NoBypass, E500_GPR_Bypass]>,
228 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
229 InstrStage<1, [E500_LSU_0]>]>,
230 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
231 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]232 [7, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]233 [E500_GPR_Bypass, E500_GPR_Bypass]>,
234 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
235 InstrStage<2, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]236 [5, 1], // Latency = 2, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]237 [E500_GPR_Bypass, E500_GPR_Bypass]>,
238 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
239 InstrStage<1, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]240 [5, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]241 [NoBypass, E500_GPR_Bypass]>,
242 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
243 InstrStage<1, [E500_LSU_0], 0>]>,
244 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
245 InstrStage<5, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]246 [8, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]247 [E500_GPR_Bypass, E500_CR_Bypass]>,
Hal Finkel46402a42013-11-30 20:41:13 +0000[diff] [blame]248 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
249 InstrStage<5, [E500_SFX0]>],
250 [8, 1],
251 [E500_GPR_Bypass, E500_CR_Bypass]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]252 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
253 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]254 [7, 1], // Latency = 4, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]255 [E500_GPR_Bypass, E500_GPR_Bypass]>,
256 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
257 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]258 [4, 1], // Latency = 1, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]259 [E500_GPR_Bypass, E500_CR_Bypass]>,
260 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
261 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]262 [7, 1], // Latency = 4, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]263 [NoBypass, E500_GPR_Bypass]>,
264 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
265 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]266 [4, 1], // Latency = 1, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]267 [E500_CR_Bypass, E500_GPR_Bypass]>,
268 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
269 InstrStage<1, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]270 [4, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]271 [NoBypass, E500_GPR_Bypass]>,
272 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
273 InstrStage<2, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]274 [11, 1, 1], // Latency = 8, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]275 [E500_FPR_Bypass,
276 E500_FPR_Bypass, E500_FPR_Bypass]>,
277 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
278 InstrStage<4, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]279 [13, 1, 1], // Latency = 10, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]280 [E500_FPR_Bypass,
281 E500_FPR_Bypass, E500_FPR_Bypass]>,
282 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
283 InstrStage<2, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]284 [11, 1, 1], // Latency = 8, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]285 [E500_CR_Bypass,
286 E500_FPR_Bypass, E500_FPR_Bypass]>,
287 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
288 InstrStage<68, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]289 [71, 1, 1], // Latency = 68, Repeat rate = 68
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]290 [E500_FPR_Bypass,
291 E500_FPR_Bypass, E500_FPR_Bypass]>,
292 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
293 InstrStage<38, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]294 [41, 1, 1], // Latency = 38, Repeat rate = 38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]295 [E500_FPR_Bypass,
296 E500_FPR_Bypass, E500_FPR_Bypass]>,
297 InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
298 InstrStage<4, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]299 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]300 [E500_FPR_Bypass,
301 E500_FPR_Bypass, E500_FPR_Bypass,
302 E500_FPR_Bypass]>,
303 InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
304 InstrStage<38, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]305 [41, 1], // Latency = 38, Repeat rate = 38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame]306 [E500_FPR_Bypass, E500_FPR_Bypass]>
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]307]>;
308
309// ===---------------------------------------------------------------------===//
310// e500mc machine model for scheduling and other instruction cost heuristics.
311
312def PPCE500mcModel : SchedMachineModel {
313 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
314 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
315 let LoadLatency = 5; // Optimistic load latency assuming bypass.
316 // This is overriden by OperandCycles if the
317 // Itineraries are queried instead.
318
319 let Itineraries = PPCE500mcItineraries;
320}