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gerrit-public.fairphone.software / toolchain / llvm-project / 3b78693b9a1a89ae7453214add34b0e678f15d79 / . / llvm / lib / Target / AMDGPU / VOPCInstructions.td
blob: cd347b86d3050ca195d8df97c6489fb428dc3ab2 [file] [log] [blame]
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]1//===-- VOPCInstructions.td - Vector Instruction Defintions ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Encodings
12//===----------------------------------------------------------------------===//
13
14class VOPCe <bits<8> op> : Enc32 {
15 bits<9> src0;
16 bits<8> src1;
17
18 let Inst{8-0} = src0;
19 let Inst{16-9} = src1;
20 let Inst{24-17} = op;
21 let Inst{31-25} = 0x3e;
22}
23
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]24class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
25 bits<8> src1;
26
27 let Inst{8-0} = 0xf9; // sdwa
28 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
29 let Inst{24-17} = op;
30 let Inst{31-25} = 0x3e; // encoding
31
32 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
33 let Inst{42-40} = SDWA.DWORD;
34 let Inst{44-43} = SDWA.UNUSED_PRESERVE;
35}
36
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]37class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
38 bits<9> src1;
39
40 let Inst{8-0} = 0xf9; // sdwa
41 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
42 let Inst{24-17} = op;
43 let Inst{31-25} = 0x3e; // encoding
44 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
45}
46
47
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]48//===----------------------------------------------------------------------===//
49// VOPC classes
50//===----------------------------------------------------------------------===//
51
52// VOPC instructions are a special case because for the 32-bit
53// encoding, we want to display the implicit vcc write as if it were
54// an explicit $dst.
55class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
56 VOPProfile <[i1, vt0, vt1, untyped]> {
57 let Asm32 = "vcc, $src0, $src1";
58 // The destination for 32-bit encoding is implicit.
59 let HasDst32 = 0;
60 let Outs64 = (outs VOPDstS64:$sdst);
61 list<SchedReadWrite> Schedule = sched;
62}
63
64class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[]> :
65 InstSI<(outs), P.Ins32, "", pattern>,
66 VOP <opName>,
67 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
68
69 let isPseudo = 1;
70 let isCodeGenOnly = 1;
71 let UseNamedOperandTable = 1;
72
73 string Mnemonic = opName;
74 string AsmOperands = P.Asm32;
75
76 let Size = 4;
77 let mayLoad = 0;
78 let mayStore = 0;
79 let hasSideEffects = 0;
80
81 let VALU = 1;
82 let VOPC = 1;
83 let Uses = [EXEC];
84 let Defs = [VCC];
85
86 let SubtargetPredicate = isGCN;
87
88 VOPProfile Pfl = P;
89}
90
91class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
92 InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
93 SIMCInstr <ps.PseudoInstr, EncodingFamily> {
94
95 let isPseudo = 0;
96 let isCodeGenOnly = 0;
97
Sam Koltona6792a32016-12-22 11:30:48 +0000[diff] [blame]98 let Constraints = ps.Constraints;
99 let DisableEncoding = ps.DisableEncoding;
100
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]101 // copy relevant pseudo op flags
102 let SubtargetPredicate = ps.SubtargetPredicate;
103 let AsmMatchConverter = ps.AsmMatchConverter;
104 let Constraints = ps.Constraints;
105 let DisableEncoding = ps.DisableEncoding;
106 let TSFlags = ps.TSFlags;
Dmitry Preobrazhensky03880f82017-03-03 14:31:06 +0000[diff] [blame]107 let UseNamedOperandTable = ps.UseNamedOperandTable;
108 let Uses = ps.Uses;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]109}
110
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]111class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
112 VOP_SDWA_Pseudo <OpName, P, pattern> {
113 let AsmMatchConverter = "cvtSdwaVOPC";
114}
115
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]116class VOPC_SDWA9_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
117 VOP_SDWA9_Pseudo <OpName, P, pattern> {
118 let AsmMatchConverter = "cvtSdwaVOPC";
119}
120
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]121// This class is used only with VOPC instructions. Use $sdst for out operand
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]122class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst, VOPProfile p = ps.Pfl> :
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]123 InstAlias <ps.OpName#" "#p.Asm32, (inst)>, PredicateControl {
124
125 field bit isCompare;
126 field bit isCommutable;
127
128 let ResultInst =
129 !if (p.HasDst32,
130 !if (!eq(p.NumSrcArgs, 0),
131 // 1 dst, 0 src
132 (inst p.DstRC:$sdst),
133 !if (!eq(p.NumSrcArgs, 1),
134 // 1 dst, 1 src
135 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
136 !if (!eq(p.NumSrcArgs, 2),
137 // 1 dst, 2 src
138 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
139 // else - unreachable
140 (inst)))),
141 // else
142 !if (!eq(p.NumSrcArgs, 2),
143 // 0 dst, 2 src
144 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
145 !if (!eq(p.NumSrcArgs, 1),
146 // 0 dst, 1 src
147 (inst p.Src0RC32:$src1),
148 // else
149 // 0 dst, 0 src
150 (inst))));
151
152 let AsmVariantName = AMDGPUAsmVariants.Default;
153 let SubtargetPredicate = AssemblerPredicate;
154}
155
156multiclass VOPC_Pseudos <string opName,
157 VOPC_Profile P,
158 PatLeaf cond = COND_NULL,
159 string revOp = opName,
160 bit DefExec = 0> {
161
162 def _e32 : VOPC_Pseudo <opName, P>,
163 Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
164 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
165 let SchedRW = P.Schedule;
166 let isConvergent = DefExec;
167 let isCompare = 1;
168 let isCommutable = 1;
169 }
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]170
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]171 def _e64 : VOP3_Pseudo<opName, P,
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]172 !if(P.HasModifiers,
173 [(set i1:$sdst,
174 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
175 i1:$clamp, i32:$omod)),
176 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
177 cond))],
178 [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))])>,
179 Commutable_REV<revOp#"_e64", !eq(revOp, opName)> {
180 let Defs = !if(DefExec, [EXEC], []);
181 let SchedRW = P.Schedule;
182 let isCompare = 1;
183 let isCommutable = 1;
184 }
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]185
Sam Kolton07dbde22017-01-20 10:01:25 +0000[diff] [blame]186 def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]187 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
188 let SchedRW = P.Schedule;
189 let isConvergent = DefExec;
190 let isCompare = 1;
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]191 }
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]192
193 def _sdwa9 : VOPC_SDWA9_Pseudo <opName, P> {
194 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
195 let SchedRW = P.Schedule;
196 let isConvergent = DefExec;
197 let isCompare = 1;
198 }
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]199}
200
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]201def VOPC_I1_F16_F16 : VOPC_Profile<[Write32Bit], f16>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]202def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
203def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]204def VOPC_I1_I16_I16 : VOPC_Profile<[Write32Bit], i16>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]205def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
206def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;
207
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]208multiclass VOPC_F16 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
209 VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>;
210
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]211multiclass VOPC_F32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
212 VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;
213
214multiclass VOPC_F64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
215 VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;
216
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]217multiclass VOPC_I16 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
218 VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>;
219
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]220multiclass VOPC_I32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
221 VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;
222
223multiclass VOPC_I64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
224 VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;
225
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]226multiclass VOPCX_F16 <string opName, string revOp = opName> :
227 VOPC_Pseudos <opName, VOPC_I1_F16_F16, COND_NULL, revOp, 1>;
228
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]229multiclass VOPCX_F32 <string opName, string revOp = opName> :
230 VOPC_Pseudos <opName, VOPC_I1_F32_F32, COND_NULL, revOp, 1>;
231
232multiclass VOPCX_F64 <string opName, string revOp = opName> :
233 VOPC_Pseudos <opName, VOPC_I1_F64_F64, COND_NULL, revOp, 1>;
234
Matt Arsenault3c97e202016-12-22 16:27:14 +0000[diff] [blame]235multiclass VOPCX_I16 <string opName, string revOp = opName> :
236 VOPC_Pseudos <opName, VOPC_I1_I16_I16, COND_NULL, revOp, 1>;
237
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]238multiclass VOPCX_I32 <string opName, string revOp = opName> :
239 VOPC_Pseudos <opName, VOPC_I1_I32_I32, COND_NULL, revOp, 1>;
240
241multiclass VOPCX_I64 <string opName, string revOp = opName> :
242 VOPC_Pseudos <opName, VOPC_I1_I64_I64, COND_NULL, revOp, 1>;
243
244
245//===----------------------------------------------------------------------===//
246// Compare instructions
247//===----------------------------------------------------------------------===//
248
249defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">;
250defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
251defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>;
252defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
253defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>;
254defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>;
255defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>;
256defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>;
257defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>;
258defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">;
259defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>;
260defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
261defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>;
262defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>;
263defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>;
264defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">;
265
266defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">;
267defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">;
268defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">;
269defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">;
270defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">;
271defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">;
272defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">;
273defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">;
274defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">;
Matt Arsenault3de76b92016-12-22 04:39:41 +0000[diff] [blame]275defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]276defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">;
Matt Arsenault3de76b92016-12-22 04:39:41 +0000[diff] [blame]277defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]278defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">;
279defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">;
280defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">;
281defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">;
282
283defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">;
284defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
285defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>;
286defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
287defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>;
288defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>;
289defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>;
290defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>;
291defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>;
292defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
293defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>;
294defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
295defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>;
296defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>;
297defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>;
298defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">;
299
300defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">;
301defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">;
302defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">;
303defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">;
304defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">;
305defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">;
306defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">;
307defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">;
308defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">;
309defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">;
310defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">;
311defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
312defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">;
313defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
314defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
315defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;
316
317let SubtargetPredicate = isSICI in {
318
319defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
320defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
321defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">;
322defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
323defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">;
324defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">;
325defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">;
326defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">;
327defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">;
328defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
329defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">;
330defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
331defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">;
332defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">;
333defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">;
334defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">;
335
336defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">;
337defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
338defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">;
339defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
340defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">;
341defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">;
342defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">;
343defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">;
344defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">;
345defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
346defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">;
347defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
348defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">;
349defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">;
350defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">;
351defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">;
352
353defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">;
354defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
355defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">;
356defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
357defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">;
358defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">;
359defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">;
360defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">;
361defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">;
362defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
363defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">;
364defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
365defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">;
366defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">;
367defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">;
368defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">;
369
370defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">;
371defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
372defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">;
373defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
374defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">;
375defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">;
376defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">;
377defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">;
378defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">;
379defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
380defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">;
381defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
382defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
383defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
384defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
385defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;
386
387} // End SubtargetPredicate = isSICI
388
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]389let SubtargetPredicate = Has16BitInsts in {
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]390
391defm V_CMP_F_F16 : VOPC_F16 <"v_cmp_f_f16">;
392defm V_CMP_LT_F16 : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">;
393defm V_CMP_EQ_F16 : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>;
394defm V_CMP_LE_F16 : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">;
395defm V_CMP_GT_F16 : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>;
396defm V_CMP_LG_F16 : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>;
397defm V_CMP_GE_F16 : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>;
398defm V_CMP_O_F16 : VOPC_F16 <"v_cmp_o_f16", COND_O>;
399defm V_CMP_U_F16 : VOPC_F16 <"v_cmp_u_f16", COND_UO>;
400defm V_CMP_NGE_F16 : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">;
401defm V_CMP_NLG_F16 : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>;
402defm V_CMP_NGT_F16 : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">;
403defm V_CMP_NLE_F16 : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>;
404defm V_CMP_NEQ_F16 : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>;
405defm V_CMP_NLT_F16 : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>;
406defm V_CMP_TRU_F16 : VOPC_F16 <"v_cmp_tru_f16">;
407
408defm V_CMPX_F_F16 : VOPCX_F16 <"v_cmpx_f_f16">;
409defm V_CMPX_LT_F16 : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">;
410defm V_CMPX_EQ_F16 : VOPCX_F16 <"v_cmpx_eq_f16">;
411defm V_CMPX_LE_F16 : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">;
412defm V_CMPX_GT_F16 : VOPCX_F16 <"v_cmpx_gt_f16">;
413defm V_CMPX_LG_F16 : VOPCX_F16 <"v_cmpx_lg_f16">;
414defm V_CMPX_GE_F16 : VOPCX_F16 <"v_cmpx_ge_f16">;
415defm V_CMPX_O_F16 : VOPCX_F16 <"v_cmpx_o_f16">;
416defm V_CMPX_U_F16 : VOPCX_F16 <"v_cmpx_u_f16">;
Matt Arsenault3de76b92016-12-22 04:39:41 +0000[diff] [blame]417defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]418defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">;
Matt Arsenault3de76b92016-12-22 04:39:41 +0000[diff] [blame]419defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]420defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">;
421defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">;
422defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">;
423defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">;
424
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]425defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">;
426defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">;
427defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">;
428defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">;
429defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>;
430defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">;
431defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>;
432defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">;
433
434defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">;
435defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">;
436defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>;
437defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">;
438defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>;
439defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>;
440defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>;
441defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">;
442
Matt Arsenault3c97e202016-12-22 16:27:14 +0000[diff] [blame]443defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">;
444defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">;
445defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">;
446defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">;
447defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">;
448defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">;
449defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">;
450defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">;
451defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">;
452
453defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">;
454defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">;
455defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">;
456defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">;
457defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">;
458defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">;
459defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">;
460
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]461} // End SubtargetPredicate = Has16BitInsts
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]462
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]463defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
464defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]465defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]466defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
467defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]468defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]469defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>;
470defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">;
471
472defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">;
473defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">;
474defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">;
475defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">;
476defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">;
477defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
478defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
479defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;
480
481defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
482defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]483defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]484defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
485defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]486defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]487defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
488defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;
489
490defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
491defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
492defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
493defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
494defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
495defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
496defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
497defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;
498
499defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
500defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
501defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>;
502defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
503defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>;
504defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>;
505defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>;
506defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">;
507
508defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">;
509defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">;
510defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">;
511defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">;
512defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">;
513defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">;
514defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">;
515defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">;
516
517defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">;
518defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
519defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>;
520defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
521defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>;
522defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>;
523defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>;
524defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">;
525
526defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">;
527defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">;
528defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">;
529defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">;
530defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">;
531defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">;
532defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">;
533defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
534
535//===----------------------------------------------------------------------===//
536// Class instructions
537//===----------------------------------------------------------------------===//
538
539class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
540 VOPC_Profile<sched, vt, i32> {
541 let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
542 let Asm64 = "$sdst, $src0_modifiers, $src1";
Sam Kolton9772eb32017-01-11 11:46:30 +0000[diff] [blame]543 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
544 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]545 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]546 let InsSDWA9 = (ins Src0ModSDWA9:$src0_modifiers, Src0SDWA9:$src0,
547 Src1ModSDWA9:$src1_modifiers, Src1SDWA9:$src1,
548 src0_sel:$src0_sel, src1_sel:$src1_sel);
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]549 let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]550 //let AsmSDWA9 = " $sdst, $src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]551 let HasSrc1Mods = 0;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]552 let HasClamp = 0;
553 let HasOMod = 0;
554}
555
556class getVOPCClassPat64 <VOPProfile P> {
557 list<dag> ret =
558 [(set i1:$sdst,
559 (AMDGPUfp_class
560 (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)),
561 P.Src1VT:$src1))];
562}
563
564// Special case for class instructions which only have modifiers on
565// the 1st source operand.
566multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec> {
567 def _e32 : VOPC_Pseudo <opName, p> {
568 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
569 let SchedRW = p.Schedule;
570 let isConvergent = DefExec;
571 }
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]572
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]573 def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret> {
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]574 let Defs = !if(DefExec, [EXEC], []);
575 let SchedRW = p.Schedule;
576 }
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]577
578 def _sdwa : VOPC_SDWA_Pseudo <opName, p> {
579 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
580 let SchedRW = p.Schedule;
581 let isConvergent = DefExec;
582 }
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]583
584 def _sdwa9 : VOPC_SDWA9_Pseudo <opName, p> {
585 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
586 let SchedRW = p.Schedule;
587 let isConvergent = DefExec;
588 }
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]589}
590
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]591def VOPC_I1_F16_I32 : VOPC_Class_Profile<[Write32Bit], f16>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]592def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
593def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>;
594
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]595multiclass VOPC_CLASS_F16 <string opName> :
596 VOPC_Class_Pseudos <opName, VOPC_I1_F16_I32, 0>;
597
598multiclass VOPCX_CLASS_F16 <string opName> :
Dmitry Preobrazhensky5ac9fd62017-04-12 16:31:18 +0000[diff] [blame]599 VOPC_Class_Pseudos <opName, VOPC_I1_F16_I32, 1>;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]600
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]601multiclass VOPC_CLASS_F32 <string opName> :
602 VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;
603
604multiclass VOPCX_CLASS_F32 <string opName> :
605 VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 1>;
606
607multiclass VOPC_CLASS_F64 <string opName> :
608 VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
609
610multiclass VOPCX_CLASS_F64 <string opName> :
611 VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 1>;
612
613defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
614defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
615defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
616defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]617defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">;
618defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]619
620//===----------------------------------------------------------------------===//
621// V_ICMPIntrinsic Pattern.
622//===----------------------------------------------------------------------===//
623
624let Predicates = [isGCN] in {
625
626class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
627 (AMDGPUsetcc vt:$src0, vt:$src1, cond),
628 (inst $src0, $src1)
629>;
630
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]631def : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;
632def : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]633def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
634def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
635def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
636def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
637def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
638def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
639def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
640def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;
641
Matt Arsenault5d8eb252016-09-30 01:50:20 +0000[diff] [blame]642def : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>;
643def : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]644def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
645def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
646def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
647def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
648def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
649def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
650def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
651def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
652
653class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
654 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
655 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
656 (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
657 DSTCLAMP.NONE, DSTOMOD.NONE)
658>;
659
660def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
661def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
662def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
663def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
664def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
665def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;
666
667def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
668def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
669def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
670def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
671def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
672def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
673
674def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
675def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
676def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
677def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
678def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
679def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
680
681def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
682def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
683def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
684def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
685def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
686def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
687
688} // End Predicates = [isGCN]
689
690//===----------------------------------------------------------------------===//
691// Target
692//===----------------------------------------------------------------------===//
693
694//===----------------------------------------------------------------------===//
695// SI
696//===----------------------------------------------------------------------===//
697
698multiclass VOPC_Real_si <bits<9> op> {
699 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
700 def _e32_si :
701 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
702 VOPCe<op{7-0}>;
703
704 def _e64_si :
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]705 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
706 VOP3a_si <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]707 // Encoding used for VOPC instructions encoded as VOP3
708 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
709 bits<8> sdst;
710 let Inst{7-0} = sdst;
711 }
712 }
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]713 def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"),
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]714 !cast<Instruction>(NAME#"_e32_si")> {
715 let AssemblerPredicate = isSICI;
716 }
717}
718
719defm V_CMP_F_F32 : VOPC_Real_si <0x0>;
720defm V_CMP_LT_F32 : VOPC_Real_si <0x1>;
721defm V_CMP_EQ_F32 : VOPC_Real_si <0x2>;
722defm V_CMP_LE_F32 : VOPC_Real_si <0x3>;
723defm V_CMP_GT_F32 : VOPC_Real_si <0x4>;
724defm V_CMP_LG_F32 : VOPC_Real_si <0x5>;
725defm V_CMP_GE_F32 : VOPC_Real_si <0x6>;
726defm V_CMP_O_F32 : VOPC_Real_si <0x7>;
727defm V_CMP_U_F32 : VOPC_Real_si <0x8>;
728defm V_CMP_NGE_F32 : VOPC_Real_si <0x9>;
729defm V_CMP_NLG_F32 : VOPC_Real_si <0xa>;
730defm V_CMP_NGT_F32 : VOPC_Real_si <0xb>;
731defm V_CMP_NLE_F32 : VOPC_Real_si <0xc>;
732defm V_CMP_NEQ_F32 : VOPC_Real_si <0xd>;
733defm V_CMP_NLT_F32 : VOPC_Real_si <0xe>;
734defm V_CMP_TRU_F32 : VOPC_Real_si <0xf>;
735
736defm V_CMPX_F_F32 : VOPC_Real_si <0x10>;
737defm V_CMPX_LT_F32 : VOPC_Real_si <0x11>;
738defm V_CMPX_EQ_F32 : VOPC_Real_si <0x12>;
739defm V_CMPX_LE_F32 : VOPC_Real_si <0x13>;
740defm V_CMPX_GT_F32 : VOPC_Real_si <0x14>;
741defm V_CMPX_LG_F32 : VOPC_Real_si <0x15>;
742defm V_CMPX_GE_F32 : VOPC_Real_si <0x16>;
743defm V_CMPX_O_F32 : VOPC_Real_si <0x17>;
744defm V_CMPX_U_F32 : VOPC_Real_si <0x18>;
745defm V_CMPX_NGE_F32 : VOPC_Real_si <0x19>;
746defm V_CMPX_NLG_F32 : VOPC_Real_si <0x1a>;
747defm V_CMPX_NGT_F32 : VOPC_Real_si <0x1b>;
748defm V_CMPX_NLE_F32 : VOPC_Real_si <0x1c>;
749defm V_CMPX_NEQ_F32 : VOPC_Real_si <0x1d>;
750defm V_CMPX_NLT_F32 : VOPC_Real_si <0x1e>;
751defm V_CMPX_TRU_F32 : VOPC_Real_si <0x1f>;
752
753defm V_CMP_F_F64 : VOPC_Real_si <0x20>;
754defm V_CMP_LT_F64 : VOPC_Real_si <0x21>;
755defm V_CMP_EQ_F64 : VOPC_Real_si <0x22>;
756defm V_CMP_LE_F64 : VOPC_Real_si <0x23>;
757defm V_CMP_GT_F64 : VOPC_Real_si <0x24>;
758defm V_CMP_LG_F64 : VOPC_Real_si <0x25>;
759defm V_CMP_GE_F64 : VOPC_Real_si <0x26>;
760defm V_CMP_O_F64 : VOPC_Real_si <0x27>;
761defm V_CMP_U_F64 : VOPC_Real_si <0x28>;
762defm V_CMP_NGE_F64 : VOPC_Real_si <0x29>;
763defm V_CMP_NLG_F64 : VOPC_Real_si <0x2a>;
764defm V_CMP_NGT_F64 : VOPC_Real_si <0x2b>;
765defm V_CMP_NLE_F64 : VOPC_Real_si <0x2c>;
766defm V_CMP_NEQ_F64 : VOPC_Real_si <0x2d>;
767defm V_CMP_NLT_F64 : VOPC_Real_si <0x2e>;
768defm V_CMP_TRU_F64 : VOPC_Real_si <0x2f>;
769
770defm V_CMPX_F_F64 : VOPC_Real_si <0x30>;
771defm V_CMPX_LT_F64 : VOPC_Real_si <0x31>;
772defm V_CMPX_EQ_F64 : VOPC_Real_si <0x32>;
773defm V_CMPX_LE_F64 : VOPC_Real_si <0x33>;
774defm V_CMPX_GT_F64 : VOPC_Real_si <0x34>;
775defm V_CMPX_LG_F64 : VOPC_Real_si <0x35>;
776defm V_CMPX_GE_F64 : VOPC_Real_si <0x36>;
777defm V_CMPX_O_F64 : VOPC_Real_si <0x37>;
778defm V_CMPX_U_F64 : VOPC_Real_si <0x38>;
779defm V_CMPX_NGE_F64 : VOPC_Real_si <0x39>;
780defm V_CMPX_NLG_F64 : VOPC_Real_si <0x3a>;
781defm V_CMPX_NGT_F64 : VOPC_Real_si <0x3b>;
782defm V_CMPX_NLE_F64 : VOPC_Real_si <0x3c>;
783defm V_CMPX_NEQ_F64 : VOPC_Real_si <0x3d>;
784defm V_CMPX_NLT_F64 : VOPC_Real_si <0x3e>;
785defm V_CMPX_TRU_F64 : VOPC_Real_si <0x3f>;
786
787defm V_CMPS_F_F32 : VOPC_Real_si <0x40>;
788defm V_CMPS_LT_F32 : VOPC_Real_si <0x41>;
789defm V_CMPS_EQ_F32 : VOPC_Real_si <0x42>;
790defm V_CMPS_LE_F32 : VOPC_Real_si <0x43>;
791defm V_CMPS_GT_F32 : VOPC_Real_si <0x44>;
792defm V_CMPS_LG_F32 : VOPC_Real_si <0x45>;
793defm V_CMPS_GE_F32 : VOPC_Real_si <0x46>;
794defm V_CMPS_O_F32 : VOPC_Real_si <0x47>;
795defm V_CMPS_U_F32 : VOPC_Real_si <0x48>;
796defm V_CMPS_NGE_F32 : VOPC_Real_si <0x49>;
797defm V_CMPS_NLG_F32 : VOPC_Real_si <0x4a>;
798defm V_CMPS_NGT_F32 : VOPC_Real_si <0x4b>;
799defm V_CMPS_NLE_F32 : VOPC_Real_si <0x4c>;
800defm V_CMPS_NEQ_F32 : VOPC_Real_si <0x4d>;
801defm V_CMPS_NLT_F32 : VOPC_Real_si <0x4e>;
802defm V_CMPS_TRU_F32 : VOPC_Real_si <0x4f>;
803
804defm V_CMPSX_F_F32 : VOPC_Real_si <0x50>;
805defm V_CMPSX_LT_F32 : VOPC_Real_si <0x51>;
806defm V_CMPSX_EQ_F32 : VOPC_Real_si <0x52>;
807defm V_CMPSX_LE_F32 : VOPC_Real_si <0x53>;
808defm V_CMPSX_GT_F32 : VOPC_Real_si <0x54>;
809defm V_CMPSX_LG_F32 : VOPC_Real_si <0x55>;
810defm V_CMPSX_GE_F32 : VOPC_Real_si <0x56>;
811defm V_CMPSX_O_F32 : VOPC_Real_si <0x57>;
812defm V_CMPSX_U_F32 : VOPC_Real_si <0x58>;
813defm V_CMPSX_NGE_F32 : VOPC_Real_si <0x59>;
814defm V_CMPSX_NLG_F32 : VOPC_Real_si <0x5a>;
815defm V_CMPSX_NGT_F32 : VOPC_Real_si <0x5b>;
816defm V_CMPSX_NLE_F32 : VOPC_Real_si <0x5c>;
817defm V_CMPSX_NEQ_F32 : VOPC_Real_si <0x5d>;
818defm V_CMPSX_NLT_F32 : VOPC_Real_si <0x5e>;
819defm V_CMPSX_TRU_F32 : VOPC_Real_si <0x5f>;
820
821defm V_CMPS_F_F64 : VOPC_Real_si <0x60>;
822defm V_CMPS_LT_F64 : VOPC_Real_si <0x61>;
823defm V_CMPS_EQ_F64 : VOPC_Real_si <0x62>;
824defm V_CMPS_LE_F64 : VOPC_Real_si <0x63>;
825defm V_CMPS_GT_F64 : VOPC_Real_si <0x64>;
826defm V_CMPS_LG_F64 : VOPC_Real_si <0x65>;
827defm V_CMPS_GE_F64 : VOPC_Real_si <0x66>;
828defm V_CMPS_O_F64 : VOPC_Real_si <0x67>;
829defm V_CMPS_U_F64 : VOPC_Real_si <0x68>;
830defm V_CMPS_NGE_F64 : VOPC_Real_si <0x69>;
831defm V_CMPS_NLG_F64 : VOPC_Real_si <0x6a>;
832defm V_CMPS_NGT_F64 : VOPC_Real_si <0x6b>;
833defm V_CMPS_NLE_F64 : VOPC_Real_si <0x6c>;
834defm V_CMPS_NEQ_F64 : VOPC_Real_si <0x6d>;
835defm V_CMPS_NLT_F64 : VOPC_Real_si <0x6e>;
836defm V_CMPS_TRU_F64 : VOPC_Real_si <0x6f>;
837
838defm V_CMPSX_F_F64 : VOPC_Real_si <0x70>;
839defm V_CMPSX_LT_F64 : VOPC_Real_si <0x71>;
840defm V_CMPSX_EQ_F64 : VOPC_Real_si <0x72>;
841defm V_CMPSX_LE_F64 : VOPC_Real_si <0x73>;
842defm V_CMPSX_GT_F64 : VOPC_Real_si <0x74>;
843defm V_CMPSX_LG_F64 : VOPC_Real_si <0x75>;
844defm V_CMPSX_GE_F64 : VOPC_Real_si <0x76>;
845defm V_CMPSX_O_F64 : VOPC_Real_si <0x77>;
846defm V_CMPSX_U_F64 : VOPC_Real_si <0x78>;
847defm V_CMPSX_NGE_F64 : VOPC_Real_si <0x79>;
848defm V_CMPSX_NLG_F64 : VOPC_Real_si <0x7a>;
849defm V_CMPSX_NGT_F64 : VOPC_Real_si <0x7b>;
850defm V_CMPSX_NLE_F64 : VOPC_Real_si <0x7c>;
851defm V_CMPSX_NEQ_F64 : VOPC_Real_si <0x7d>;
852defm V_CMPSX_NLT_F64 : VOPC_Real_si <0x7e>;
853defm V_CMPSX_TRU_F64 : VOPC_Real_si <0x7f>;
854
855defm V_CMP_F_I32 : VOPC_Real_si <0x80>;
856defm V_CMP_LT_I32 : VOPC_Real_si <0x81>;
857defm V_CMP_EQ_I32 : VOPC_Real_si <0x82>;
858defm V_CMP_LE_I32 : VOPC_Real_si <0x83>;
859defm V_CMP_GT_I32 : VOPC_Real_si <0x84>;
860defm V_CMP_NE_I32 : VOPC_Real_si <0x85>;
861defm V_CMP_GE_I32 : VOPC_Real_si <0x86>;
862defm V_CMP_T_I32 : VOPC_Real_si <0x87>;
863
864defm V_CMPX_F_I32 : VOPC_Real_si <0x90>;
865defm V_CMPX_LT_I32 : VOPC_Real_si <0x91>;
866defm V_CMPX_EQ_I32 : VOPC_Real_si <0x92>;
867defm V_CMPX_LE_I32 : VOPC_Real_si <0x93>;
868defm V_CMPX_GT_I32 : VOPC_Real_si <0x94>;
869defm V_CMPX_NE_I32 : VOPC_Real_si <0x95>;
870defm V_CMPX_GE_I32 : VOPC_Real_si <0x96>;
871defm V_CMPX_T_I32 : VOPC_Real_si <0x97>;
872
873defm V_CMP_F_I64 : VOPC_Real_si <0xa0>;
874defm V_CMP_LT_I64 : VOPC_Real_si <0xa1>;
875defm V_CMP_EQ_I64 : VOPC_Real_si <0xa2>;
876defm V_CMP_LE_I64 : VOPC_Real_si <0xa3>;
877defm V_CMP_GT_I64 : VOPC_Real_si <0xa4>;
878defm V_CMP_NE_I64 : VOPC_Real_si <0xa5>;
879defm V_CMP_GE_I64 : VOPC_Real_si <0xa6>;
880defm V_CMP_T_I64 : VOPC_Real_si <0xa7>;
881
882defm V_CMPX_F_I64 : VOPC_Real_si <0xb0>;
883defm V_CMPX_LT_I64 : VOPC_Real_si <0xb1>;
884defm V_CMPX_EQ_I64 : VOPC_Real_si <0xb2>;
885defm V_CMPX_LE_I64 : VOPC_Real_si <0xb3>;
886defm V_CMPX_GT_I64 : VOPC_Real_si <0xb4>;
887defm V_CMPX_NE_I64 : VOPC_Real_si <0xb5>;
888defm V_CMPX_GE_I64 : VOPC_Real_si <0xb6>;
889defm V_CMPX_T_I64 : VOPC_Real_si <0xb7>;
890
891defm V_CMP_F_U32 : VOPC_Real_si <0xc0>;
892defm V_CMP_LT_U32 : VOPC_Real_si <0xc1>;
893defm V_CMP_EQ_U32 : VOPC_Real_si <0xc2>;
894defm V_CMP_LE_U32 : VOPC_Real_si <0xc3>;
895defm V_CMP_GT_U32 : VOPC_Real_si <0xc4>;
896defm V_CMP_NE_U32 : VOPC_Real_si <0xc5>;
897defm V_CMP_GE_U32 : VOPC_Real_si <0xc6>;
898defm V_CMP_T_U32 : VOPC_Real_si <0xc7>;
899
900defm V_CMPX_F_U32 : VOPC_Real_si <0xd0>;
901defm V_CMPX_LT_U32 : VOPC_Real_si <0xd1>;
902defm V_CMPX_EQ_U32 : VOPC_Real_si <0xd2>;
903defm V_CMPX_LE_U32 : VOPC_Real_si <0xd3>;
904defm V_CMPX_GT_U32 : VOPC_Real_si <0xd4>;
905defm V_CMPX_NE_U32 : VOPC_Real_si <0xd5>;
906defm V_CMPX_GE_U32 : VOPC_Real_si <0xd6>;
907defm V_CMPX_T_U32 : VOPC_Real_si <0xd7>;
908
909defm V_CMP_F_U64 : VOPC_Real_si <0xe0>;
910defm V_CMP_LT_U64 : VOPC_Real_si <0xe1>;
911defm V_CMP_EQ_U64 : VOPC_Real_si <0xe2>;
912defm V_CMP_LE_U64 : VOPC_Real_si <0xe3>;
913defm V_CMP_GT_U64 : VOPC_Real_si <0xe4>;
914defm V_CMP_NE_U64 : VOPC_Real_si <0xe5>;
915defm V_CMP_GE_U64 : VOPC_Real_si <0xe6>;
916defm V_CMP_T_U64 : VOPC_Real_si <0xe7>;
917
918defm V_CMPX_F_U64 : VOPC_Real_si <0xf0>;
919defm V_CMPX_LT_U64 : VOPC_Real_si <0xf1>;
920defm V_CMPX_EQ_U64 : VOPC_Real_si <0xf2>;
921defm V_CMPX_LE_U64 : VOPC_Real_si <0xf3>;
922defm V_CMPX_GT_U64 : VOPC_Real_si <0xf4>;
923defm V_CMPX_NE_U64 : VOPC_Real_si <0xf5>;
924defm V_CMPX_GE_U64 : VOPC_Real_si <0xf6>;
925defm V_CMPX_T_U64 : VOPC_Real_si <0xf7>;
926
927defm V_CMP_CLASS_F32 : VOPC_Real_si <0x88>;
928defm V_CMPX_CLASS_F32 : VOPC_Real_si <0x98>;
929defm V_CMP_CLASS_F64 : VOPC_Real_si <0xa8>;
930defm V_CMPX_CLASS_F64 : VOPC_Real_si <0xb8>;
931
932//===----------------------------------------------------------------------===//
933// VI
934//===----------------------------------------------------------------------===//
935
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]936multiclass VOPC_Real_vi <bits<10> op> {
937 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
938 def _e32_vi :
939 VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
940 VOPCe<op{7-0}>;
941
942 def _e64_vi :
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]943 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
944 VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]945 // Encoding used for VOPC instructions encoded as VOP3
946 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
947 bits<8> sdst;
948 let Inst{7-0} = sdst;
949 }
950 }
951
Sam Koltona568e3d2016-12-22 12:57:41 +0000[diff] [blame]952 def _sdwa_vi :
953 VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
954 VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]955
Sam Koltonf7659d712017-05-23 10:08:55 +0000[diff] [blame]956 def _sdwa_gfx9 :
957 VOP_SDWA9_Real <!cast<VOPC_SDWA9_Pseudo>(NAME#"_sdwa9")>,
958 VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA9_Pseudo>(NAME#"_sdwa9").Pfl>;
959
Valery Pykhtin355103f2016-09-23 09:08:07 +0000[diff] [blame]960 def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"),
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]961 !cast<Instruction>(NAME#"_e32_vi")> {
962 let AssemblerPredicate = isVI;
963 }
964}
965
Valery Pykhtin2828b9b2016-09-19 14:39:49 +0000[diff] [blame]966defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>;
967defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>;
968defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>;
969defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]970defm V_CMP_CLASS_F16 : VOPC_Real_vi <0x14>;
971defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>;
972
973defm V_CMP_F_F16 : VOPC_Real_vi <0x20>;
974defm V_CMP_LT_F16 : VOPC_Real_vi <0x21>;
975defm V_CMP_EQ_F16 : VOPC_Real_vi <0x22>;
976defm V_CMP_LE_F16 : VOPC_Real_vi <0x23>;
977defm V_CMP_GT_F16 : VOPC_Real_vi <0x24>;
978defm V_CMP_LG_F16 : VOPC_Real_vi <0x25>;
979defm V_CMP_GE_F16 : VOPC_Real_vi <0x26>;
980defm V_CMP_O_F16 : VOPC_Real_vi <0x27>;
981defm V_CMP_U_F16 : VOPC_Real_vi <0x28>;
982defm V_CMP_NGE_F16 : VOPC_Real_vi <0x29>;
983defm V_CMP_NLG_F16 : VOPC_Real_vi <0x2a>;
984defm V_CMP_NGT_F16 : VOPC_Real_vi <0x2b>;
985defm V_CMP_NLE_F16 : VOPC_Real_vi <0x2c>;
986defm V_CMP_NEQ_F16 : VOPC_Real_vi <0x2d>;
987defm V_CMP_NLT_F16 : VOPC_Real_vi <0x2e>;
988defm V_CMP_TRU_F16 : VOPC_Real_vi <0x2f>;
989
990defm V_CMPX_F_F16 : VOPC_Real_vi <0x30>;
991defm V_CMPX_LT_F16 : VOPC_Real_vi <0x31>;
992defm V_CMPX_EQ_F16 : VOPC_Real_vi <0x32>;
993defm V_CMPX_LE_F16 : VOPC_Real_vi <0x33>;
994defm V_CMPX_GT_F16 : VOPC_Real_vi <0x34>;
995defm V_CMPX_LG_F16 : VOPC_Real_vi <0x35>;
996defm V_CMPX_GE_F16 : VOPC_Real_vi <0x36>;
997defm V_CMPX_O_F16 : VOPC_Real_vi <0x37>;
998defm V_CMPX_U_F16 : VOPC_Real_vi <0x38>;
999defm V_CMPX_NGE_F16 : VOPC_Real_vi <0x39>;
1000defm V_CMPX_NLG_F16 : VOPC_Real_vi <0x3a>;
1001defm V_CMPX_NGT_F16 : VOPC_Real_vi <0x3b>;
1002defm V_CMPX_NLE_F16 : VOPC_Real_vi <0x3c>;
1003defm V_CMPX_NEQ_F16 : VOPC_Real_vi <0x3d>;
1004defm V_CMPX_NLT_F16 : VOPC_Real_vi <0x3e>;
1005defm V_CMPX_TRU_F16 : VOPC_Real_vi <0x3f>;
1006
1007defm V_CMP_F_F32 : VOPC_Real_vi <0x40>;
1008defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>;
1009defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>;
1010defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>;
1011defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>;
1012defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>;
1013defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>;
1014defm V_CMP_O_F32 : VOPC_Real_vi <0x47>;
1015defm V_CMP_U_F32 : VOPC_Real_vi <0x48>;
1016defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>;
1017defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>;
1018defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>;
1019defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>;
1020defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>;
1021defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>;
1022defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>;
1023
1024defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>;
1025defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>;
1026defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>;
1027defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>;
1028defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>;
1029defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>;
1030defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>;
1031defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>;
1032defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>;
1033defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>;
1034defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>;
1035defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>;
1036defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>;
1037defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>;
1038defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>;
1039defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>;
1040
1041defm V_CMP_F_F64 : VOPC_Real_vi <0x60>;
1042defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>;
1043defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>;
1044defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>;
1045defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>;
1046defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>;
1047defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>;
1048defm V_CMP_O_F64 : VOPC_Real_vi <0x67>;
1049defm V_CMP_U_F64 : VOPC_Real_vi <0x68>;
1050defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>;
1051defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>;
1052defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>;
1053defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>;
1054defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>;
1055defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>;
1056defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>;
1057
1058defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>;
1059defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>;
1060defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>;
1061defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>;
1062defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>;
1063defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>;
1064defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>;
1065defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>;
1066defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>;
1067defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>;
1068defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>;
1069defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>;
1070defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>;
1071defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>;
1072defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>;
1073defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>;
1074
Matt Arsenault18f56be2016-12-22 16:27:11 +0000[diff] [blame]1075defm V_CMP_F_I16 : VOPC_Real_vi <0xa0>;
1076defm V_CMP_LT_I16 : VOPC_Real_vi <0xa1>;
1077defm V_CMP_EQ_I16 : VOPC_Real_vi <0xa2>;
1078defm V_CMP_LE_I16 : VOPC_Real_vi <0xa3>;
1079defm V_CMP_GT_I16 : VOPC_Real_vi <0xa4>;
1080defm V_CMP_NE_I16 : VOPC_Real_vi <0xa5>;
1081defm V_CMP_GE_I16 : VOPC_Real_vi <0xa6>;
1082defm V_CMP_T_I16 : VOPC_Real_vi <0xa7>;
1083
1084defm V_CMP_F_U16 : VOPC_Real_vi <0xa8>;
1085defm V_CMP_LT_U16 : VOPC_Real_vi <0xa9>;
1086defm V_CMP_EQ_U16 : VOPC_Real_vi <0xaa>;
1087defm V_CMP_LE_U16 : VOPC_Real_vi <0xab>;
1088defm V_CMP_GT_U16 : VOPC_Real_vi <0xac>;
1089defm V_CMP_NE_U16 : VOPC_Real_vi <0xad>;
1090defm V_CMP_GE_U16 : VOPC_Real_vi <0xae>;
1091defm V_CMP_T_U16 : VOPC_Real_vi <0xaf>;
1092
Matt Arsenault3c97e202016-12-22 16:27:14 +0000[diff] [blame]1093defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>;
1094defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>;
1095defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>;
1096defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>;
1097defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>;
1098defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>;
1099defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>;
1100defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>;
1101
1102defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>;
1103defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>;
1104defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>;
1105defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>;
1106defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>;
1107defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>;
1108defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>;
1109defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>;
1110
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000[diff] [blame]1111defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>;
1112defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>;
1113defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>;
1114defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>;
1115defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>;
1116defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>;
1117defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>;
1118defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>;
1119
1120defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>;
1121defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>;
1122defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>;
1123defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>;
1124defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>;
1125defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>;
1126defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>;
1127defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>;
1128
1129defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>;
1130defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>;
1131defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>;
1132defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>;
1133defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>;
1134defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>;
1135defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>;
1136defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>;
1137
1138defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>;
1139defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>;
1140defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>;
1141defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>;
1142defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>;
1143defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>;
1144defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>;
1145defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>;
1146
1147defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>;
1148defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>;
1149defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>;
1150defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>;
1151defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>;
1152defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>;
1153defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>;
1154defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>;
1155
1156defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>;
1157defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>;
1158defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>;
1159defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>;
1160defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>;
1161defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>;
1162defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>;
1163defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>;
1164
1165defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>;
1166defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>;
1167defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>;
1168defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>;
1169defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>;
1170defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>;
1171defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>;
1172defm V_CMP_T_U64 : VOPC_Real_vi <0xef>;
1173
1174defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>;
1175defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>;
1176defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>;
1177defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>;
1178defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>;
1179defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>;
1180defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>;
1181defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>;