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Changpeng Fangb28fe032016-09-01 17:54:54 +00001//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class MIMG_Mask <string op, int channels> {
11 string Op = op;
12 int Channels = channels;
13}
14
15class mimg <bits<7> si, bits<7> vi = si> {
16 field bits<7> SI = si;
17 field bits<7> VI = vi;
18}
19
20class MIMG_Helper <dag outs, dag ins, string asm,
21 string dns=""> : MIMG<outs, ins, asm,[]> {
22 let mayLoad = 1;
23 let mayStore = 0;
24 let hasPostISelHook = 1;
25 let DecoderNamespace = dns;
26 let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
27 let AsmMatchConverter = "cvtMIMG";
Tom Stellard244891d2016-12-20 15:52:17 +000028 let usesCustomInserter = 1;
Marek Olsakb83f5c92017-07-04 14:43:38 +000029 let SchedRW = [WriteVMEM];
Changpeng Fangb28fe032016-09-01 17:54:54 +000030}
31
32class MIMG_NoSampler_Helper <bits<7> op, string asm,
33 RegisterClass dst_rc,
34 RegisterClass addr_rc,
Changpeng Fang4737e892018-01-18 22:08:53 +000035 bit d16_bit=0,
Changpeng Fangb28fe032016-09-01 17:54:54 +000036 string dns=""> : MIMG_Helper <
37 (outs dst_rc:$vdata),
38 (ins addr_rc:$vaddr, SReg_256:$srsrc,
Matt Arsenault4b6a6cc2016-10-28 21:55:08 +000039 dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
Changpeng Fangb28fe032016-09-01 17:54:54 +000040 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
Changpeng Fang4737e892018-01-18 22:08:53 +000041 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
Changpeng Fangb28fe032016-09-01 17:54:54 +000042 dns>, MIMGe<op> {
43 let ssamp = 0;
Changpeng Fang4737e892018-01-18 22:08:53 +000044 let D16 = d16;
45}
46
47multiclass MIMG_NoSampler_Src_Helper_Helper <bits<7> op, string asm,
48 RegisterClass dst_rc,
49 int channels, bit d16_bit,
50 string suffix> {
51 def _V1 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, d16_bit,
52 !if(!eq(channels, 1), "AMDGPU", "")>,
53 MIMG_Mask<asm#"_V1"#suffix, channels>;
54 def _V2 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, d16_bit>,
55 MIMG_Mask<asm#"_V2"#suffix, channels>;
56 def _V4 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, d16_bit>,
57 MIMG_Mask<asm#"_V4"#suffix, channels>;
Changpeng Fangb28fe032016-09-01 17:54:54 +000058}
59
60multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
61 RegisterClass dst_rc,
62 int channels> {
Changpeng Fang4737e892018-01-18 22:08:53 +000063 defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 0, "">;
64
65 let d16 = 1 in {
66 let SubtargetPredicate = HasPackedD16VMem in {
67 defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16">;
68 } // End HasPackedD16VMem.
69
70 let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
71 defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16_gfx80">;
72 } // End HasUnpackedD16VMem.
73 } // End d16 = 1.
Changpeng Fangb28fe032016-09-01 17:54:54 +000074}
75
76multiclass MIMG_NoSampler <bits<7> op, string asm> {
77 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
78 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
79 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
80 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
81}
82
83class MIMG_Store_Helper <bits<7> op, string asm,
84 RegisterClass data_rc,
Matt Arsenaultcad7fa82017-12-13 21:07:51 +000085 RegisterClass addr_rc,
Changpeng Fang4737e892018-01-18 22:08:53 +000086 bit d16_bit=0,
Matt Arsenaultcad7fa82017-12-13 21:07:51 +000087 string dns = ""> : MIMG_Helper <
Changpeng Fangb28fe032016-09-01 17:54:54 +000088 (outs),
89 (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
Matt Arsenault4b6a6cc2016-10-28 21:55:08 +000090 dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
Changpeng Fangb28fe032016-09-01 17:54:54 +000091 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
Changpeng Fang4737e892018-01-18 22:08:53 +000092 asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""), dns>, MIMGe<op> {
Changpeng Fangb28fe032016-09-01 17:54:54 +000093 let ssamp = 0;
Matt Arsenaultd94b63d2017-12-29 17:18:18 +000094 let mayLoad = 0;
Changpeng Fangb28fe032016-09-01 17:54:54 +000095 let mayStore = 1;
Matt Arsenaultd94b63d2017-12-29 17:18:18 +000096 let hasSideEffects = 0;
Changpeng Fangb28fe032016-09-01 17:54:54 +000097 let hasPostISelHook = 0;
98 let DisableWQM = 1;
Changpeng Fang4737e892018-01-18 22:08:53 +000099 let D16 = d16;
100}
101
102multiclass MIMG_Store_Addr_Helper_Helper <bits<7> op, string asm,
103 RegisterClass data_rc,
104 int channels, bit d16_bit,
105 string suffix> {
106 def _V1 # suffix : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, d16_bit,
107 !if(!eq(channels, 1), "AMDGPU", "")>,
108 MIMG_Mask<asm#"_V1"#suffix, channels>;
109 def _V2 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_64, d16_bit>,
110 MIMG_Mask<asm#"_V2"#suffix, channels>;
111 def _V4 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_128, d16_bit>,
112 MIMG_Mask<asm#"_V4"#suffix, channels>;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000113}
114
115multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm,
116 RegisterClass data_rc,
117 int channels> {
Changpeng Fang4737e892018-01-18 22:08:53 +0000118 defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 0, "">;
119
120 let d16 = 1 in {
121 let SubtargetPredicate = HasPackedD16VMem in {
122 defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16">;
123 } // End HasPackedD16VMem.
124
125 let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
126 defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16_gfx80">;
127 } // End HasUnpackedD16VMem.
128 } // End d16 = 1.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000129}
130
131multiclass MIMG_Store <bits<7> op, string asm> {
132 defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
133 defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 2>;
134 defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 3>;
135 defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>;
136}
137
138class MIMG_Atomic_Helper <string asm, RegisterClass data_rc,
139 RegisterClass addr_rc> : MIMG_Helper <
140 (outs data_rc:$vdst),
141 (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
Matt Arsenault4b6a6cc2016-10-28 21:55:08 +0000142 dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000143 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
Matt Arsenaultd94b63d2017-12-29 17:18:18 +0000144 asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"> {
145 let mayLoad = 1;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000146 let mayStore = 1;
Matt Arsenaultd94b63d2017-12-29 17:18:18 +0000147 let hasSideEffects = 1; // FIXME: Remove this
Changpeng Fangb28fe032016-09-01 17:54:54 +0000148 let hasPostISelHook = 0;
149 let DisableWQM = 1;
150 let Constraints = "$vdst = $vdata";
151 let AsmMatchConverter = "cvtMIMGAtomic";
152}
153
154class MIMG_Atomic_Real_si<mimg op, string name, string asm,
155 RegisterClass data_rc, RegisterClass addr_rc> :
156 MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
157 SIMCInstr<name, SIEncodingFamily.SI>,
158 MIMGe<op.SI> {
159 let isCodeGenOnly = 0;
160 let AssemblerPredicates = [isSICI];
161 let DecoderNamespace = "SICI";
162 let DisableDecoder = DisableSIDecoder;
163}
164
165class MIMG_Atomic_Real_vi<mimg op, string name, string asm,
166 RegisterClass data_rc, RegisterClass addr_rc> :
167 MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
168 SIMCInstr<name, SIEncodingFamily.VI>,
169 MIMGe<op.VI> {
170 let isCodeGenOnly = 0;
171 let AssemblerPredicates = [isVI];
172 let DecoderNamespace = "VI";
173 let DisableDecoder = DisableVIDecoder;
174}
175
176multiclass MIMG_Atomic_Helper_m <mimg op, string name, string asm,
177 RegisterClass data_rc, RegisterClass addr_rc> {
178 let isPseudo = 1, isCodeGenOnly = 1 in {
179 def "" : MIMG_Atomic_Helper<asm, data_rc, addr_rc>,
180 SIMCInstr<name, SIEncodingFamily.NONE>;
181 }
182
183 let ssamp = 0 in {
184 def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc>;
185
186 def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc>;
187 }
188}
189
190multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> {
191 defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32>;
192 defm _V2 : MIMG_Atomic_Helper_m <op, asm # "_V2", asm, data_rc, VReg_64>;
193 defm _V4 : MIMG_Atomic_Helper_m <op, asm # "_V3", asm, data_rc, VReg_128>;
194}
195
196class MIMG_Sampler_Helper <bits<7> op, string asm,
197 RegisterClass dst_rc,
198 RegisterClass src_rc,
Sam Koltonc01faa32016-11-15 13:39:07 +0000199 bit wqm,
Changpeng Fang4737e892018-01-18 22:08:53 +0000200 bit d16_bit=0,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000201 string dns=""> : MIMG_Helper <
202 (outs dst_rc:$vdata),
203 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
Matt Arsenault4b6a6cc2016-10-28 21:55:08 +0000204 dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000205 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
Changpeng Fang4737e892018-01-18 22:08:53 +0000206 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
Changpeng Fangb28fe032016-09-01 17:54:54 +0000207 dns>, MIMGe<op> {
208 let WQM = wqm;
Changpeng Fang4737e892018-01-18 22:08:53 +0000209 let D16 = d16;
210}
211
212multiclass MIMG_Sampler_Src_Helper_Helper <bits<7> op, string asm,
213 RegisterClass dst_rc,
214 int channels, bit wqm,
215 bit d16_bit, string suffix> {
216 def _V1 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm, d16_bit,
217 !if(!eq(channels, 1), "AMDGPU", "")>,
218 MIMG_Mask<asm#"_V1"#suffix, channels>;
219 def _V2 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>,
220 MIMG_Mask<asm#"_V2"#suffix, channels>;
221 def _V4 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>,
222 MIMG_Mask<asm#"_V4"#suffix, channels>;
223 def _V8 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>,
224 MIMG_Mask<asm#"_V8"#suffix, channels>;
225 def _V16 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm, d16_bit>,
226 MIMG_Mask<asm#"_V16"#suffix, channels>;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000227}
228
229multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
230 RegisterClass dst_rc,
Sam Koltonc01faa32016-11-15 13:39:07 +0000231 int channels, bit wqm> {
Changpeng Fang4737e892018-01-18 22:08:53 +0000232 defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 0, "">;
233
234 let d16 = 1 in {
235 let SubtargetPredicate = HasPackedD16VMem in {
236 defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16">;
237 } // End HasPackedD16VMem.
238
239 let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
240 defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16_gfx80">;
241 } // End HasUnpackedD16VMem.
242 } // End d16 = 1.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000243}
244
Sam Koltonc01faa32016-11-15 13:39:07 +0000245multiclass MIMG_Sampler <bits<7> op, string asm, bit wqm=0> {
Changpeng Fangb28fe032016-09-01 17:54:54 +0000246 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
247 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
248 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
249 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>;
250}
251
252multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>;
253
254class MIMG_Gather_Helper <bits<7> op, string asm,
255 RegisterClass dst_rc,
Changpeng Fang4737e892018-01-18 22:08:53 +0000256 RegisterClass src_rc, bit wqm, bit d16_bit=0> : MIMG <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000257 (outs dst_rc:$vdata),
258 (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
Matt Arsenault4b6a6cc2016-10-28 21:55:08 +0000259 dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000260 r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
Changpeng Fang4737e892018-01-18 22:08:53 +0000261 asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"#!if(d16_bit, " d16", ""),
Changpeng Fangb28fe032016-09-01 17:54:54 +0000262 []>, MIMGe<op> {
263 let mayLoad = 1;
264 let mayStore = 0;
265
266 // DMASK was repurposed for GATHER4. 4 components are always
267 // returned and DMASK works like a swizzle - it selects
268 // the component to fetch. The only useful DMASK values are
269 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
270 // (red,red,red,red) etc.) The ISA document doesn't mention
271 // this.
272 // Therefore, disable all code which updates DMASK by setting this:
273 let Gather4 = 1;
274 let hasPostISelHook = 0;
275 let WQM = wqm;
Changpeng Fang4737e892018-01-18 22:08:53 +0000276 let D16 = d16;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000277
278 let isAsmParserOnly = 1; // TBD: fix it later
279}
280
Changpeng Fang4737e892018-01-18 22:08:53 +0000281
282multiclass MIMG_Gather_Src_Helper_Helper <bits<7> op, string asm,
283 RegisterClass dst_rc,
284 int channels, bit wqm,
285 bit d16_bit, string suffix> {
286 def _V1 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm, d16_bit>,
287 MIMG_Mask<asm#"_V1"#suffix, channels>;
288 def _V2 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>,
289 MIMG_Mask<asm#"_V2"#suffix, channels>;
290 def _V4 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>,
291 MIMG_Mask<asm#"_V4"#suffix, channels>;
292 def _V8 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>,
293 MIMG_Mask<asm#"_V8"#suffix, channels>;
294 def _V16 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm, d16_bit>,
295 MIMG_Mask<asm#"_V16"#suffix, channels>;
296}
297
Changpeng Fangb28fe032016-09-01 17:54:54 +0000298multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
299 RegisterClass dst_rc,
Sam Koltonc01faa32016-11-15 13:39:07 +0000300 int channels, bit wqm> {
Changpeng Fang4737e892018-01-18 22:08:53 +0000301 defm : MIMG_Gather_Src_Helper_Helper<op, asm, dst_rc, channels, wqm, 0, "">;
302
303 let d16 = 1 in {
304 let SubtargetPredicate = HasPackedD16VMem in {
305 defm : MIMG_Gather_Src_Helper_Helper<op, asm, dst_rc, channels, wqm, 1, "_D16">;
306 } // End HasPackedD16VMem.
307
308 let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
309 defm : MIMG_Gather_Src_Helper_Helper<op, asm, dst_rc, channels, wqm, 1, "_D16_gfx80">;
310 } // End HasUnpackedD16VMem.
311 } // End d16 = 1.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000312}
313
Sam Koltonc01faa32016-11-15 13:39:07 +0000314multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
Changpeng Fangb28fe032016-09-01 17:54:54 +0000315 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
316 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
317 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;
318 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>;
319}
320
321multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>;
322
323//===----------------------------------------------------------------------===//
324// MIMG Instructions
325//===----------------------------------------------------------------------===//
326let SubtargetPredicate = isGCN in {
327defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
328defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
329//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
330//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
331//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
332//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
333defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
334defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
335//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
336//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
Matt Arsenault856777d2017-12-08 20:00:57 +0000337
338let mayLoad = 0, mayStore = 0 in {
Changpeng Fangb28fe032016-09-01 17:54:54 +0000339defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
Matt Arsenault856777d2017-12-08 20:00:57 +0000340}
341
Changpeng Fangb28fe032016-09-01 17:54:54 +0000342defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
343defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", VReg_64>;
344defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
345defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
346//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
347defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
348defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
349defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
350defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
351defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
352defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
353defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
354defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
355defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
356//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; -- not on VI
357//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
358//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
359defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">;
360defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">;
361defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
362defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
363defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
364defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">;
365defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">;
366defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
367defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">;
368defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">;
369defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
370defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
371defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
372defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">;
373defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">;
374defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
375defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">;
376defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">;
377defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
378defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
379defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
380defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">;
381defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">;
382defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
383defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">;
384defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">;
385defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
386defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
387defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
388defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">;
389defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">;
390defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
391defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">;
392defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">;
393defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
394defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">;
395defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">;
396defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
397defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">;
398defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">;
399defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
400defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">;
401defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">;
402defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
403defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">;
404defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">;
405defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
406defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">;
407defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
408defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
409defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">;
410defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">;
411defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
412defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">;
413defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">;
414defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
Matt Arsenault856777d2017-12-08 20:00:57 +0000415
416let mayLoad = 0, mayStore = 0 in {
Changpeng Fangb28fe032016-09-01 17:54:54 +0000417defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">;
Matt Arsenault856777d2017-12-08 20:00:57 +0000418}
419
Changpeng Fangb28fe032016-09-01 17:54:54 +0000420defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
421defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
422defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
423defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
424defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
425defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
426defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
427defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
428//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
429//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
430}
431
432/********** ======================= **********/
433/********** Image sampling patterns **********/
434/********** ======================= **********/
435
Changpeng Fang4737e892018-01-18 22:08:53 +0000436// ImageSample for amdgcn
Changpeng Fangb28fe032016-09-01 17:54:54 +0000437// TODO:
Changpeng Fang4737e892018-01-18 22:08:53 +0000438// 1. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128).
439// 2. Add A16 support when we pass address of half type.
440multiclass ImageSamplePattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt> {
Matt Arsenault90c75932017-10-03 00:06:41 +0000441 def : GCNPat<
Changpeng Fang8236fe12016-11-14 18:33:18 +0000442 (dt (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000443 i1:$slc, i1:$lwe, i1:$da)),
444 (opcode $addr, $rsrc, $sampler,
445 (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
446 0, 0, (as_i1imm $lwe), (as_i1imm $da))
447 >;
448}
449
Changpeng Fang4737e892018-01-18 22:08:53 +0000450multiclass ImageSampleDataPatterns<SDPatternOperator name, string opcode, ValueType dt, string suffix = ""> {
451 defm : ImageSamplePattern<name, !cast<MIMG>(opcode # _V1 # suffix), dt, f32>;
452 defm : ImageSamplePattern<name, !cast<MIMG>(opcode # _V2 # suffix), dt, v2f32>;
453 defm : ImageSamplePattern<name, !cast<MIMG>(opcode # _V4 # suffix), dt, v4f32>;
454 defm : ImageSamplePattern<name, !cast<MIMG>(opcode # _V8 # suffix), dt, v8f32>;
455 defm : ImageSamplePattern<name, !cast<MIMG>(opcode # _V16 # suffix), dt, v16f32>;
Changpeng Fang8236fe12016-11-14 18:33:18 +0000456}
457
Changpeng Fang4737e892018-01-18 22:08:53 +0000458// ImageSample patterns.
459multiclass ImageSamplePatterns<SDPatternOperator name, string opcode> {
460 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V1), f32>;
461 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
462 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
463
464 let SubtargetPredicate = HasUnpackedD16VMem in {
465 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16_gfx80">;
466 } // End HasUnpackedD16VMem.
467
468 let SubtargetPredicate = HasPackedD16VMem in {
469 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16">;
470 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V1), v2f16, "_D16">;
471 } // End HasPackedD16VMem.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000472}
473
Changpeng Fang4737e892018-01-18 22:08:53 +0000474// ImageSample alternative patterns for illegal vector half Types.
475multiclass ImageSampleAltPatterns<SDPatternOperator name, string opcode> {
476 let SubtargetPredicate = HasUnpackedD16VMem in {
477 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16_gfx80">;
478 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V4), v4i32, "_D16_gfx80">;
479 } // End HasUnpackedD16VMem.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000480
Changpeng Fang4737e892018-01-18 22:08:53 +0000481 let SubtargetPredicate = HasPackedD16VMem in {
482 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V1), i32, "_D16">;
483 defm : ImageSampleDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16">;
484 } // End HasPackedD16VMem.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000485}
486
Changpeng Fang4737e892018-01-18 22:08:53 +0000487// ImageLoad for amdgcn.
Changpeng Fang8236fe12016-11-14 18:33:18 +0000488multiclass ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt> {
Matt Arsenault90c75932017-10-03 00:06:41 +0000489 def : GCNPat <
Changpeng Fang8236fe12016-11-14 18:33:18 +0000490 (dt (name vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, i1:$lwe,
Tom Stellardfac248c2016-10-12 16:35:29 +0000491 i1:$da)),
492 (opcode $addr, $rsrc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000493 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
Tom Stellardfac248c2016-10-12 16:35:29 +0000494 0, 0, (as_i1imm $lwe), (as_i1imm $da))
495 >;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000496}
497
Changpeng Fang4737e892018-01-18 22:08:53 +0000498multiclass ImageLoadDataPatterns<SDPatternOperator name, string opcode, ValueType dt, string suffix = ""> {
499 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V1 # suffix), dt, i32>;
500 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V2 # suffix), dt, v2i32>;
501 defm : ImageLoadPattern<name, !cast<MIMG>(opcode # _V4 # suffix), dt, v4i32>;
Tom Stellardfac248c2016-10-12 16:35:29 +0000502}
503
Changpeng Fang4737e892018-01-18 22:08:53 +0000504// ImageLoad patterns.
Changpeng Fang8236fe12016-11-14 18:33:18 +0000505// TODO: support v3f32.
506multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
507 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), f32>;
508 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
509 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
Changpeng Fang4737e892018-01-18 22:08:53 +0000510
511 let SubtargetPredicate = HasUnpackedD16VMem in {
512 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16_gfx80">;
513 } // End HasUnpackedD16VMem.
514
515 let SubtargetPredicate = HasPackedD16VMem in {
516 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16">;
517 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), v2f16, "_D16">;
518 } // End HasPackedD16VMem.
Changpeng Fang8236fe12016-11-14 18:33:18 +0000519}
520
Changpeng Fang4737e892018-01-18 22:08:53 +0000521// ImageLoad alternative patterns for illegal vector half Types.
522multiclass ImageLoadAltPatterns<SDPatternOperator name, string opcode> {
523 let SubtargetPredicate = HasUnpackedD16VMem in {
524 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16_gfx80">;
525 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V4), v4i32, "_D16_gfx80">;
526 } // End HasUnPackedD16VMem.
527
528 let SubtargetPredicate = HasPackedD16VMem in {
529 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V1), i32, "_D16">;
530 defm : ImageLoadDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16">;
531 } // End HasPackedD16VMem.
532}
533
534// ImageStore for amdgcn.
Changpeng Fang8236fe12016-11-14 18:33:18 +0000535multiclass ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType dt, ValueType vt> {
Matt Arsenault90c75932017-10-03 00:06:41 +0000536 def : GCNPat <
Changpeng Fang8236fe12016-11-14 18:33:18 +0000537 (name dt:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc,
Tom Stellardfac248c2016-10-12 16:35:29 +0000538 i1:$lwe, i1:$da),
539 (opcode $data, $addr, $rsrc,
Changpeng Fangb28fe032016-09-01 17:54:54 +0000540 (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
Tom Stellardfac248c2016-10-12 16:35:29 +0000541 0, 0, (as_i1imm $lwe), (as_i1imm $da))
542 >;
543}
Changpeng Fangb28fe032016-09-01 17:54:54 +0000544
Changpeng Fang4737e892018-01-18 22:08:53 +0000545multiclass ImageStoreDataPatterns<SDPatternOperator name, string opcode, ValueType dt, string suffix = ""> {
546 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V1 # suffix), dt, i32>;
547 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V2 # suffix), dt, v2i32>;
548 defm : ImageStorePattern<name, !cast<MIMG>(opcode # _V4 # suffix), dt, v4i32>;
Changpeng Fang8236fe12016-11-14 18:33:18 +0000549}
550
Changpeng Fang4737e892018-01-18 22:08:53 +0000551// ImageStore patterns.
Changpeng Fang8236fe12016-11-14 18:33:18 +0000552// TODO: support v3f32.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000553multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
Changpeng Fang8236fe12016-11-14 18:33:18 +0000554 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), f32>;
555 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V2), v2f32>;
556 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V4), v4f32>;
Changpeng Fang4737e892018-01-18 22:08:53 +0000557
558 let SubtargetPredicate = HasUnpackedD16VMem in {
559 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16_gfx80">;
560 } // End HasUnpackedD16VMem.
561
562 let SubtargetPredicate = HasPackedD16VMem in {
563 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), f16, "_D16">;
564 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), v2f16, "_D16">;
565 } // End HasPackedD16VMem.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000566}
567
Changpeng Fang4737e892018-01-18 22:08:53 +0000568// ImageStore alternative patterns.
569multiclass ImageStoreAltPatterns<SDPatternOperator name, string opcode> {
570 let SubtargetPredicate = HasUnpackedD16VMem in {
571 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16_gfx80">;
572 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V4), v4i32, "_D16_gfx80">;
573 } // End HasUnpackedD16VMem.
574
575 let SubtargetPredicate = HasPackedD16VMem in {
576 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V1), i32, "_D16">;
577 defm : ImageStoreDataPatterns<name, !cast<string>(opcode # _V2), v2i32, "_D16">;
578 } // End HasPackedD16VMem.
579}
580
581// ImageAtomic for amdgcn.
Matt Arsenault90c75932017-10-03 00:06:41 +0000582class ImageAtomicPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000583 (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc),
584 (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da))
585>;
586
Changpeng Fang4737e892018-01-18 22:08:53 +0000587// ImageAtomic patterns.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000588multiclass ImageAtomicPatterns<SDPatternOperator name, string opcode> {
589 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V1), i32>;
590 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V2), v2i32>;
591 def : ImageAtomicPattern<name, !cast<MIMG>(opcode # _V4), v4i32>;
592}
593
Changpeng Fang4737e892018-01-18 22:08:53 +0000594// ImageAtomicCmpSwap for amdgcn.
Matt Arsenault90c75932017-10-03 00:06:41 +0000595class ImageAtomicCmpSwapPattern<MIMG opcode, ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000596 (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc,
597 imm:$r128, imm:$da, imm:$slc),
598 (EXTRACT_SUBREG
599 (opcode (REG_SEQUENCE VReg_64, $vsrc, sub0, $vcmp, sub1),
600 $addr, $rsrc, 3, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)),
601 sub0)
602>;
603
Changpeng Fangb28fe032016-09-01 17:54:54 +0000604// ======= amdgcn Image Intrinsics ==============
605
Changpeng Fang4737e892018-01-18 22:08:53 +0000606// Image load.
Changpeng Fangb28fe032016-09-01 17:54:54 +0000607defm : ImageLoadPatterns<int_amdgcn_image_load, "IMAGE_LOAD">;
608defm : ImageLoadPatterns<int_amdgcn_image_load_mip, "IMAGE_LOAD_MIP">;
Changpeng Fang8236fe12016-11-14 18:33:18 +0000609defm : ImageLoadPatterns<int_amdgcn_image_getresinfo, "IMAGE_GET_RESINFO">;
Changpeng Fang4737e892018-01-18 22:08:53 +0000610defm : ImageLoadAltPatterns<SIImage_load, "IMAGE_LOAD">;
611defm : ImageLoadAltPatterns<SIImage_load_mip, "IMAGE_LOAD_MIP">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000612
Changpeng Fang4737e892018-01-18 22:08:53 +0000613// Image store.
614defm : ImageStorePatterns<SIImage_store, "IMAGE_STORE">;
615defm : ImageStorePatterns<SIImage_store_mip, "IMAGE_STORE_MIP">;
616defm : ImageStoreAltPatterns<SIImage_store, "IMAGE_STORE">;
617defm : ImageStoreAltPatterns<SIImage_store_mip, "IMAGE_STORE_MIP">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000618
Changpeng Fang4737e892018-01-18 22:08:53 +0000619// Basic sample.
620defm : ImageSamplePatterns<int_amdgcn_image_sample, "IMAGE_SAMPLE">;
621defm : ImageSamplePatterns<int_amdgcn_image_sample_cl, "IMAGE_SAMPLE_CL">;
622defm : ImageSamplePatterns<int_amdgcn_image_sample_d, "IMAGE_SAMPLE_D">;
623defm : ImageSamplePatterns<int_amdgcn_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
624defm : ImageSamplePatterns<int_amdgcn_image_sample_l, "IMAGE_SAMPLE_L">;
625defm : ImageSamplePatterns<int_amdgcn_image_sample_b, "IMAGE_SAMPLE_B">;
626defm : ImageSamplePatterns<int_amdgcn_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
627defm : ImageSamplePatterns<int_amdgcn_image_sample_lz, "IMAGE_SAMPLE_LZ">;
628defm : ImageSamplePatterns<int_amdgcn_image_sample_cd, "IMAGE_SAMPLE_CD">;
629defm : ImageSamplePatterns<int_amdgcn_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000630
Changpeng Fang4737e892018-01-18 22:08:53 +0000631// Sample with comparison.
632defm : ImageSamplePatterns<int_amdgcn_image_sample_c, "IMAGE_SAMPLE_C">;
633defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
634defm : ImageSamplePatterns<int_amdgcn_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
635defm : ImageSamplePatterns<int_amdgcn_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
636defm : ImageSamplePatterns<int_amdgcn_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
637defm : ImageSamplePatterns<int_amdgcn_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
638defm : ImageSamplePatterns<int_amdgcn_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
639defm : ImageSamplePatterns<int_amdgcn_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
640defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
641defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000642
Changpeng Fang4737e892018-01-18 22:08:53 +0000643// Sample with offsets.
644defm : ImageSamplePatterns<int_amdgcn_image_sample_o, "IMAGE_SAMPLE_O">;
645defm : ImageSamplePatterns<int_amdgcn_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
646defm : ImageSamplePatterns<int_amdgcn_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
647defm : ImageSamplePatterns<int_amdgcn_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
648defm : ImageSamplePatterns<int_amdgcn_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
649defm : ImageSamplePatterns<int_amdgcn_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
650defm : ImageSamplePatterns<int_amdgcn_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
651defm : ImageSamplePatterns<int_amdgcn_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
652defm : ImageSamplePatterns<int_amdgcn_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
653defm : ImageSamplePatterns<int_amdgcn_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000654
Changpeng Fang4737e892018-01-18 22:08:53 +0000655// Sample with comparison and offsets.
656defm : ImageSamplePatterns<int_amdgcn_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
657defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
658defm : ImageSamplePatterns<int_amdgcn_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
659defm : ImageSamplePatterns<int_amdgcn_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
660defm : ImageSamplePatterns<int_amdgcn_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
661defm : ImageSamplePatterns<int_amdgcn_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
662defm : ImageSamplePatterns<int_amdgcn_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
663defm : ImageSamplePatterns<int_amdgcn_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
664defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
665defm : ImageSamplePatterns<int_amdgcn_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000666
Changpeng Fang4737e892018-01-18 22:08:53 +0000667// Basic gather4.
668defm : ImageSamplePatterns<int_amdgcn_image_gather4, "IMAGE_GATHER4">;
669defm : ImageSamplePatterns<int_amdgcn_image_gather4_cl, "IMAGE_GATHER4_CL">;
670defm : ImageSamplePatterns<int_amdgcn_image_gather4_l, "IMAGE_GATHER4_L">;
671defm : ImageSamplePatterns<int_amdgcn_image_gather4_b, "IMAGE_GATHER4_B">;
672defm : ImageSamplePatterns<int_amdgcn_image_gather4_b_cl, "IMAGE_GATHER4_B_CL">;
673defm : ImageSamplePatterns<int_amdgcn_image_gather4_lz, "IMAGE_GATHER4_LZ">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000674
Changpeng Fang4737e892018-01-18 22:08:53 +0000675// Gather4 with comparison.
676defm : ImageSamplePatterns<int_amdgcn_image_gather4_c, "IMAGE_GATHER4_C">;
677defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_cl, "IMAGE_GATHER4_C_CL">;
678defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_l, "IMAGE_GATHER4_C_L">;
679defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_b, "IMAGE_GATHER4_C_B">;
680defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_b_cl, "IMAGE_GATHER4_C_B_CL">;
681defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_lz, "IMAGE_GATHER4_C_LZ">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000682
Changpeng Fang4737e892018-01-18 22:08:53 +0000683// Gather4 with offsets.
684defm : ImageSamplePatterns<int_amdgcn_image_gather4_o, "IMAGE_GATHER4_O">;
685defm : ImageSamplePatterns<int_amdgcn_image_gather4_cl_o, "IMAGE_GATHER4_CL_O">;
686defm : ImageSamplePatterns<int_amdgcn_image_gather4_l_o, "IMAGE_GATHER4_L_O">;
687defm : ImageSamplePatterns<int_amdgcn_image_gather4_b_o, "IMAGE_GATHER4_B_O">;
688defm : ImageSamplePatterns<int_amdgcn_image_gather4_b_cl_o, "IMAGE_GATHER4_B_CL_O">;
689defm : ImageSamplePatterns<int_amdgcn_image_gather4_lz_o, "IMAGE_GATHER4_LZ_O">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000690
Changpeng Fang4737e892018-01-18 22:08:53 +0000691// Gather4 with comparison and offsets.
692defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_o, "IMAGE_GATHER4_C_O">;
693defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_cl_o, "IMAGE_GATHER4_C_CL_O">;
694defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_l_o, "IMAGE_GATHER4_C_L_O">;
695defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_b_o, "IMAGE_GATHER4_C_B_O">;
696defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_b_cl_o, "IMAGE_GATHER4_C_B_CL_O">;
697defm : ImageSamplePatterns<int_amdgcn_image_gather4_c_lz_o, "IMAGE_GATHER4_C_LZ_O">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000698
Changpeng Fang4737e892018-01-18 22:08:53 +0000699// Basic sample alternative.
700defm : ImageSampleAltPatterns<SIImage_sample, "IMAGE_SAMPLE">;
701defm : ImageSampleAltPatterns<SIImage_sample_cl, "IMAGE_SAMPLE_CL">;
702defm : ImageSampleAltPatterns<SIImage_sample_d, "IMAGE_SAMPLE_D">;
703defm : ImageSampleAltPatterns<SIImage_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
704defm : ImageSampleAltPatterns<SIImage_sample_l, "IMAGE_SAMPLE_L">;
705defm : ImageSampleAltPatterns<SIImage_sample_b, "IMAGE_SAMPLE_B">;
706defm : ImageSampleAltPatterns<SIImage_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
707defm : ImageSampleAltPatterns<SIImage_sample_lz, "IMAGE_SAMPLE_LZ">;
708defm : ImageSampleAltPatterns<SIImage_sample_cd, "IMAGE_SAMPLE_CD">;
709defm : ImageSampleAltPatterns<SIImage_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
710
711// Sample with comparison alternative.
712defm : ImageSampleAltPatterns<SIImage_sample_c, "IMAGE_SAMPLE_C">;
713defm : ImageSampleAltPatterns<SIImage_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
714defm : ImageSampleAltPatterns<SIImage_sample_c_d, "IMAGE_SAMPLE_C_D">;
715defm : ImageSampleAltPatterns<SIImage_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
716defm : ImageSampleAltPatterns<SIImage_sample_c_l, "IMAGE_SAMPLE_C_L">;
717defm : ImageSampleAltPatterns<SIImage_sample_c_b, "IMAGE_SAMPLE_C_B">;
718defm : ImageSampleAltPatterns<SIImage_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
719defm : ImageSampleAltPatterns<SIImage_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
720defm : ImageSampleAltPatterns<SIImage_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
721defm : ImageSampleAltPatterns<SIImage_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
722
723// Sample with offsets alternative.
724defm : ImageSampleAltPatterns<SIImage_sample_o, "IMAGE_SAMPLE_O">;
725defm : ImageSampleAltPatterns<SIImage_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
726defm : ImageSampleAltPatterns<SIImage_sample_d_o, "IMAGE_SAMPLE_D_O">;
727defm : ImageSampleAltPatterns<SIImage_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
728defm : ImageSampleAltPatterns<SIImage_sample_l_o, "IMAGE_SAMPLE_L_O">;
729defm : ImageSampleAltPatterns<SIImage_sample_b_o, "IMAGE_SAMPLE_B_O">;
730defm : ImageSampleAltPatterns<SIImage_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
731defm : ImageSampleAltPatterns<SIImage_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
732defm : ImageSampleAltPatterns<SIImage_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
733defm : ImageSampleAltPatterns<SIImage_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
734
735// Sample with comparison and offsets alternative.
736defm : ImageSampleAltPatterns<SIImage_sample_c_o, "IMAGE_SAMPLE_C_O">;
737defm : ImageSampleAltPatterns<SIImage_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
738defm : ImageSampleAltPatterns<SIImage_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
739defm : ImageSampleAltPatterns<SIImage_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
740defm : ImageSampleAltPatterns<SIImage_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
741defm : ImageSampleAltPatterns<SIImage_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
742defm : ImageSampleAltPatterns<SIImage_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
743defm : ImageSampleAltPatterns<SIImage_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
744defm : ImageSampleAltPatterns<SIImage_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
745defm : ImageSampleAltPatterns<SIImage_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
746
747// Basic gather4 alternative.
748defm : ImageSampleAltPatterns<SIImage_gather4, "IMAGE_GATHER4">;
749defm : ImageSampleAltPatterns<SIImage_gather4_cl, "IMAGE_GATHER4_CL">;
750defm : ImageSampleAltPatterns<SIImage_gather4_l, "IMAGE_GATHER4_L">;
751defm : ImageSampleAltPatterns<SIImage_gather4_b, "IMAGE_GATHER4_B">;
752defm : ImageSampleAltPatterns<SIImage_gather4_b_cl, "IMAGE_GATHER4_B_CL">;
753defm : ImageSampleAltPatterns<SIImage_gather4_lz, "IMAGE_GATHER4_LZ">;
754
755// Gather4 with comparison alternative.
756defm : ImageSampleAltPatterns<SIImage_gather4_c, "IMAGE_GATHER4_C">;
757defm : ImageSampleAltPatterns<SIImage_gather4_c_cl, "IMAGE_GATHER4_C_CL">;
758defm : ImageSampleAltPatterns<SIImage_gather4_c_l, "IMAGE_GATHER4_C_L">;
759defm : ImageSampleAltPatterns<SIImage_gather4_c_b, "IMAGE_GATHER4_C_B">;
760defm : ImageSampleAltPatterns<SIImage_gather4_c_b_cl, "IMAGE_GATHER4_C_B_CL">;
761defm : ImageSampleAltPatterns<SIImage_gather4_c_lz, "IMAGE_GATHER4_C_LZ">;
762
763// Gather4 with offsets alternative.
764defm : ImageSampleAltPatterns<SIImage_gather4_o, "IMAGE_GATHER4_O">;
765defm : ImageSampleAltPatterns<SIImage_gather4_cl_o, "IMAGE_GATHER4_CL_O">;
766defm : ImageSampleAltPatterns<SIImage_gather4_l_o, "IMAGE_GATHER4_L_O">;
767defm : ImageSampleAltPatterns<SIImage_gather4_b_o, "IMAGE_GATHER4_B_O">;
768defm : ImageSampleAltPatterns<SIImage_gather4_b_cl_o, "IMAGE_GATHER4_B_CL_O">;
769defm : ImageSampleAltPatterns<SIImage_gather4_lz_o, "IMAGE_GATHER4_LZ_O">;
770
771// Gather4 with comparison and offsets alternative.
772defm : ImageSampleAltPatterns<SIImage_gather4_c_o, "IMAGE_GATHER4_C_O">;
773defm : ImageSampleAltPatterns<SIImage_gather4_c_cl_o, "IMAGE_GATHER4_C_CL_O">;
774defm : ImageSampleAltPatterns<SIImage_gather4_c_l_o, "IMAGE_GATHER4_C_L_O">;
775defm : ImageSampleAltPatterns<SIImage_gather4_c_b_o, "IMAGE_GATHER4_C_B_O">;
776defm : ImageSampleAltPatterns<SIImage_gather4_c_b_cl_o, "IMAGE_GATHER4_C_B_CL_O">;
777defm : ImageSampleAltPatterns<SIImage_gather4_c_lz_o, "IMAGE_GATHER4_C_LZ_O">;
778
779defm : ImageSamplePatterns<int_amdgcn_image_getlod, "IMAGE_GET_LOD">;
Changpeng Fangb28fe032016-09-01 17:54:54 +0000780
781// Image atomics
782defm : ImageAtomicPatterns<int_amdgcn_image_atomic_swap, "IMAGE_ATOMIC_SWAP">;
783def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V1, i32>;
784def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V2, v2i32>;
785def : ImageAtomicCmpSwapPattern<IMAGE_ATOMIC_CMPSWAP_V4, v4i32>;
786defm : ImageAtomicPatterns<int_amdgcn_image_atomic_add, "IMAGE_ATOMIC_ADD">;
787defm : ImageAtomicPatterns<int_amdgcn_image_atomic_sub, "IMAGE_ATOMIC_SUB">;
788defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smin, "IMAGE_ATOMIC_SMIN">;
789defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umin, "IMAGE_ATOMIC_UMIN">;
790defm : ImageAtomicPatterns<int_amdgcn_image_atomic_smax, "IMAGE_ATOMIC_SMAX">;
791defm : ImageAtomicPatterns<int_amdgcn_image_atomic_umax, "IMAGE_ATOMIC_UMAX">;
792defm : ImageAtomicPatterns<int_amdgcn_image_atomic_and, "IMAGE_ATOMIC_AND">;
793defm : ImageAtomicPatterns<int_amdgcn_image_atomic_or, "IMAGE_ATOMIC_OR">;
794defm : ImageAtomicPatterns<int_amdgcn_image_atomic_xor, "IMAGE_ATOMIC_XOR">;
795defm : ImageAtomicPatterns<int_amdgcn_image_atomic_inc, "IMAGE_ATOMIC_INC">;
796defm : ImageAtomicPatterns<int_amdgcn_image_atomic_dec, "IMAGE_ATOMIC_DEC">;
797
798/* SIsample for simple 1D texture lookup */
Matt Arsenault90c75932017-10-03 00:06:41 +0000799def : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000800 (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
801 (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
802>;
803
Matt Arsenault90c75932017-10-03 00:06:41 +0000804class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000805 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
806 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
807>;
808
Matt Arsenault90c75932017-10-03 00:06:41 +0000809class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000810 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
811 (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
812>;
813
Matt Arsenault90c75932017-10-03 00:06:41 +0000814class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000815 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
816 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
817>;
818
819class SampleShadowPattern<SDNode name, MIMG opcode,
Matt Arsenault90c75932017-10-03 00:06:41 +0000820 ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000821 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
822 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
823>;
824
825class SampleShadowArrayPattern<SDNode name, MIMG opcode,
Matt Arsenault90c75932017-10-03 00:06:41 +0000826 ValueType vt> : GCNPat <
Changpeng Fangb28fe032016-09-01 17:54:54 +0000827 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
828 (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
829>;
830
831/* SIsample* for texture lookups consuming more address parameters */
832multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
833 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
834MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
835 def : SamplePattern <SIsample, sample, addr_type>;
836 def : SampleRectPattern <SIsample, sample, addr_type>;
837 def : SampleArrayPattern <SIsample, sample, addr_type>;
838 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
839 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
840
841 def : SamplePattern <SIsamplel, sample_l, addr_type>;
842 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
843 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
844 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
845
846 def : SamplePattern <SIsampleb, sample_b, addr_type>;
847 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
848 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
849 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
850
851 def : SamplePattern <SIsampled, sample_d, addr_type>;
852 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
853 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
854 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
855}
856
857defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
858 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
859 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
860 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
861 v2i32>;
862defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
863 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
864 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
865 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
866 v4i32>;
867defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
868 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
869 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
870 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
871 v8i32>;
872defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
873 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
874 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
875 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
876 v16i32>;