Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 1 | //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the targeting of the Machinelegalizer class for X86. |
| 11 | /// \todo This should be generated by TableGen. |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "X86LegalizerInfo.h" |
| 15 | #include "X86Subtarget.h" |
Igor Breger | 531a203 | 2017-03-26 08:11:12 +0000 | [diff] [blame] | 16 | #include "X86TargetMachine.h" |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/ValueTypes.h" |
| 18 | #include "llvm/IR/DerivedTypes.h" |
| 19 | #include "llvm/IR/Type.h" |
| 20 | #include "llvm/Target/TargetOpcodes.h" |
| 21 | |
| 22 | using namespace llvm; |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 23 | using namespace TargetOpcode; |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 24 | |
| 25 | #ifndef LLVM_BUILD_GLOBAL_ISEL |
| 26 | #error "You shouldn't build this" |
| 27 | #endif |
| 28 | |
Igor Breger | 531a203 | 2017-03-26 08:11:12 +0000 | [diff] [blame] | 29 | X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI, |
| 30 | const X86TargetMachine &TM) |
| 31 | : Subtarget(STI), TM(TM) { |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 32 | |
| 33 | setLegalizerInfo32bit(); |
| 34 | setLegalizerInfo64bit(); |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 35 | setLegalizerInfoSSE1(); |
| 36 | setLegalizerInfoSSE2(); |
Igor Breger | 605b965 | 2017-05-08 09:03:37 +0000 | [diff] [blame^] | 37 | setLegalizerInfoSSE41(); |
| 38 | setLegalizerInfoAVX2(); |
| 39 | setLegalizerInfoAVX512(); |
| 40 | setLegalizerInfoAVX512DQ(); |
| 41 | setLegalizerInfoAVX512BW(); |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 42 | |
| 43 | computeTables(); |
| 44 | } |
| 45 | |
| 46 | void X86LegalizerInfo::setLegalizerInfo32bit() { |
| 47 | |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 48 | if (Subtarget.is64Bit()) |
| 49 | return; |
| 50 | |
| 51 | const LLT p0 = LLT::pointer(0, 32); |
Igor Breger | 2953788 | 2017-04-07 14:41:59 +0000 | [diff] [blame] | 52 | const LLT s1 = LLT::scalar(1); |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 53 | const LLT s8 = LLT::scalar(8); |
| 54 | const LLT s16 = LLT::scalar(16); |
| 55 | const LLT s32 = LLT::scalar(32); |
Igor Breger | 2953788 | 2017-04-07 14:41:59 +0000 | [diff] [blame] | 56 | const LLT s64 = LLT::scalar(64); |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 57 | |
Igor Breger | 605b965 | 2017-05-08 09:03:37 +0000 | [diff] [blame^] | 58 | for (unsigned BinOp : {G_ADD, G_SUB, G_MUL}) |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 59 | for (auto Ty : {s8, s16, s32}) |
| 60 | setAction({BinOp, Ty}, Legal); |
| 61 | |
| 62 | for (unsigned MemOp : {G_LOAD, G_STORE}) { |
| 63 | for (auto Ty : {s8, s16, s32, p0}) |
| 64 | setAction({MemOp, Ty}, Legal); |
| 65 | |
| 66 | // And everything's fine in addrspace 0. |
| 67 | setAction({MemOp, 1, p0}, Legal); |
Igor Breger | f7359d8 | 2017-02-22 12:25:09 +0000 | [diff] [blame] | 68 | } |
Igor Breger | 531a203 | 2017-03-26 08:11:12 +0000 | [diff] [blame] | 69 | |
| 70 | // Pointer-handling |
| 71 | setAction({G_FRAME_INDEX, p0}, Legal); |
Igor Breger | 2953788 | 2017-04-07 14:41:59 +0000 | [diff] [blame] | 72 | |
| 73 | // Constants |
| 74 | for (auto Ty : {s8, s16, s32, p0}) |
| 75 | setAction({TargetOpcode::G_CONSTANT, Ty}, Legal); |
| 76 | |
| 77 | setAction({TargetOpcode::G_CONSTANT, s1}, WidenScalar); |
| 78 | setAction({TargetOpcode::G_CONSTANT, s64}, NarrowScalar); |
Igor Breger | c08a783 | 2017-05-01 06:30:16 +0000 | [diff] [blame] | 79 | |
| 80 | // Extensions |
| 81 | setAction({G_ZEXT, s32}, Legal); |
| 82 | setAction({G_SEXT, s32}, Legal); |
| 83 | |
| 84 | for (auto Ty : {s8, s16}) { |
| 85 | setAction({G_ZEXT, 1, Ty}, Legal); |
| 86 | setAction({G_SEXT, 1, Ty}, Legal); |
| 87 | } |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 88 | } |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 89 | |
Igor Breger | f7359d8 | 2017-02-22 12:25:09 +0000 | [diff] [blame] | 90 | void X86LegalizerInfo::setLegalizerInfo64bit() { |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 91 | |
| 92 | if (!Subtarget.is64Bit()) |
| 93 | return; |
| 94 | |
Igor Breger | 531a203 | 2017-03-26 08:11:12 +0000 | [diff] [blame] | 95 | const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8); |
Igor Breger | 2953788 | 2017-04-07 14:41:59 +0000 | [diff] [blame] | 96 | const LLT s1 = LLT::scalar(1); |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 97 | const LLT s8 = LLT::scalar(8); |
| 98 | const LLT s16 = LLT::scalar(16); |
| 99 | const LLT s32 = LLT::scalar(32); |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 100 | const LLT s64 = LLT::scalar(64); |
| 101 | |
Igor Breger | 605b965 | 2017-05-08 09:03:37 +0000 | [diff] [blame^] | 102 | for (unsigned BinOp : {G_ADD, G_SUB, G_MUL}) |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 103 | for (auto Ty : {s8, s16, s32, s64}) |
| 104 | setAction({BinOp, Ty}, Legal); |
| 105 | |
| 106 | for (unsigned MemOp : {G_LOAD, G_STORE}) { |
| 107 | for (auto Ty : {s8, s16, s32, s64, p0}) |
| 108 | setAction({MemOp, Ty}, Legal); |
| 109 | |
| 110 | // And everything's fine in addrspace 0. |
| 111 | setAction({MemOp, 1, p0}, Legal); |
| 112 | } |
Igor Breger | 531a203 | 2017-03-26 08:11:12 +0000 | [diff] [blame] | 113 | |
| 114 | // Pointer-handling |
| 115 | setAction({G_FRAME_INDEX, p0}, Legal); |
Igor Breger | 2953788 | 2017-04-07 14:41:59 +0000 | [diff] [blame] | 116 | |
| 117 | // Constants |
| 118 | for (auto Ty : {s8, s16, s32, s64, p0}) |
| 119 | setAction({TargetOpcode::G_CONSTANT, Ty}, Legal); |
| 120 | |
| 121 | setAction({TargetOpcode::G_CONSTANT, s1}, WidenScalar); |
Igor Breger | c08a783 | 2017-05-01 06:30:16 +0000 | [diff] [blame] | 122 | |
| 123 | // Extensions |
| 124 | for (auto Ty : {s32, s64}) { |
| 125 | setAction({G_ZEXT, Ty}, Legal); |
| 126 | setAction({G_SEXT, Ty}, Legal); |
| 127 | } |
| 128 | |
| 129 | for (auto Ty : {s8, s16, s32}) { |
| 130 | setAction({G_ZEXT, 1, Ty}, Legal); |
| 131 | setAction({G_SEXT, 1, Ty}, Legal); |
| 132 | } |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | void X86LegalizerInfo::setLegalizerInfoSSE1() { |
| 136 | if (!Subtarget.hasSSE1()) |
| 137 | return; |
| 138 | |
| 139 | const LLT s32 = LLT::scalar(32); |
| 140 | const LLT v4s32 = LLT::vector(4, 32); |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 141 | const LLT v2s64 = LLT::vector(2, 64); |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 142 | |
| 143 | for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV}) |
| 144 | for (auto Ty : {s32, v4s32}) |
| 145 | setAction({BinOp, Ty}, Legal); |
Igor Breger | a8ba572 | 2017-03-23 15:25:57 +0000 | [diff] [blame] | 146 | |
| 147 | for (unsigned MemOp : {G_LOAD, G_STORE}) |
| 148 | for (auto Ty : {v4s32, v2s64}) |
| 149 | setAction({MemOp, Ty}, Legal); |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | void X86LegalizerInfo::setLegalizerInfoSSE2() { |
| 153 | if (!Subtarget.hasSSE2()) |
| 154 | return; |
| 155 | |
| 156 | const LLT s64 = LLT::scalar(64); |
Igor Breger | 605b965 | 2017-05-08 09:03:37 +0000 | [diff] [blame^] | 157 | const LLT v8s16 = LLT::vector(8, 16); |
Igor Breger | 321cf3c | 2017-03-03 08:06:46 +0000 | [diff] [blame] | 158 | const LLT v4s32 = LLT::vector(4, 32); |
| 159 | const LLT v2s64 = LLT::vector(2, 64); |
| 160 | |
| 161 | for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV}) |
| 162 | for (auto Ty : {s64, v2s64}) |
| 163 | setAction({BinOp, Ty}, Legal); |
| 164 | |
| 165 | for (unsigned BinOp : {G_ADD, G_SUB}) |
| 166 | for (auto Ty : {v4s32}) |
| 167 | setAction({BinOp, Ty}, Legal); |
Igor Breger | 605b965 | 2017-05-08 09:03:37 +0000 | [diff] [blame^] | 168 | |
| 169 | setAction({G_MUL, v8s16}, Legal); |
| 170 | } |
| 171 | |
| 172 | void X86LegalizerInfo::setLegalizerInfoSSE41() { |
| 173 | if (!Subtarget.hasSSE41()) |
| 174 | return; |
| 175 | |
| 176 | const LLT v4s32 = LLT::vector(4, 32); |
| 177 | |
| 178 | setAction({G_MUL, v4s32}, Legal); |
| 179 | } |
| 180 | |
| 181 | void X86LegalizerInfo::setLegalizerInfoAVX2() { |
| 182 | if (!Subtarget.hasAVX2()) |
| 183 | return; |
| 184 | |
| 185 | const LLT v16s16 = LLT::vector(16, 16); |
| 186 | const LLT v8s32 = LLT::vector(8, 32); |
| 187 | |
| 188 | for (auto Ty : {v16s16, v8s32}) |
| 189 | setAction({G_MUL, Ty}, Legal); |
| 190 | } |
| 191 | |
| 192 | void X86LegalizerInfo::setLegalizerInfoAVX512() { |
| 193 | if (!Subtarget.hasAVX512()) |
| 194 | return; |
| 195 | |
| 196 | const LLT v16s32 = LLT::vector(16, 32); |
| 197 | |
| 198 | setAction({G_MUL, v16s32}, Legal); |
| 199 | |
| 200 | /************ VLX *******************/ |
| 201 | if (!Subtarget.hasVLX()) |
| 202 | return; |
| 203 | |
| 204 | const LLT v4s32 = LLT::vector(4, 32); |
| 205 | const LLT v8s32 = LLT::vector(8, 32); |
| 206 | |
| 207 | for (auto Ty : {v4s32, v8s32}) |
| 208 | setAction({G_MUL, Ty}, Legal); |
| 209 | } |
| 210 | |
| 211 | void X86LegalizerInfo::setLegalizerInfoAVX512DQ() { |
| 212 | if (!(Subtarget.hasAVX512() && Subtarget.hasDQI())) |
| 213 | return; |
| 214 | |
| 215 | const LLT v8s64 = LLT::vector(8, 64); |
| 216 | |
| 217 | setAction({G_MUL, v8s64}, Legal); |
| 218 | |
| 219 | /************ VLX *******************/ |
| 220 | if (!Subtarget.hasVLX()) |
| 221 | return; |
| 222 | |
| 223 | const LLT v2s64 = LLT::vector(2, 64); |
| 224 | const LLT v4s64 = LLT::vector(4, 64); |
| 225 | |
| 226 | for (auto Ty : {v2s64, v4s64}) |
| 227 | setAction({G_MUL, Ty}, Legal); |
| 228 | } |
| 229 | |
| 230 | void X86LegalizerInfo::setLegalizerInfoAVX512BW() { |
| 231 | if (!(Subtarget.hasAVX512() && Subtarget.hasBWI())) |
| 232 | return; |
| 233 | |
| 234 | const LLT v32s16 = LLT::vector(32, 16); |
| 235 | |
| 236 | setAction({G_MUL, v32s16}, Legal); |
| 237 | |
| 238 | /************ VLX *******************/ |
| 239 | if (!Subtarget.hasVLX()) |
| 240 | return; |
| 241 | |
| 242 | const LLT v8s16 = LLT::vector(8, 16); |
| 243 | const LLT v16s16 = LLT::vector(16, 16); |
| 244 | |
| 245 | for (auto Ty : {v8s16, v16s16}) |
| 246 | setAction({G_MUL, Ty}, Legal); |
Igor Breger | b4442f3 | 2017-02-10 07:05:56 +0000 | [diff] [blame] | 247 | } |