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gerrit-public.fairphone.software / toolchain / llvm-project / 6d1379e1800994bc877b33deaf19d13840cc844f / . / llvm / test / CodeGen / R600 / store.ll
blob: f2a8dd7d2658d6c17e4bf603e24feb6c22b98db6 [file] [log] [blame]
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
Tom Stellard6aa0d552013-06-14 22:12:24 +0000[diff] [blame]2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]3; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
4
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]5; floating-point store
6; EG-CHECK: @store_f32
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]7; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
Tom Stellard6aa0d552013-06-14 22:12:24 +0000[diff] [blame]8; CM-CHECK: @store_f32
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]9; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]10; SI-CHECK: @store_f32
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]11; SI-CHECK: BUFFER_STORE_DWORD
12
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]13define void @store_f32(float addrspace(1)* %out, float %in) {
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]14 store float %in, float addrspace(1)* %out
15 ret void
16}
Tom Stellard0125f2a2013-06-25 02:39:35 +0000[diff] [blame]17
Tom Stellarded2f6142013-07-18 21:43:42 +0000[diff] [blame]18; vec2 floating-point stores
19; EG-CHECK: @store_v2f32
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]20; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
Tom Stellarded2f6142013-07-18 21:43:42 +0000[diff] [blame]21; CM-CHECK: @store_v2f32
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]22; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
Tom Stellarded2f6142013-07-18 21:43:42 +0000[diff] [blame]23; SI-CHECK: @store_v2f32
24; SI-CHECK: BUFFER_STORE_DWORDX2
25
26define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
27entry:
28 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
Tom Stellard8e5da412013-08-14 23:24:32 +0000[diff] [blame]29 %1 = insertelement <2 x float> %0, float %b, i32 1
Tom Stellarded2f6142013-07-18 21:43:42 +0000[diff] [blame]30 store <2 x float> %1, <2 x float> addrspace(1)* %out
31 ret void
32}
33
Tom Stellard6d1379e2013-08-16 01:12:00 +0000[diff] [blame^]34; EG-CHECK: @store_v4i32
35; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
36; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
37; CM-CHECK: @store_v4i32
38; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
39; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
40; SI-CHECK: @store_v4i32
41; SI-CHECK: BUFFER_STORE_DWORDX4
42define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
43entry:
44 store <4 x i32> %in, <4 x i32> addrspace(1)* %out
45 ret void
46}
47
Tom Stellard0125f2a2013-06-25 02:39:35 +0000[diff] [blame]48; The stores in this function are combined by the optimizer to create a
49; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
50; should not try to split the 64-bit store back into 2 32-bit stores.
51;
52; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
53; be two 32-bit stores.
54
55; EG-CHECK: @vecload2
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]56; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
Tom Stellard0125f2a2013-06-25 02:39:35 +0000[diff] [blame]57; CM-CHECK: @vecload2
Tom Stellardac00f9d2013-08-16 01:11:46 +0000[diff] [blame]58; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
Tom Stellard0125f2a2013-06-25 02:39:35 +0000[diff] [blame]59; SI-CHECK: @vecload2
60; SI-CHECK: BUFFER_STORE_DWORDX2
61define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
62entry:
63 %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
64 %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
65 %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
66 store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
67 %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
68 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
69 ret void
70}
71
72attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
73
74!5 = metadata !{metadata !"int", metadata !6}
75!6 = metadata !{metadata !"omnipotent char", metadata !7}
76!7 = metadata !{metadata !"Simple C/C++ TBAA"}