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Eugene Zelenkod96089b2017-02-14 00:33:36 +00001//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
Tom Stellard347ac792015-06-26 21:15:07 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12
Yaxun Liu1a14bfa2017-03-27 14:04:01 +000013#include "AMDGPU.h"
Tom Stellard347ac792015-06-26 21:15:07 +000014#include "AMDKernelCodeT.h"
Matt Arsenault4bd72362016-12-10 00:39:12 +000015#include "SIDefines.h"
Eugene Zelenkod96089b2017-02-14 00:33:36 +000016#include "llvm/ADT/StringRef.h"
17#include "llvm/IR/CallingConv.h"
18#include "llvm/MC/MCInstrDesc.h"
Scott Linder1e8c2c72018-06-21 19:38:56 +000019#include "llvm/Support/AMDHSAKernelDescriptor.h"
Eugene Zelenkod96089b2017-02-14 00:33:36 +000020#include "llvm/Support/Compiler.h"
21#include "llvm/Support/ErrorHandling.h"
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000022#include "llvm/Support/TargetParser.h"
Eugene Zelenkod96089b2017-02-14 00:33:36 +000023#include <cstdint>
Konstantin Zhuravlyov9c05b2b2017-10-14 15:40:33 +000024#include <string>
Eugene Zelenkod96089b2017-02-14 00:33:36 +000025#include <utility>
Matt Arsenault4bd72362016-12-10 00:39:12 +000026
Tom Stellard347ac792015-06-26 21:15:07 +000027namespace llvm {
28
Matt Arsenault894e53d2017-07-26 20:39:42 +000029class Argument;
Tim Renouf4f703f52018-08-21 11:07:10 +000030class AMDGPUSubtarget;
Tom Stellard347ac792015-06-26 21:15:07 +000031class FeatureBitset;
Tom Stellardac00eb52015-12-15 16:26:16 +000032class Function;
Tim Renouf4f703f52018-08-21 11:07:10 +000033class GCNSubtarget;
Tom Stellarde3b5aea2015-12-02 17:00:42 +000034class GlobalValue;
Tom Stellarde135ffd2015-09-25 21:41:28 +000035class MCContext;
Krzysztof Parzyszekc8715502016-10-19 17:40:36 +000036class MCRegisterClass;
Sam Kolton1eeb11b2016-09-09 14:44:04 +000037class MCRegisterInfo;
Tom Stellarde135ffd2015-09-25 21:41:28 +000038class MCSection;
Tom Stellard2b65ed32015-12-21 18:44:27 +000039class MCSubtargetInfo;
Scott Linder1e8c2c72018-06-21 19:38:56 +000040class MachineMemOperand;
Eugene Zelenkod96089b2017-02-14 00:33:36 +000041class Triple;
Tom Stellard347ac792015-06-26 21:15:07 +000042
43namespace AMDGPU {
Nicolai Haehnle0ab200b2018-06-21 13:36:44 +000044
45#define GET_MIMGBaseOpcode_DECL
Nicolai Haehnle7a9c03f2018-06-21 13:36:57 +000046#define GET_MIMGDim_DECL
Nicolai Haehnle0ab200b2018-06-21 13:36:44 +000047#define GET_MIMGEncoding_DECL
Ryan Taylor894c8fd2018-08-01 12:12:01 +000048#define GET_MIMGLZMapping_DECL
Nicolai Haehnle0ab200b2018-06-21 13:36:44 +000049#include "AMDGPUGenSearchableTables.inc"
50
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000051namespace IsaInfo {
Sam Koltona3ec5c12016-10-07 14:46:06 +000052
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000053enum {
54 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
55 // doesn't spill SGPRs as much as when 80 is set.
Konstantin Zhuravlyovc72ece62018-05-16 20:47:48 +000056 FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
57 TRAP_NUM_SGPRS = 16
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000058};
59
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000060/// Streams isa version string for given subtarget \p STI into \p Stream.
Konstantin Zhuravlyov9c05b2b2017-10-14 15:40:33 +000061void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
62
Konstantin Zhuravlyov00f2cb12018-06-12 18:02:46 +000063/// \returns True if given subtarget \p STI supports code object version 3,
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +000064/// false otherwise.
Konstantin Zhuravlyov00f2cb12018-06-12 18:02:46 +000065bool hasCodeObjectV3(const MCSubtargetInfo *STI);
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +000066
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000067/// \returns Wavefront size for given subtarget \p STI.
68unsigned getWavefrontSize(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000069
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000070/// \returns Local memory size in bytes for given subtarget \p STI.
71unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000072
73/// \returns Number of execution units per compute unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000074/// STI.
75unsigned getEUsPerCU(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000076
77/// \returns Maximum number of work groups per compute unit for given subtarget
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000078/// \p STI and limited by given \p FlatWorkGroupSize.
79unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000080 unsigned FlatWorkGroupSize);
81
82/// \returns Maximum number of waves per compute unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000083/// STI without any kind of limitation.
84unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000085
86/// \returns Maximum number of waves per compute unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000087/// STI and limited by given \p FlatWorkGroupSize.
88unsigned getMaxWavesPerCU(const MCSubtargetInfo *STI,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000089 unsigned FlatWorkGroupSize);
90
91/// \returns Minimum number of waves per execution unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000092/// STI.
93unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000094
95/// \returns Maximum number of waves per execution unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000096/// STI without any kind of limitation.
Tom Stellardc5a154d2018-06-28 23:47:12 +000097unsigned getMaxWavesPerEU();
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +000098
99/// \returns Maximum number of waves per execution unit for given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000100/// STI and limited by given \p FlatWorkGroupSize.
101unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000102 unsigned FlatWorkGroupSize);
103
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000104/// \returns Minimum flat work group size for given subtarget \p STI.
105unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000106
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000107/// \returns Maximum flat work group size for given subtarget \p STI.
108unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000109
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000110/// \returns Number of waves per work group for given subtarget \p STI and
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000111/// limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000112unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000113 unsigned FlatWorkGroupSize);
114
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000115/// \returns SGPR allocation granularity for given subtarget \p STI.
116unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000117
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000118/// \returns SGPR encoding granularity for given subtarget \p STI.
119unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000120
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000121/// \returns Total number of SGPRs for given subtarget \p STI.
122unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000123
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000124/// \returns Addressable number of SGPRs for given subtarget \p STI.
125unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000126
127/// \returns Minimum number of SGPRs that meets the given number of waves per
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000128/// execution unit requirement for given subtarget \p STI.
129unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000130
131/// \returns Maximum number of SGPRs that meets the given number of waves per
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000132/// execution unit requirement for given subtarget \p STI.
133unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000134 bool Addressable);
135
Scott Linder1e8c2c72018-06-21 19:38:56 +0000136/// \returns Number of extra SGPRs implicitly required by given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000137/// STI when the given special registers are used.
138unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
Scott Linder1e8c2c72018-06-21 19:38:56 +0000139 bool FlatScrUsed, bool XNACKUsed);
140
141/// \returns Number of extra SGPRs implicitly required by given subtarget \p
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000142/// STI when the given special registers are used. XNACK is inferred from
143/// \p STI.
144unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
Scott Linder1e8c2c72018-06-21 19:38:56 +0000145 bool FlatScrUsed);
146
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000147/// \returns Number of SGPR blocks needed for given subtarget \p STI when
Scott Linder1e8c2c72018-06-21 19:38:56 +0000148/// \p NumSGPRs are used. \p NumSGPRs should already include any special
149/// register counts.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000150unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
Scott Linder1e8c2c72018-06-21 19:38:56 +0000151
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000152/// \returns VGPR allocation granularity for given subtarget \p STI.
153unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000154
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000155/// \returns VGPR encoding granularity for given subtarget \p STI.
156unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000157
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000158/// \returns Total number of VGPRs for given subtarget \p STI.
159unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000160
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000161/// \returns Addressable number of VGPRs for given subtarget \p STI.
162unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000163
164/// \returns Minimum number of VGPRs that meets given number of waves per
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000165/// execution unit requirement for given subtarget \p STI.
166unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000167
168/// \returns Maximum number of VGPRs that meets given number of waves per
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000169/// execution unit requirement for given subtarget \p STI.
170unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000171
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000172/// \returns Number of VGPR blocks needed for given subtarget \p STI when
Scott Linder1e8c2c72018-06-21 19:38:56 +0000173/// \p NumVGPRs are used.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000174unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
Scott Linder1e8c2c72018-06-21 19:38:56 +0000175
Eugene Zelenkod96089b2017-02-14 00:33:36 +0000176} // end namespace IsaInfo
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000177
178LLVM_READONLY
179int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
180
Nicolai Haehnle7a9c03f2018-06-21 13:36:57 +0000181struct MIMGBaseOpcodeInfo {
182 MIMGBaseOpcode BaseOpcode;
183 bool Store;
184 bool Atomic;
185 bool AtomicX2;
186 bool Sampler;
187
188 uint8_t NumExtraArgs;
189 bool Gradients;
190 bool Coordinates;
191 bool LodOrClampOrMip;
192 bool HasD16;
193};
194
195LLVM_READONLY
196const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
197
198struct MIMGDimInfo {
199 MIMGDim Dim;
200 uint8_t NumCoords;
201 uint8_t NumGradients;
202 bool DA;
203};
204
205LLVM_READONLY
206const MIMGDimInfo *getMIMGDimInfo(unsigned Dim);
207
Ryan Taylor894c8fd2018-08-01 12:12:01 +0000208struct MIMGLZMappingInfo {
209 MIMGBaseOpcode L;
210 MIMGBaseOpcode LZ;
211};
212
213LLVM_READONLY
214const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
215
Nicolai Haehnle7a9c03f2018-06-21 13:36:57 +0000216LLVM_READONLY
217int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
218 unsigned VDataDwords, unsigned VAddrDwords);
219
Matt Arsenaultcad7fa82017-12-13 21:07:51 +0000220LLVM_READONLY
Nicolai Haehnle0ab200b2018-06-21 13:36:44 +0000221int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
Nicolai Haehnlef2674312018-06-21 13:36:01 +0000222
223LLVM_READONLY
Neil Henning76504a42018-12-12 16:15:21 +0000224int getMUBUFBaseOpcode(unsigned Opc);
225
226LLVM_READONLY
227int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords);
228
229LLVM_READONLY
230int getMUBUFDwords(unsigned Opc);
231
232LLVM_READONLY
233bool getMUBUFHasVAddr(unsigned Opc);
234
235LLVM_READONLY
236bool getMUBUFHasSrsrc(unsigned Opc);
237
238LLVM_READONLY
239bool getMUBUFHasSoffset(unsigned Opc);
240
241LLVM_READONLY
Matt Arsenaultcad7fa82017-12-13 21:07:51 +0000242int getMCOpcode(uint16_t Opcode, unsigned Gen);
243
Tom Stellardff7416b2015-06-26 21:58:31 +0000244void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000245 const MCSubtargetInfo *STI);
Tom Stellard9760f032015-12-03 03:34:32 +0000246
Scott Linder1e8c2c72018-06-21 19:38:56 +0000247amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor();
248
Konstantin Zhuravlyov435151a2017-11-01 19:12:38 +0000249bool isGroupSegment(const GlobalValue *GV);
250bool isGlobalSegment(const GlobalValue *GV);
251bool isReadOnlySegment(const GlobalValue *GV);
Tom Stellarde3b5aea2015-12-02 17:00:42 +0000252
Konstantin Zhuravlyov08326b62016-10-20 18:12:38 +0000253/// \returns True if constants should be emitted to .text section for given
254/// target triple \p TT, false otherwise.
255bool shouldEmitConstantsToTextSection(const Triple &TT);
256
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000257/// \returns Integer value requested using \p F's \p Name attribute.
258///
259/// \returns \p Default if attribute is not present.
260///
261/// \returns \p Default and emits error if requested value cannot be converted
262/// to integer.
Matt Arsenault83002722016-05-12 02:45:18 +0000263int getIntegerAttribute(const Function &F, StringRef Name, int Default);
264
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000265/// \returns A pair of integer values requested using \p F's \p Name attribute
266/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
267/// is false).
268///
269/// \returns \p Default if attribute is not present.
270///
271/// \returns \p Default and emits error if one of the requested values cannot be
272/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
273/// not present.
274std::pair<int, int> getIntegerPairAttribute(const Function &F,
275 StringRef Name,
276 std::pair<int, int> Default,
277 bool OnlyFirstRequired = false);
278
Nicolai Haehnle1a94cbb2018-11-29 11:06:06 +0000279/// Represents the counter values to wait for in an s_waitcnt instruction.
280///
281/// Large values (including the maximum possible integer) can be used to
282/// represent "don't care" waits.
283struct Waitcnt {
284 unsigned VmCnt = ~0u;
285 unsigned ExpCnt = ~0u;
286 unsigned LgkmCnt = ~0u;
287
288 Waitcnt() {}
289 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt)
290 : VmCnt(VmCnt), ExpCnt(ExpCnt), LgkmCnt(LgkmCnt) {}
291
292 static Waitcnt allZero() { return Waitcnt(0, 0, 0); }
293
294 bool dominates(const Waitcnt &Other) const {
295 return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
296 LgkmCnt <= Other.LgkmCnt;
297 }
298
299 Waitcnt combined(const Waitcnt &Other) const {
300 return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
301 std::min(LgkmCnt, Other.LgkmCnt));
302 }
303};
304
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000305/// \returns Vmcnt bit mask for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000306unsigned getVmcntBitMask(const IsaVersion &Version);
Konstantin Zhuravlyov836cbff2016-09-30 17:01:40 +0000307
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000308/// \returns Expcnt bit mask for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000309unsigned getExpcntBitMask(const IsaVersion &Version);
Konstantin Zhuravlyov836cbff2016-09-30 17:01:40 +0000310
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000311/// \returns Lgkmcnt bit mask for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000312unsigned getLgkmcntBitMask(const IsaVersion &Version);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000313
314/// \returns Waitcnt bit mask for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000315unsigned getWaitcntBitMask(const IsaVersion &Version);
Konstantin Zhuravlyov836cbff2016-09-30 17:01:40 +0000316
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000317/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000318unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
Konstantin Zhuravlyov836cbff2016-09-30 17:01:40 +0000319
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000320/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000321unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000322
323/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000324unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000325
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000326/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000327/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
328/// \p Lgkmcnt respectively.
329///
330/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
Matt Arsenaulte823d922017-02-18 18:29:53 +0000331/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
332/// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000333/// \p Expcnt = \p Waitcnt[6:4]
334/// \p Lgkmcnt = \p Waitcnt[11:8]
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000335void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000336 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
337
Nicolai Haehnle1a94cbb2018-11-29 11:06:06 +0000338Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
339
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000340/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000341unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000342 unsigned Vmcnt);
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000343
344/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000345unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000346 unsigned Expcnt);
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000347
348/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000349unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000350 unsigned Lgkmcnt);
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000351
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000352/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000353/// \p Version.
354///
355/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
Matt Arsenaulte823d922017-02-18 18:29:53 +0000356/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
357/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
358/// Waitcnt[6:4] = \p Expcnt
359/// Waitcnt[11:8] = \p Lgkmcnt
360/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000361///
362/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
363/// isa \p Version.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000364unsigned encodeWaitcnt(const IsaVersion &Version,
Konstantin Zhuravlyovcdd45472016-10-11 18:58:22 +0000365 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
Konstantin Zhuravlyov836cbff2016-09-30 17:01:40 +0000366
Nicolai Haehnle1a94cbb2018-11-29 11:06:06 +0000367unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
368
Marek Olsakfccabaf2016-01-13 11:45:36 +0000369unsigned getInitialPSInputAddr(const Function &F);
370
Matt Arsenaulte622dc32017-04-11 22:29:24 +0000371LLVM_READNONE
372bool isShader(CallingConv::ID CC);
373
374LLVM_READNONE
375bool isCompute(CallingConv::ID CC);
376
377LLVM_READNONE
378bool isEntryFunctionCC(CallingConv::ID CC);
379
Matt Arsenaultefa9f4b2017-04-11 22:29:28 +0000380// FIXME: Remove this when calling conventions cleaned up
381LLVM_READNONE
382inline bool isKernel(CallingConv::ID CC) {
383 switch (CC) {
Matt Arsenaultefa9f4b2017-04-11 22:29:28 +0000384 case CallingConv::AMDGPU_KERNEL:
385 case CallingConv::SPIR_KERNEL:
386 return true;
387 default:
388 return false;
389 }
390}
Tom Stellardac00eb52015-12-15 16:26:16 +0000391
Dmitry Preobrazhensky3afbd822018-01-10 14:22:19 +0000392bool hasXNACK(const MCSubtargetInfo &STI);
Konstantin Zhuravlyov108927b2018-11-05 22:44:19 +0000393bool hasSRAMECC(const MCSubtargetInfo &STI);
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000394bool hasMIMG_R128(const MCSubtargetInfo &STI);
Dmitry Preobrazhensky0a1ff462018-02-05 14:18:53 +0000395bool hasPackedD16(const MCSubtargetInfo &STI);
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000396
Tom Stellard2b65ed32015-12-21 18:44:27 +0000397bool isSI(const MCSubtargetInfo &STI);
398bool isCI(const MCSubtargetInfo &STI);
399bool isVI(const MCSubtargetInfo &STI);
Sam Koltonf7659d712017-05-23 10:08:55 +0000400bool isGFX9(const MCSubtargetInfo &STI);
401
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000402/// Is Reg - scalar register
Sam Koltonf7659d712017-05-23 10:08:55 +0000403bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
Tom Stellard2b65ed32015-12-21 18:44:27 +0000404
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000405/// Is there any intersection between registers
Dmitry Preobrazhenskydc4ac822017-06-21 14:41:34 +0000406bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
407
Tom Stellard2b65ed32015-12-21 18:44:27 +0000408/// If \p Reg is a pseudo reg, return the correct hardware register given
409/// \p STI otherwise return \p Reg.
410unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
411
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000412/// Convert hardware register \p Reg to a pseudo register
Dmitry Preobrazhensky03880f82017-03-03 14:31:06 +0000413LLVM_READNONE
414unsigned mc2PseudoReg(unsigned Reg);
415
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000416/// Can this operand also contain immediate values?
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000417bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
418
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000419/// Is this floating-point operand?
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000420bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
421
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000422/// Does this opearnd support only inlinable literals?
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000423bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
424
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000425/// Get the size in bits of a register from the register class \p RC.
Tom Stellardb133fbb2016-10-27 23:05:31 +0000426unsigned getRegBitWidth(unsigned RCID);
427
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000428/// Get the size in bits of a register from the register class \p RC.
Krzysztof Parzyszekc8715502016-10-19 17:40:36 +0000429unsigned getRegBitWidth(const MCRegisterClass &RC);
430
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000431/// Get size of register operand
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000432unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
433 unsigned OpNo);
434
Matt Arsenault4bd72362016-12-10 00:39:12 +0000435LLVM_READNONE
436inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
437 switch (OpInfo.OperandType) {
438 case AMDGPU::OPERAND_REG_IMM_INT32:
439 case AMDGPU::OPERAND_REG_IMM_FP32:
440 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
441 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
442 return 4;
443
444 case AMDGPU::OPERAND_REG_IMM_INT64:
445 case AMDGPU::OPERAND_REG_IMM_FP64:
446 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
447 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
448 return 8;
449
450 case AMDGPU::OPERAND_REG_IMM_INT16:
451 case AMDGPU::OPERAND_REG_IMM_FP16:
452 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
453 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000454 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
455 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
Matt Arsenault4bd72362016-12-10 00:39:12 +0000456 return 2;
457
458 default:
459 llvm_unreachable("unhandled operand type");
460 }
461}
462
463LLVM_READNONE
464inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
465 return getOperandSize(Desc.OpInfo[OpNo]);
466}
467
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000468/// Is this literal inlinable
Matt Arsenault26faed32016-12-05 22:26:17 +0000469LLVM_READNONE
470bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
471
472LLVM_READNONE
473bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
474
Matt Arsenault4bd72362016-12-10 00:39:12 +0000475LLVM_READNONE
476bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000477
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000478LLVM_READNONE
479bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
480
Matt Arsenault894e53d2017-07-26 20:39:42 +0000481bool isArgPassedInSGPR(const Argument *Arg);
Tom Stellard08efb7e2017-01-27 18:41:14 +0000482
483/// \returns The encoding that will be used for \p ByteOffset in the SMRD
484/// offset field.
485int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
486
487/// \returns true if this offset is small enough to fit in the SMRD
488/// offset field. \p ByteOffset should be the offset in bytes and
489/// not the encoded offset.
490bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
491
Tim Renouf4f703f52018-08-21 11:07:10 +0000492bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
Nicolai Haehnlea7b00052018-11-30 22:55:38 +0000493 const GCNSubtarget *Subtarget, uint32_t Align = 4);
Tim Renouf4f703f52018-08-21 11:07:10 +0000494
Alexander Timofeev2e5eece2018-03-05 15:12:21 +0000495/// \returns true if the intrinsic is divergent
496bool isIntrinsicSourceOfDivergence(unsigned IntrID);
497
Tom Stellard347ac792015-06-26 21:15:07 +0000498} // end namespace AMDGPU
499} // end namespace llvm
500
Eugene Zelenkod96089b2017-02-14 00:33:36 +0000501#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H