blob: 0e3789e4c02727bb72a4d82006d28564e4aea590 [file] [log] [blame]
Tom Stellard919bb6b2014-04-29 23:12:53 +00001; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
Matt Arsenaultfb826fa2013-11-18 20:09:47 +00002
3
Tom Stellard1f15bff2014-02-25 21:36:18 +00004declare i32 @llvm.r600.read.tidig.x() readnone
Matt Arsenaultfb826fa2013-11-18 20:09:47 +00005
Tom Stellard79243d92014-10-01 17:15:17 +00006; SI-LABEL: {{^}}test_i64_vreg:
Tom Stellard1f15bff2014-02-25 21:36:18 +00007; SI: V_ADD_I32
8; SI: V_ADDC_U32
Matt Arsenaultfb826fa2013-11-18 20:09:47 +00009define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
Tom Stellard1f15bff2014-02-25 21:36:18 +000010 %tid = call i32 @llvm.r600.read.tidig.x() readnone
Matt Arsenaultfb826fa2013-11-18 20:09:47 +000011 %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid
12 %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid
13 %a = load i64 addrspace(1)* %a_ptr
14 %b = load i64 addrspace(1)* %b_ptr
15 %result = add i64 %a, %b
16 store i64 %result, i64 addrspace(1)* %out
17 ret void
18}
19
Matt Arsenault3a4d86a2013-11-18 20:09:55 +000020; Check that the SGPR add operand is correctly moved to a VGPR.
Tom Stellard79243d92014-10-01 17:15:17 +000021; SI-LABEL: {{^}}sgpr_operand:
Tom Stellard1f15bff2014-02-25 21:36:18 +000022; SI: V_ADD_I32
23; SI: V_ADDC_U32
Matt Arsenault3a4d86a2013-11-18 20:09:55 +000024define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
Matt Arsenault08f7e372013-11-18 20:09:50 +000025 %foo = load i64 addrspace(1)* %in, align 8
26 %result = add i64 %foo, %a
Matt Arsenaultfb826fa2013-11-18 20:09:47 +000027 store i64 %result, i64 addrspace(1)* %out
28 ret void
29}
30
Matt Arsenault08f7e372013-11-18 20:09:50 +000031; Swap the arguments. Check that the SGPR -> VGPR copy works with the
32; SGPR as other operand.
33;
Tom Stellard79243d92014-10-01 17:15:17 +000034; SI-LABEL: {{^}}sgpr_operand_reversed:
Tom Stellard1f15bff2014-02-25 21:36:18 +000035; SI: V_ADD_I32
36; SI: V_ADDC_U32
Matt Arsenault3a4d86a2013-11-18 20:09:55 +000037define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
38 %foo = load i64 addrspace(1)* %in, align 8
39 %result = add i64 %a, %foo
40 store i64 %result, i64 addrspace(1)* %out
41 ret void
42}
Matt Arsenault08f7e372013-11-18 20:09:50 +000043
44
Tom Stellard79243d92014-10-01 17:15:17 +000045; SI-LABEL: {{^}}test_v2i64_sreg:
Tom Stellard80942a12014-09-05 14:07:59 +000046; SI: S_ADD_U32
Tom Stellard1f15bff2014-02-25 21:36:18 +000047; SI: S_ADDC_U32
Tom Stellard80942a12014-09-05 14:07:59 +000048; SI: S_ADD_U32
Tom Stellard1f15bff2014-02-25 21:36:18 +000049; SI: S_ADDC_U32
Matt Arsenaultfb826fa2013-11-18 20:09:47 +000050define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
51 %result = add <2 x i64> %a, %b
52 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
53 ret void
54}
55
Tom Stellard79243d92014-10-01 17:15:17 +000056; SI-LABEL: {{^}}test_v2i64_vreg:
Tom Stellard1f15bff2014-02-25 21:36:18 +000057; SI: V_ADD_I32
58; SI: V_ADDC_U32
59; SI: V_ADD_I32
60; SI: V_ADDC_U32
Matt Arsenaultfb826fa2013-11-18 20:09:47 +000061define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
Tom Stellard1f15bff2014-02-25 21:36:18 +000062 %tid = call i32 @llvm.r600.read.tidig.x() readnone
Matt Arsenaultfb826fa2013-11-18 20:09:47 +000063 %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid
64 %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid
65 %a = load <2 x i64> addrspace(1)* %a_ptr
66 %b = load <2 x i64> addrspace(1)* %b_ptr
67 %result = add <2 x i64> %a, %b
68 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
69 ret void
70}
Matt Arsenaultb517c812014-03-27 17:23:31 +000071
Tom Stellard79243d92014-10-01 17:15:17 +000072; SI-LABEL: {{^}}trunc_i64_add_to_i32:
Chandler Carruth9f4530b2014-07-24 22:15:28 +000073; SI: S_LOAD_DWORD s[[SREG0:[0-9]+]]
74; SI: S_LOAD_DWORD s[[SREG1:[0-9]+]]
Tom Stellard10ae6a02014-07-02 20:53:54 +000075; SI: S_ADD_I32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
Matt Arsenaultb517c812014-03-27 17:23:31 +000076; SI-NOT: ADDC
77; SI: V_MOV_B32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
78; SI: BUFFER_STORE_DWORD [[VRESULT]],
79define void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
80 %add = add i64 %b, %a
81 %trunc = trunc i64 %add to i32
82 store i32 %trunc, i32 addrspace(1)* %out, align 8
83 ret void
84}