Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 7a64346533444da236f2ab6330935143ad8b8dcf / . / llvm / lib / Target / ARM / ARMISelLowering.h
blob: af8b3fb006e6f74f4977f506d2e9338fb973f5eb [file] [log] [blame]
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]15#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]17
Craig Toppera9253262014-03-22 23:51:00 +0000[diff] [blame]18#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]19#include "llvm/CodeGen/CallingConvLower.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]20#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]21#include "llvm/Target/TargetLowering.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]22#include <vector>
23
24namespace llvm {
25 class ARMConstantPoolValue;
Craig Toppera9253262014-03-22 23:51:00 +0000[diff] [blame]26 class ARMSubtarget;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]27
28 namespace ARMISD {
29 // ARM Specific DAG Nodes
Matthias Braund04893f2015-05-07 21:33:59 +0000[diff] [blame]30 enum NodeType : unsigned {
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]31 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +0000[diff] [blame]32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]33
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chengdfce83c2011-01-17 08:03:18 +0000[diff] [blame]36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
37 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]39
Manman Ren9f911162012-06-01 02:44:42 +0000[diff] [blame]40 // Add pseudo op to model memcpy for struct byval.
41 COPY_STRUCT_BYVAL,
42
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]43 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +0000[diff] [blame]44 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]45 CALL_NOLINK, // Function call with branch not branch-and-link.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]46 BRCOND, // Conditional branch.
47 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +0000[diff] [blame]48 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]49 RET_FLAG, // Return with a flag operand.
Tim Northoverd8407452013-10-01 14:33:28 +0000[diff] [blame]50 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]51
52 PIC_ADD, // Add with a PC operand and a PIC label.
53
54 CMP, // ARM compare instructions.
Bill Wendling4b796472012-06-11 08:07:26 +0000[diff] [blame]55 CMN, // ARM CMN instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +0000[diff] [blame]56 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]57 CMPFP, // ARM VFP compare instruction, sets FPSCR.
58 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
59 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]60
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]61 CMOV, // ARM conditional move instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]62
Pablo Barrio7a643462016-06-23 16:53:49 +0000[diff] [blame^]63 SSAT, // Signed saturation
64
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]65 BCC_i64,
66
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]70
Evan Chenge8916542011-08-30 01:34:54 +0000[diff] [blame]71 ADDC, // Add with carry
72 ADDE, // Add using carry
73 SUBC, // Sub with carry
74 SUBE, // Sub using carry
75
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000[diff] [blame]76 VMOVRRD, // double to two gprs.
77 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000[diff] [blame]78
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000[diff] [blame]79 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
80 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]81 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000[diff] [blame]82
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]83 TC_RETURN, // Tail call return pseudo.
84
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]85 THREAD_POINTER,
86
Evan Chengb972e562009-08-07 00:34:42 +0000[diff] [blame]87 DYN_ALLOC, // Dynamic allocation on the stack.
88
Bob Wilson7ed59712010-10-30 00:54:37 +0000[diff] [blame]89 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]90
91 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]92
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]93 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]94 WIN__DBZCHK, // Windows' divide by zero check
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]95
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]96 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]97 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]98 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
107
108 // Vector shift by immediate:
109 VSHL, // ...left
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]112
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
117
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
125
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
130
131 // Vector shift and insert:
132 VSLI, // ...left
133 VSRI, // ...right
134
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
139
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]140 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000[diff] [blame]141 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]142 VMVNIMM,
143
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000[diff] [blame]144 // Vector move f32 immediate:
145 VMOVFPIMM,
146
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]147 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000[diff] [blame]148 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000[diff] [blame]149 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000[diff] [blame]150
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]151 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000[diff] [blame]152 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000[diff] [blame]155 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000[diff] [blame]156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]158 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000[diff] [blame]159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]161
Bob Wilson38ab35a2010-09-01 23:50:19 +0000[diff] [blame]162 // Vector multiply long:
163 VMULLs, // ...signed
164 VMULLu, // ...unsigned
165
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
Sam Parkerd616cf02016-06-20 16:47:09 +0000[diff] [blame]168 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]169
Bob Wilsond8a9a042010-06-04 00:04:02 +0000[diff] [blame]170 // Operands of the standard BUILD_VECTOR node are not legalized, which
171 // is fine if BUILD_VECTORs are always lowered to shuffles or other
172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
173 // operands need to be legalized. Define an ARM-specific version of
174 // BUILD_VECTOR for this purpose.
175 BUILD_VECTOR,
176
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]177 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]178 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]179
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]180 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000[diff] [blame]181 VORRIMM,
182 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]183 VBICIMM,
184
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000[diff] [blame]185 // Vector bitwise select
186 VBSL,
187
Scott Douglass953f9082015-10-05 14:49:54 +0000[diff] [blame]188 // Pseudo-instruction representing a memory copy using ldm/stm
189 // instructions.
190 MEMCPY,
191
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]192 // Vector load N-element structure to all lanes:
193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
194 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]195 VLD4DUP,
196
197 // NEON loads with post-increment base updates:
198 VLD1_UPD,
199 VLD2_UPD,
200 VLD3_UPD,
201 VLD4_UPD,
202 VLD2LN_UPD,
203 VLD3LN_UPD,
204 VLD4LN_UPD,
205 VLD2DUP_UPD,
206 VLD3DUP_UPD,
207 VLD4DUP_UPD,
208
209 // NEON stores with post-increment base updates:
210 VST1_UPD,
211 VST2_UPD,
212 VST3_UPD,
213 VST4_UPD,
214 VST2LN_UPD,
215 VST3LN_UPD,
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000[diff] [blame]216 VST4LN_UPD
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]217 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]218 }
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]219
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]220 /// Define some predicates that are used for node matching.
221 namespace ARM {
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]222 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]223 }
224
Bob Wilsondd0e2362009-05-20 16:30:25 +0000[diff] [blame]225 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000[diff] [blame]226 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]227
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]228 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]229 public:
Eric Christopher1889fdc2015-01-29 00:19:39 +0000[diff] [blame]230 explicit ARMTargetLowering(const TargetMachine &TM,
231 const ARMSubtarget &STI);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]232
Rafael Espindola0f898332016-06-20 16:43:17 +0000[diff] [blame]233 bool isPositionIndependent() const;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]234 unsigned getJumpTableEncoding() const override;
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]235 bool useSoftFloat() const override;
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000[diff] [blame]236
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]238
239 /// ReplaceNodeResults - Replace the results of node with an illegal result
240 /// type with new values built out of custom code.
241 ///
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
243 SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]244
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]245 const char *getTargetNodeName(unsigned Opcode) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]246
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]247 bool isSelectSupported(SelectSupportKind Kind) const override {
Nadav Rotem9d832022012-09-02 12:10:19 +0000[diff] [blame]248 // ARM does not support scalar condition selects on vectors.
249 return (Kind != ScalarCondVectorVal);
250 }
251
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]252 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]253 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
254 EVT VT) const override;
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]255
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]256 MachineBasicBlock *
Dan Gohman25c16532010-05-01 00:01:06 +0000[diff] [blame]257 EmitInstrWithCustomInserter(MachineInstr *MI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]258 MachineBasicBlock *MBB) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]259
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]260 void AdjustInstrPostInstrSelection(MachineInstr *MI,
261 SDNode *Node) const override;
Evan Chenge6fba772011-08-30 19:09:48 +0000[diff] [blame]262
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]263 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Peter Collingbourne86b9fbe2016-03-21 18:00:02 +0000[diff] [blame]264 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
James Molloy9d55f192015-11-10 14:22:05 +0000[diff] [blame]265 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]266 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]267
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]268 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]269
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]270 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
Evan Cheng79e2ca92012-12-10 23:21:26 +0000[diff] [blame]271 /// unaligned memory accesses of the specified type. Returns whether it
272 /// is "fast" by reference in the second argument.
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]273 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
274 unsigned Align,
275 bool *Fast) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]276
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]277 EVT getOptimalMemOpType(uint64_t Size,
278 unsigned DstAlign, unsigned SrcAlign,
279 bool IsMemset, bool ZeroMemset,
280 bool MemcpyStrSrc,
281 MachineFunction &MF) const override;
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]282
Matt Beaumont-Gay4a04c922012-12-06 23:15:36 +0000[diff] [blame]283 using TargetLowering::isZExtFree;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]284 bool isZExtFree(SDValue Val, EVT VT2) const override;
Evan Cheng9ec512d2012-12-06 19:13:27 +0000[diff] [blame]285
Ahmed Bougacha4200cc92015-03-05 19:37:53 +0000[diff] [blame]286 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
287
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]288 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
Tim Northovercc2e9032013-08-06 13:58:03 +0000[diff] [blame]289
290
Chris Lattner1eb94d92007-03-30 23:15:24 +0000[diff] [blame]291 /// isLegalAddressingMode - Return true if the addressing mode represented
292 /// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]293 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
294 Type *Ty, unsigned AS) const override;
Evan Chengdc49a8d2009-08-14 20:09:37 +0000[diff] [blame]295 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]296
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]297 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]298 /// icmp immediate, that is the target has icmp instructions which can
299 /// compare a register against the immediate without having to materialize
300 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]301 bool isLegalICmpImmediate(int64_t Imm) const override;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]302
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]303 /// isLegalAddImmediate - Return true if the specified immediate is legal
304 /// add immediate, that is the target has add instructions which can
305 /// add a register and the immediate without having to materialize
306 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]307 bool isLegalAddImmediate(int64_t Imm) const override;
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]308
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]309 /// getPreIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if the node's address
311 /// can be legally represented as pre-indexed load / store address.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]312 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
313 ISD::MemIndexedMode &AM,
314 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]315
316 /// getPostIndexedAddressParts - returns true by value, base pointer and
317 /// offset pointer and addressing mode by reference if this node can be
318 /// combined with a load / store to form a post-indexed load / store.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]319 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
320 SDValue &Offset, ISD::MemIndexedMode &AM,
321 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]322
Jay Foada0653a32014-05-14 21:14:37 +0000[diff] [blame]323 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
324 APInt &KnownOne,
325 const SelectionDAG &DAG,
326 unsigned Depth) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]327
328
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]329 bool ExpandInlineAsm(CallInst *CI) const override;
Evan Cheng078b0b02011-01-08 01:24:27 +0000[diff] [blame]330
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]331 ConstraintType getConstraintType(StringRef Constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]332
333 /// Examine constraint string and operand type and determine a weight value.
334 /// The operand object must already have been set up with the operand type.
335 ConstraintWeight getSingleConstraintMatchWeight(
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]336 AsmOperandInfo &info, const char *constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]337
Eric Christopher11e4df72015-02-26 22:38:43 +0000[diff] [blame]338 std::pair<unsigned, const TargetRegisterClass *>
339 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]340 StringRef Constraint, MVT VT) const override;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]341
Silviu Baranga82d04262016-04-25 14:29:18 +0000[diff] [blame]342 const char *LowerXConstraint(EVT ConstraintVT) const override;
343
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]344 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
345 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
346 /// true it means one of the asm constraint of the inline asm instruction
347 /// being processed is 'm'.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]348 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
349 std::vector<SDValue> &Ops,
350 SelectionDAG &DAG) const override;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]351
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]352 unsigned
353 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000[diff] [blame]354 if (ConstraintCode == "Q")
355 return InlineAsm::Constraint_Q;
James Molloy72222f52015-10-26 10:04:52 +0000[diff] [blame]356 else if (ConstraintCode == "o")
357 return InlineAsm::Constraint_o;
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000[diff] [blame]358 else if (ConstraintCode.size() == 2) {
359 if (ConstraintCode[0] == 'U') {
360 switch(ConstraintCode[1]) {
361 default:
362 break;
363 case 'm':
364 return InlineAsm::Constraint_Um;
365 case 'n':
366 return InlineAsm::Constraint_Un;
367 case 'q':
368 return InlineAsm::Constraint_Uq;
369 case 's':
370 return InlineAsm::Constraint_Us;
371 case 't':
372 return InlineAsm::Constraint_Ut;
373 case 'v':
374 return InlineAsm::Constraint_Uv;
375 case 'y':
376 return InlineAsm::Constraint_Uy;
377 }
378 }
379 }
380 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
Daniel Sandersbf5b80f2015-03-16 13:13:41 +0000[diff] [blame]381 }
382
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000[diff] [blame]383 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000[diff] [blame]384 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]385 }
386
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]387 /// getRegClassFor - Return the register class that should be used for the
388 /// specified value type.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]389 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]390
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]391 /// Returns true if a cast between SrcAS and DestAS is a noop.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]392 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]393 // Addrspacecasts are always noops.
394 return true;
395 }
396
John Brawn0dbcd652015-03-18 12:01:59 +0000[diff] [blame]397 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
398 unsigned &PrefAlign) const override;
399
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]400 /// createFastISel - This method returns a target specific FastISel object,
401 /// or null if the target does not support "fast" ISel.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]402 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
403 const TargetLibraryInfo *libInfo) const override;
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]404
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]405 Sched::Preference getSchedulingPreference(SDNode *N) const override;
Evan Cheng4401f882010-05-20 23:26:43 +0000[diff] [blame]406
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]407 bool
408 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
409 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]410
411 /// isFPImmLegal - Returns true if the target can instruction select the
412 /// specified FP immediate natively. If false, the legalizer will
413 /// materialize the FP immediate as a load from a constant pool.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]414 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]415
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]416 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
417 const CallInst &I,
418 unsigned Intrinsic) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]419
420 /// \brief Returns true if it is beneficial to convert a load of a constant
421 /// to just the constant itself.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]422 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
423 Type *Ty) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]424
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]425 /// \brief Returns true if an argument of type Ty needs to be passed in a
426 /// contiguous block of registers in calling convention CallConv.
427 bool functionArgumentNeedsConsecutiveRegisters(
428 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
429
Joseph Tremouletf748c892015-11-07 01:11:31 +0000[diff] [blame]430 /// If a physical register, this returns the register that receives the
431 /// exception address on entry to an EH pad.
432 unsigned
433 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
434
435 /// If a physical register, this returns the register that receives the
436 /// exception typeid on entry to a landing pad.
437 unsigned
438 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
439
Robin Morisset5349e8e2014-09-18 18:56:04 +0000[diff] [blame]440 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]441 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
442 AtomicOrdering Ord) const override;
443 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
444 Value *Addr, AtomicOrdering Ord) const override;
445
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame]446 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
447
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]448 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]449 bool IsStore, bool IsLoad) const override;
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]450 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]451 bool IsStore, bool IsLoad) const override;
452
Hao Liu2cd34bb2015-06-26 02:45:36 +0000[diff] [blame]453 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
454
455 bool lowerInterleavedLoad(LoadInst *LI,
456 ArrayRef<ShuffleVectorInst *> Shuffles,
457 ArrayRef<unsigned> Indices,
458 unsigned Factor) const override;
459 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
460 unsigned Factor) const override;
461
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]462 bool shouldInsertFencesForAtomic(const Instruction *I) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]463 TargetLoweringBase::AtomicExpansionKind
464 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
Robin Morisseted3d48f2014-09-03 21:29:59 +0000[diff] [blame]465 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
Ahmed Bougacha9d677132015-09-11 17:08:17 +0000[diff] [blame]466 TargetLoweringBase::AtomicExpansionKind
JF Bastienf14889e2015-03-04 15:47:57 +0000[diff] [blame]467 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]468 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]469
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]470 bool useLoadStackGuardNode() const override;
471
Quentin Colombetc32615d2014-10-31 17:52:53 +0000[diff] [blame]472 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
473 unsigned &Cost) const override;
474
Sanjay Patelaf1b48b2015-11-10 19:24:31 +0000[diff] [blame]475 bool isCheapToSpeculateCttz() const override;
476 bool isCheapToSpeculateCtlz() const override;
477
Manman Ren57518142016-04-11 21:08:06 +0000[diff] [blame]478 bool supportSwiftError() const override {
479 return true;
480 }
481
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]482 protected:
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]483 std::pair<const TargetRegisterClass *, uint8_t>
484 findRepresentativeClass(const TargetRegisterInfo *TRI,
485 MVT VT) const override;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]486
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]487 private:
488 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
489 /// make the right decision when generating code for different targets.
490 const ARMSubtarget *Subtarget;
491
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]492 const TargetRegisterInfo *RegInfo;
493
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]494 const InstrItineraryData *Itins;
495
Bob Wilson844d6c82009-07-13 18:11:36 +0000[diff] [blame]496 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]497 ///
498 unsigned ARMPCLabelIndex;
499
James Y Knightf44fc522016-03-16 22:12:04 +0000[diff] [blame]500 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
501 // check.
502 bool InsertFencesForAtomic;
503
Craig Topper4fa625f2012-08-12 03:16:37 +0000[diff] [blame]504 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
505 void addDRTypeForNEON(MVT VT);
506 void addQRTypeForNEON(MVT VT);
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]507 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]508
509 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]510 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
511 SDValue &Arg, RegsToPassVector &RegsToPass,
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]512 CCValAssign &VA, CCValAssign &NextVA,
513 SDValue &StackPtr,
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]514 SmallVectorImpl<SDValue> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]515 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]516 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]517 SDValue &Root, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]518 const SDLoc &dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]519
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]520 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
521 bool isVarArg) const;
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]522 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
523 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]524 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]525 const SDLoc &dl, SelectionDAG &DAG,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]526 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]527 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000[diff] [blame]528 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000[diff] [blame]529 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]530 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000[diff] [blame]531 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]532 const ARMSubtarget *Subtarget) const;
533 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +0000[diff] [blame]536 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]537 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]538 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]539 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]540 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +0000[diff] [blame]541 SelectionDAG &DAG,
542 TLSModel::Model model) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000[diff] [blame]543 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasoolf36005a2016-02-03 18:21:59 +0000[diff] [blame]544 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Tim Northoverbd41cf82016-01-07 09:03:03 +0000[diff] [blame]545 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]546 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]547 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000[diff] [blame]548 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]549 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
550 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000[diff] [blame]551 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000[diff] [blame]552 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]553 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]554 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000[diff] [blame]556 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000[diff] [blame]557 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
558 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]559 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]560 const ARMSubtarget *ST) const;
Bob Wilsone7dde0c2013-11-03 06:14:38 +0000[diff] [blame]561 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
Renato Golin87610692013-07-16 09:32:17 +0000[diff] [blame]562 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
Martell Maloned1229242015-11-26 15:34:03 +0000[diff] [blame]563 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
564 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]565 SmallVectorImpl<SDValue> &Results) const;
Martell Maloned1229242015-11-26 15:34:03 +0000[diff] [blame]566 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]567 SDValue &Chain) const;
Scott Douglassbdef6042015-08-24 09:17:18 +0000[diff] [blame]568 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]569 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]570 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
571 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
573 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]574
Pat Gavlina717f252015-07-09 17:40:29 +0000[diff] [blame]575 unsigned getRegisterByName(const char* RegName, EVT VT,
576 SelectionDAG &DAG) const override;
Renato Golinc7aea402014-05-06 16:51:25 +0000[diff] [blame]577
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]578 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
579 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
580 /// expanded to FMAs when this method returns true, otherwise fmuladd is
581 /// expanded to fmul + fadd.
582 ///
583 /// ARM supports both fused and unfused multiply-add operations; we already
Stephen Lin2a644732013-07-10 01:57:39 +0000[diff] [blame]584 /// lower a pair of fmul and fadd to the latter so it's not clear that there
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]585 /// would be a gain or that the gain would be worthwhile enough to risk
586 /// correctness bugs.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]587 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]588
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]589 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000[diff] [blame]590
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]591 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]592 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]593 const SmallVectorImpl<ISD::InputArg> &Ins,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]594 const SDLoc &dl, SelectionDAG &DAG,
595 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
596 SDValue ThisVal) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]597
Manman Ren5e9e65e2016-01-12 00:47:18 +0000[diff] [blame]598 bool supportSplitCSR(MachineFunction *MF) const override {
599 return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
600 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
601 }
602 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
603 void insertCopiesSplitCSR(
604 MachineBasicBlock *Entry,
605 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
606
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]607 SDValue
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]608 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
609 const SmallVectorImpl<ISD::InputArg> &Ins,
610 const SDLoc &dl, SelectionDAG &DAG,
611 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]612
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]613 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
614 SDValue &Chain, const Value *OrigArg,
615 unsigned InRegsParamRecordIdx, int ArgOffset,
Tim Northover8cda34f2015-03-11 18:54:22 +0000[diff] [blame]616 unsigned ArgSize) const;
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]617
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]618 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]619 const SDLoc &dl, SDValue &Chain,
620 unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]621 bool ForceMutable = false) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]622
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]623 SDValue
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]624 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]625 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]626
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]627 /// HandleByVal - Target-specific cleanup for ByVal support.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]628 void HandleByVal(CCState *, unsigned &, unsigned) const override;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]629
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]630 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
631 /// for tail call optimization. Targets which want to do tail call
632 /// optimization should implement this function.
633 bool IsEligibleForTailCallOptimization(SDValue Callee,
634 CallingConv::ID CalleeCC,
635 bool isVarArg,
636 bool isCalleeStructRet,
637 bool isCallerStructRet,
638 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]639 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]640 const SmallVectorImpl<ISD::InputArg> &Ins,
641 SelectionDAG& DAG) const;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]642
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]643 bool CanLowerReturn(CallingConv::ID CallConv,
644 MachineFunction &MF, bool isVarArg,
645 const SmallVectorImpl<ISD::OutputArg> &Outs,
646 LLVMContext &Context) const override;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]647
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]648 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
649 const SmallVectorImpl<ISD::OutputArg> &Outs,
650 const SmallVectorImpl<SDValue> &OutVals,
651 const SDLoc &dl, SelectionDAG &DAG) const override;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]652
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]653 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
Evan Chengd4b08732010-11-30 23:55:39 +0000[diff] [blame]654
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]655 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
Evan Cheng0663f232011-03-21 01:19:09 +0000[diff] [blame]656
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]657 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]658 SDValue ARMcc, SDValue CCR, SDValue Cmp,
659 SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]660 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]661 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
662 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
663 const SDLoc &dl) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000[diff] [blame]664 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]665
666 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]667
Bill Wendling030b58e2011-10-06 22:18:16 +0000[diff] [blame]668 void SetupEntryBlockForSjLj(MachineInstr *MI,
669 MachineBasicBlock *MBB,
670 MachineBasicBlock *DispatchBB, int FI) const;
671
Matthias Brauneec4efc2015-04-28 00:37:05 +0000[diff] [blame]672 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
Bill Wendling374ee192011-10-03 21:25:38 +0000[diff] [blame]673
Andrew Trick0ed57782011-04-23 03:55:32 +0000[diff] [blame]674 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Manman Rene8735522012-06-01 19:33:18 +0000[diff] [blame]675
676 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
677 MachineBasicBlock *MBB) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]678
679 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
680 MachineBasicBlock *MBB) const;
Saleem Abdulrasoolfe83b502015-09-25 05:15:46 +0000[diff] [blame]681 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr *MI,
682 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]683 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]684
Owen Andersona4076922010-11-05 21:57:54 +0000[diff] [blame]685 enum NEONModImmType {
686 VMOVModImm,
687 VMVNModImm,
688 OtherModImm
689 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]690
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]691 namespace ARM {
Bob Wilson3e6fa462012-08-03 04:06:28 +0000[diff] [blame]692 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
693 const TargetLibraryInfo *libInfo);
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]694 }
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]695}
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]696
697#endif // ARMISELLOWERING_H