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Tom Stellardcb97e3a2013-04-15 17:51:35 +00001//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Tom Stellardb6550522015-01-12 19:33:18 +000011#include "llvm/MC/MCInstrDesc.h"
12
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000013#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
Tom Stellardcb97e3a2013-04-15 17:51:35 +000015
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000016namespace llvm {
17
Tom Stellard16a9a202013-08-14 23:24:17 +000018namespace SIInstrFlags {
Matt Arsenaulte2fabd32014-07-29 18:51:56 +000019// This needs to be kept in sync with the field bits in InstSI.
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000020enum : uint64_t {
21 // Low bits - basic encoding information.
22 SALU = 1 << 0,
23 VALU = 1 << 1,
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000024
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000025 // SALU instruction formats.
26 SOP1 = 1 << 2,
27 SOP2 = 1 << 3,
28 SOPC = 1 << 4,
29 SOPK = 1 << 5,
30 SOPP = 1 << 6,
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000031
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000032 // VALU instruction formats.
33 VOP1 = 1 << 7,
34 VOP2 = 1 << 8,
35 VOPC = 1 << 9,
36
37 // TODO: Should this be spilt into VOP3 a and b?
38 VOP3 = 1 << 10,
Matt Arsenault9be7b0d2017-02-27 18:49:11 +000039 VOP3P = 1 << 12,
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000040
41 VINTRP = 1 << 13,
Sam Kolton3025e7f2016-04-26 13:33:56 +000042 SDWA = 1 << 14,
43 DPP = 1 << 15,
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000044
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000045 // Memory instruction formats.
Sam Kolton3025e7f2016-04-26 13:33:56 +000046 MUBUF = 1 << 16,
47 MTBUF = 1 << 17,
48 SMRD = 1 << 18,
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000049 MIMG = 1 << 19,
50 EXP = 1 << 20,
Sam Kolton3025e7f2016-04-26 13:33:56 +000051 FLAT = 1 << 21,
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000052 DS = 1 << 22,
53
54 // Pseudo instruction formats.
55 VGPRSpill = 1 << 23,
56 SGPRSpill = 1 << 24,
57
58 // High bits - other information.
59 VM_CNT = UINT64_C(1) << 32,
60 EXP_CNT = UINT64_C(1) << 33,
61 LGKM_CNT = UINT64_C(1) << 34,
62
63 WQM = UINT64_C(1) << 35,
64 DisableWQM = UINT64_C(1) << 36,
65 Gather4 = UINT64_C(1) << 37,
66 SOPK_ZEXT = UINT64_C(1) << 38,
67 SCALAR_STORE = UINT64_C(1) << 39,
68 FIXED_SIZE = UINT64_C(1) << 40,
Matt Arsenaultd5c65152017-02-22 23:27:53 +000069 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +000070 VOP3_OPSEL = UINT64_C(1) << 42,
71 maybeAtomic = UINT64_C(1) << 43,
Dmitry Preobrazhenskya0342dc2017-11-20 18:24:21 +000072 renamedInGFX9 = UINT64_C(1) << 44,
Matt Arsenaultab4a5cd2017-08-31 23:53:50 +000073
74 // Is a clamp on FP type.
75 FPClamp = UINT64_C(1) << 45,
76
77 // Is an integer clamp
78 IntClamp = UINT64_C(1) << 46,
79
80 // Clamps lo component of register.
81 ClampLo = UINT64_C(1) << 47,
82
83 // Clamps hi component of register.
84 // ClampLo and ClampHi set for packed clamp.
Dmitry Preobrazhensky682a6542017-11-17 15:15:40 +000085 ClampHi = UINT64_C(1) << 48,
86
87 // Is a packed VOP3P instruction.
Changpeng Fang4737e892018-01-18 22:08:53 +000088 IsPacked = UINT64_C(1) << 49,
89
Nicolai Haehnlef2674312018-06-21 13:36:01 +000090 // Is a D16 buffer instruction.
Tim Corringham4c4d2fe2018-12-10 12:06:10 +000091 D16Buf = UINT64_C(1) << 50,
92
93 // Uses floating point double precision rounding mode
94 FPDPRounding = UINT64_C(1) << 51
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +000095};
96
97// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
98// The result is true if any of these tests are true.
99enum ClassFlags {
100 S_NAN = 1 << 0, // Signaling NaN
101 Q_NAN = 1 << 1, // Quiet NaN
102 N_INFINITY = 1 << 2, // Negative infinity
103 N_NORMAL = 1 << 3, // Negative normal
104 N_SUBNORMAL = 1 << 4, // Negative subnormal
105 N_ZERO = 1 << 5, // Negative zero
106 P_ZERO = 1 << 6, // Positive zero
107 P_SUBNORMAL = 1 << 7, // Positive subnormal
108 P_NORMAL = 1 << 8, // Positive normal
109 P_INFINITY = 1 << 9 // Positive infinity
Tom Stellard16a9a202013-08-14 23:24:17 +0000110};
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000111}
Tom Stellard16a9a202013-08-14 23:24:17 +0000112
Tom Stellardb6550522015-01-12 19:33:18 +0000113namespace AMDGPU {
114 enum OperandType {
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000115 /// Operands with register or 32-bit immediate
Matt Arsenault4bd72362016-12-10 00:39:12 +0000116 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,
117 OPERAND_REG_IMM_INT64,
118 OPERAND_REG_IMM_INT16,
119 OPERAND_REG_IMM_FP32,
120 OPERAND_REG_IMM_FP64,
121 OPERAND_REG_IMM_FP16,
122
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000123 /// Operands with register or inline constant
Matt Arsenault4bd72362016-12-10 00:39:12 +0000124 OPERAND_REG_INLINE_C_INT16,
125 OPERAND_REG_INLINE_C_INT32,
126 OPERAND_REG_INLINE_C_INT64,
127 OPERAND_REG_INLINE_C_FP16,
128 OPERAND_REG_INLINE_C_FP32,
129 OPERAND_REG_INLINE_C_FP64,
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000130 OPERAND_REG_INLINE_C_V2FP16,
131 OPERAND_REG_INLINE_C_V2INT16,
Matt Arsenault4bd72362016-12-10 00:39:12 +0000132
133 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
134 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16,
135
136 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000137 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16,
Matt Arsenault4bd72362016-12-10 00:39:12 +0000138
139 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
140 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,
Matt Arsenaultffc82752016-07-05 17:09:01 +0000141
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000142 // Operand for source modifiers for VOP instructions
143 OPERAND_INPUT_MODS,
144
Sam Kolton549c89d2017-06-21 08:53:38 +0000145 // Operand for SDWA instructions
Sam Kolton549c89d2017-06-21 08:53:38 +0000146 OPERAND_SDWA_VOPC_DST,
Sam Koltonf7659d712017-05-23 10:08:55 +0000147
Sam Kolton1eeb11b2016-09-09 14:44:04 +0000148 /// Operand with 32-bit immediate that uses the constant bus.
Matt Arsenault4bd72362016-12-10 00:39:12 +0000149 OPERAND_KIMM32,
150 OPERAND_KIMM16
Tom Stellardb6550522015-01-12 19:33:18 +0000151 };
152}
Matt Arsenault9783e002014-09-29 15:50:26 +0000153
Matt Arsenaultadc59d72018-04-23 15:51:26 +0000154namespace SIStackID {
155enum StackTypes : uint8_t {
156 SCRATCH = 0,
157 SGPR_SPILL = 1
158};
159}
160
Sam Kolton945231a2016-06-10 09:57:59 +0000161// Input operand modifiers bit-masks
162// NEG and SEXT share same bit-mask because they can't be set simultaneously.
Matt Arsenault9783e002014-09-29 15:50:26 +0000163namespace SISrcMods {
164 enum {
Matt Arsenault9be7b0d2017-02-27 18:49:11 +0000165 NEG = 1 << 0, // Floating-point negate modifier
166 ABS = 1 << 1, // Floating-point absolute modifier
167 SEXT = 1 << 0, // Integer sign-extend modifier
168 NEG_HI = ABS, // Floating-point negate high packed component modifier.
169 OP_SEL_0 = 1 << 2,
Dmitry Preobrazhenskyabf28392017-07-21 13:54:11 +0000170 OP_SEL_1 = 1 << 3,
171 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
Matt Arsenault9783e002014-09-29 15:50:26 +0000172 };
173}
174
Matt Arsenault97069782014-09-30 19:49:48 +0000175namespace SIOutMods {
176 enum {
177 NONE = 0,
178 MUL2 = 1,
179 MUL4 = 2,
180 DIV2 = 3
181 };
182}
183
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000184namespace VGPRIndexMode {
185 enum {
186 SRC0_ENABLE = 1 << 0,
187 SRC1_ENABLE = 1 << 1,
188 SRC2_ENABLE = 1 << 2,
189 DST_ENABLE = 1 << 3
190 };
191}
192
Sam Koltond63d8a72016-09-09 09:37:51 +0000193namespace AMDGPUAsmVariants {
194 enum {
195 DEFAULT = 0,
196 VOP3 = 1,
197 SDWA = 2,
Sam Koltonf7659d712017-05-23 10:08:55 +0000198 SDWA9 = 3,
199 DPP = 4
Sam Koltond63d8a72016-09-09 09:37:51 +0000200 };
201}
202
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000203namespace AMDGPU {
Artem Tamazov212a2512016-05-24 12:05:16 +0000204namespace EncValues { // Encoding values of enum9/8/7 operands
205
206enum {
207 SGPR_MIN = 0,
208 SGPR_MAX = 101,
Dmitry Preobrazhenskyac2b0262017-12-11 15:23:20 +0000209 TTMP_VI_MIN = 112,
210 TTMP_VI_MAX = 123,
211 TTMP_GFX9_MIN = 108,
212 TTMP_GFX9_MAX = 123,
Artem Tamazov212a2512016-05-24 12:05:16 +0000213 INLINE_INTEGER_C_MIN = 128,
214 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
215 INLINE_INTEGER_C_MAX = 208,
216 INLINE_FLOATING_C_MIN = 240,
217 INLINE_FLOATING_C_MAX = 248,
218 LITERAL_CONST = 255,
219 VGPR_MIN = 256,
220 VGPR_MAX = 511
221};
222
223} // namespace EncValues
224} // namespace AMDGPU
Artem Tamazov212a2512016-05-24 12:05:16 +0000225
Artem Tamazov212a2512016-05-24 12:05:16 +0000226namespace AMDGPU {
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000227namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
228
Artem Tamazov6edc1352016-05-26 17:00:33 +0000229enum Id { // Message ID, width(4) [3:0].
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000230 ID_UNKNOWN_ = -1,
231 ID_INTERRUPT = 1,
232 ID_GS,
233 ID_GS_DONE,
234 ID_SYSMSG = 15,
235 ID_GAPS_LAST_, // Indicate that sequence has gaps.
236 ID_GAPS_FIRST_ = ID_INTERRUPT,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000237 ID_SHIFT_ = 0,
238 ID_WIDTH_ = 4,
239 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000240};
241
242enum Op { // Both GS and SYS operation IDs.
243 OP_UNKNOWN_ = -1,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000244 OP_SHIFT_ = 4,
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000245 // width(2) [5:4]
246 OP_GS_NOP = 0,
247 OP_GS_CUT,
248 OP_GS_EMIT,
249 OP_GS_EMIT_CUT,
250 OP_GS_LAST_,
251 OP_GS_FIRST_ = OP_GS_NOP,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000252 OP_GS_WIDTH_ = 2,
253 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000254 // width(3) [6:4]
255 OP_SYS_ECC_ERR_INTERRUPT = 1,
256 OP_SYS_REG_RD,
257 OP_SYS_HOST_TRAP_ACK,
258 OP_SYS_TTRACE_PC,
259 OP_SYS_LAST_,
260 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000261 OP_SYS_WIDTH_ = 3,
262 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000263};
264
265enum StreamId { // Stream ID, (2) [9:8].
Artem Tamazov6edc1352016-05-26 17:00:33 +0000266 STREAM_ID_DEFAULT_ = 0,
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000267 STREAM_ID_LAST_ = 4,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000268 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_,
269 STREAM_ID_SHIFT_ = 8,
270 STREAM_ID_WIDTH_= 2,
271 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_)
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000272};
273
274} // namespace SendMsg
Artem Tamazov6edc1352016-05-26 17:00:33 +0000275
276namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
277
278enum Id { // HwRegCode, (6) [5:0]
279 ID_UNKNOWN_ = -1,
280 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
Tom Stellardaea899e2016-10-27 23:50:21 +0000281 ID_MODE = 1,
282 ID_STATUS = 2,
283 ID_TRAPSTS = 3,
284 ID_HW_ID = 4,
285 ID_GPR_ALLOC = 5,
286 ID_LDS_ALLOC = 6,
287 ID_IB_STS = 7,
Konstantin Zhuravlyov4b3847e2017-04-06 23:02:33 +0000288 ID_MEM_BASES = 15,
Stanislav Mekhanoshin62875fc2018-01-15 18:49:15 +0000289 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES,
290 ID_SYMBOLIC_LAST_ = 16,
Artem Tamazov6edc1352016-05-26 17:00:33 +0000291 ID_SHIFT_ = 0,
292 ID_WIDTH_ = 6,
293 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
294};
295
296enum Offset { // Offset, (5) [10:6]
297 OFFSET_DEFAULT_ = 0,
298 OFFSET_SHIFT_ = 6,
299 OFFSET_WIDTH_ = 5,
Konstantin Zhuravlyov4b3847e2017-04-06 23:02:33 +0000300 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),
301
302 OFFSET_SRC_SHARED_BASE = 16,
303 OFFSET_SRC_PRIVATE_BASE = 0
Artem Tamazov6edc1352016-05-26 17:00:33 +0000304};
305
306enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
307 WIDTH_M1_DEFAULT_ = 31,
308 WIDTH_M1_SHIFT_ = 11,
309 WIDTH_M1_WIDTH_ = 5,
Konstantin Zhuravlyov4b3847e2017-04-06 23:02:33 +0000310 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),
311
312 WIDTH_M1_SRC_SHARED_BASE = 15,
313 WIDTH_M1_SRC_PRIVATE_BASE = 15
Artem Tamazov6edc1352016-05-26 17:00:33 +0000314};
315
316} // namespace Hwreg
Sam Koltona3ec5c12016-10-07 14:46:06 +0000317
Dmitry Preobrazhensky793c5922017-05-31 16:26:47 +0000318namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
319
320enum Id { // id of symbolic names
321 ID_QUAD_PERM = 0,
322 ID_BITMASK_PERM,
323 ID_SWAP,
324 ID_REVERSE,
325 ID_BROADCAST
326};
327
328enum EncBits {
329
330 // swizzle mode encodings
331
332 QUAD_PERM_ENC = 0x8000,
333 QUAD_PERM_ENC_MASK = 0xFF00,
334
335 BITMASK_PERM_ENC = 0x0000,
336 BITMASK_PERM_ENC_MASK = 0x8000,
337
338 // QUAD_PERM encodings
339
340 LANE_MASK = 0x3,
341 LANE_MAX = LANE_MASK,
342 LANE_SHIFT = 2,
343 LANE_NUM = 4,
344
345 // BITMASK_PERM encodings
346
347 BITMASK_MASK = 0x1F,
348 BITMASK_MAX = BITMASK_MASK,
349 BITMASK_WIDTH = 5,
350
351 BITMASK_AND_SHIFT = 0,
352 BITMASK_OR_SHIFT = 5,
353 BITMASK_XOR_SHIFT = 10
354};
355
356} // namespace Swizzle
357
Sam Koltona3ec5c12016-10-07 14:46:06 +0000358namespace SDWA {
359
360enum SdwaSel {
361 BYTE_0 = 0,
362 BYTE_1 = 1,
363 BYTE_2 = 2,
364 BYTE_3 = 3,
365 WORD_0 = 4,
366 WORD_1 = 5,
367 DWORD = 6,
368};
369
370enum DstUnused {
371 UNUSED_PAD = 0,
372 UNUSED_SEXT = 1,
373 UNUSED_PRESERVE = 2,
374};
375
Sam Kolton363f47a2017-05-26 15:52:00 +0000376enum SDWA9EncValues{
377 SRC_SGPR_MASK = 0x100,
378 SRC_VGPR_MASK = 0xFF,
379 VOPC_DST_VCC_MASK = 0x80,
380 VOPC_DST_SGPR_MASK = 0x7F,
381
382 SRC_VGPR_MIN = 0,
383 SRC_VGPR_MAX = 255,
384 SRC_SGPR_MIN = 256,
385 SRC_SGPR_MAX = 357,
Dmitry Preobrazhenskyac2b0262017-12-11 15:23:20 +0000386 SRC_TTMP_MIN = 364,
387 SRC_TTMP_MAX = 379,
Sam Kolton363f47a2017-05-26 15:52:00 +0000388};
Sam Koltonf7659d712017-05-23 10:08:55 +0000389
Sam Koltona3ec5c12016-10-07 14:46:06 +0000390} // namespace SDWA
Stanislav Mekhanoshin43293612018-05-08 16:53:02 +0000391
392namespace DPP {
393
394enum DppCtrl {
395 QUAD_PERM_FIRST = 0,
396 QUAD_PERM_LAST = 0xFF,
397 DPP_UNUSED1 = 0x100,
398 ROW_SHL0 = 0x100,
399 ROW_SHL_FIRST = 0x101,
400 ROW_SHL_LAST = 0x10F,
401 DPP_UNUSED2 = 0x110,
402 ROW_SHR0 = 0x110,
403 ROW_SHR_FIRST = 0x111,
404 ROW_SHR_LAST = 0x11F,
405 DPP_UNUSED3 = 0x120,
406 ROW_ROR0 = 0x120,
407 ROW_ROR_FIRST = 0x121,
408 ROW_ROR_LAST = 0x12F,
409 WAVE_SHL1 = 0x130,
410 DPP_UNUSED4_FIRST = 0x131,
411 DPP_UNUSED4_LAST = 0x133,
412 WAVE_ROL1 = 0x134,
413 DPP_UNUSED5_FIRST = 0x135,
414 DPP_UNUSED5_LAST = 0x137,
415 WAVE_SHR1 = 0x138,
416 DPP_UNUSED6_FIRST = 0x139,
417 DPP_UNUSED6_LAST = 0x13B,
418 WAVE_ROR1 = 0x13C,
419 DPP_UNUSED7_FIRST = 0x13D,
420 DPP_UNUSED7_LAST = 0x13F,
421 ROW_MIRROR = 0x140,
422 ROW_HALF_MIRROR = 0x141,
423 BCAST15 = 0x142,
424 BCAST31 = 0x143,
425 DPP_LAST = BCAST31
426};
427
428} // namespace DPP
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000429} // namespace AMDGPU
Artem Tamazovebe71ce2016-05-06 17:48:48 +0000430
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000431#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
Michel Danzer49812b52013-07-10 16:37:07 +0000432#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
433#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000434#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
435#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
Tim Renoufef1ae8f2017-09-29 09:51:22 +0000436#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
Marek Olsaka302a7362017-05-02 15:41:10 +0000437#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
Tim Renoufef1ae8f2017-09-29 09:51:22 +0000438#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000439#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
440#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
441#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
Tom Stellardff7416b2015-06-26 21:58:31 +0000442
Michel Danzer49812b52013-07-10 16:37:07 +0000443#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
Tom Stellard4df465b2014-12-02 21:28:53 +0000444#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
Tom Stellardff7416b2015-06-26 21:58:31 +0000445#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
446#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
Tom Stellard4df465b2014-12-02 21:28:53 +0000447#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
Tom Stellardff7416b2015-06-26 21:58:31 +0000448#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
449#define C_00B84C_USER_SGPR 0xFFFFFFC1
Wei Ding205bfdb2017-02-10 02:15:29 +0000450#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
451#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
452#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
Tom Stellard4df465b2014-12-02 21:28:53 +0000453#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
Tom Stellardff7416b2015-06-26 21:58:31 +0000454#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
455#define C_00B84C_TGID_X_EN 0xFFFFFF7F
Tom Stellard4df465b2014-12-02 21:28:53 +0000456#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
Tom Stellardff7416b2015-06-26 21:58:31 +0000457#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
458#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000459#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
Tom Stellardff7416b2015-06-26 21:58:31 +0000460#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
461#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000462#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
Tom Stellardff7416b2015-06-26 21:58:31 +0000463#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
464#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
Tom Stellard4df465b2014-12-02 21:28:53 +0000465#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
Tom Stellardff7416b2015-06-26 21:58:31 +0000466#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
467#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
468/* CIK */
469#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
470#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
471#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
472/* */
Michel Danzer49812b52013-07-10 16:37:07 +0000473#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
Tom Stellardff7416b2015-06-26 21:58:31 +0000474#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
475#define C_00B84C_LDS_SIZE 0xFF007FFF
476#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
477#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
Matt Arsenault37fefd62016-06-10 02:18:02 +0000478#define C_00B84C_EXCP_EN
Tom Stellardff7416b2015-06-26 21:58:31 +0000479
Tom Stellardcb97e3a2013-04-15 17:51:35 +0000480#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
Marek Olsakfccabaf2016-01-13 11:45:36 +0000481#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
Matt Arsenault0989d512014-06-26 17:22:30 +0000482
483#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
484#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
485#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
486#define C_00B848_VGPRS 0xFFFFFFC0
487#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
488#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
489#define C_00B848_SGPRS 0xFFFFFC3F
490#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
491#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
492#define C_00B848_PRIORITY 0xFFFFF3FF
493#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
494#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
495#define C_00B848_FLOAT_MODE 0xFFF00FFF
496#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
497#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
498#define C_00B848_PRIV 0xFFEFFFFF
499#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
500#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
501#define C_00B848_DX10_CLAMP 0xFFDFFFFF
502#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
503#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
504#define C_00B848_DEBUG_MODE 0xFFBFFFFF
505#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
506#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
507#define C_00B848_IEEE_MODE 0xFF7FFFFF
508
509
510// Helpers for setting FLOAT_MODE
511#define FP_ROUND_ROUND_TO_NEAREST 0
512#define FP_ROUND_ROUND_TO_INF 1
513#define FP_ROUND_ROUND_TO_NEGINF 2
514#define FP_ROUND_ROUND_TO_ZERO 3
515
516// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
517// precision.
518#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
519#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
520
521#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
522#define FP_DENORM_FLUSH_OUT 1
523#define FP_DENORM_FLUSH_IN 2
524#define FP_DENORM_FLUSH_NONE 3
525
526
527// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
528// precision.
529#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
530#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
531
Tom Stellardb02094e2014-07-21 15:45:01 +0000532#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
533#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
534
Tom Stellarde99fb652015-01-20 19:33:04 +0000535#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
536#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
537
Marek Olsak0532c192016-07-13 17:35:15 +0000538#define R_SPILLED_SGPRS 0x4
539#define R_SPILLED_VGPRS 0x8
Matt Arsenaulteb4a55e2016-12-09 17:49:08 +0000540} // End namespace llvm
541
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000542#endif