blob: b24f4f11182ecf77a78baeaaaed78b350ed9ae3f [file] [log] [blame]
Matt Arsenault70b92822017-11-12 23:53:44 +00001; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +00003
Matt Arsenault0c687392017-01-30 16:57:41 +00004; GCN-LABEL: {{^}}br_cc_f16:
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +00005; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
6; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
7
Stanislav Mekhanoshind4ae4702017-09-19 20:54:38 +00008; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
9; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
10; SI: v_cmp_nlt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000011; VI: v_cmp_nlt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
12; GCN: s_cbranch_vccnz
13
Matt Arsenault8c4a3522018-06-26 19:10:00 +000014; SI: one{{$}}
15; SI: v_cvt_f16_f32_e32 v[[CVT:[0-9]+]], v[[A_F32]]
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000016
Matt Arsenault8c4a3522018-06-26 19:10:00 +000017; SI: two{{$}}
18; SI: v_cvt_f16_f32_e32 v[[CVT]], v[[B_F32]]
19
20; SI: one{{$}}
21; SI: buffer_store_short v[[CVT]]
22; SI: s_endpgm
23
24
25
26; VI: one{{$}}
27; VI: buffer_store_short v[[A_F16]]
28; VI: s_endpgm
29
30; VI: two{{$}}
31; VI: buffer_store_short v[[B_F16]]
32; VI: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000033define amdgpu_kernel void @br_cc_f16(
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000034 half addrspace(1)* %r,
35 half addrspace(1)* %a,
36 half addrspace(1)* %b) {
37entry:
Matt Arsenault8c4a3522018-06-26 19:10:00 +000038 %a.val = load volatile half, half addrspace(1)* %a
39 %b.val = load volatile half, half addrspace(1)* %b
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000040 %fcmp = fcmp olt half %a.val, %b.val
41 br i1 %fcmp, label %one, label %two
42
43one:
44 store half %a.val, half addrspace(1)* %r
45 ret void
46
47two:
48 store half %b.val, half addrspace(1)* %r
49 ret void
50}
51
Matt Arsenault0c687392017-01-30 16:57:41 +000052; GCN-LABEL: {{^}}br_cc_f16_imm_a:
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000053; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
54
55; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
Matt Arsenault0c687392017-01-30 16:57:41 +000056; SI: v_cmp_nlt_f32_e32 vcc, 0.5, v[[B_F32]]
57; SI: s_cbranch_vccnz
Matt Arsenaulte96d0372016-12-08 20:14:46 +000058
Matt Arsenault4bd72362016-12-10 00:39:12 +000059; VI: v_cmp_nlt_f16_e32 vcc, 0.5, v[[B_F16]]
Matt Arsenaultad55ee52016-12-06 01:02:51 +000060; VI: s_cbranch_vccnz
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000061
Matt Arsenault0c687392017-01-30 16:57:41 +000062; GCN: one{{$}}
Matt Arsenault70b92822017-11-12 23:53:44 +000063; GCN: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}}
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000064
Matt Arsenault0c687392017-01-30 16:57:41 +000065; SI: buffer_store_short v[[A_F16]]
66; SI: s_endpgm
67
68
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000069; GCN: two{{$}}
70; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
Matt Arsenaultad55ee52016-12-06 01:02:51 +000071
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000072define amdgpu_kernel void @br_cc_f16_imm_a(
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000073 half addrspace(1)* %r,
74 half addrspace(1)* %b) {
75entry:
76 %b.val = load half, half addrspace(1)* %b
77 %fcmp = fcmp olt half 0xH3800, %b.val
78 br i1 %fcmp, label %one, label %two
79
80one:
81 store half 0xH3800, half addrspace(1)* %r
82 ret void
83
84two:
85 store half %b.val, half addrspace(1)* %r
86 ret void
87}
88
Matt Arsenault0c687392017-01-30 16:57:41 +000089; GCN-LABEL: {{^}}br_cc_f16_imm_b:
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000090; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
91
92; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
Matt Arsenault0c687392017-01-30 16:57:41 +000093; SI: v_cmp_ngt_f32_e32 vcc, 0.5, v[[A_F32]]
94
Matt Arsenault4bd72362016-12-10 00:39:12 +000095; VI: v_cmp_ngt_f16_e32 vcc, 0.5, v[[A_F16]]
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +000096; GCN: s_cbranch_vccnz
97
98; GCN: one{{$}}
99; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +0000100
101; GCN: two{{$}}
Matt Arsenault70b92822017-11-12 23:53:44 +0000102; GCN: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +0000103; GCN: buffer_store_short v[[B_F16]]
104; GCN: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000105define amdgpu_kernel void @br_cc_f16_imm_b(
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +0000106 half addrspace(1)* %r,
107 half addrspace(1)* %a) {
108entry:
109 %a.val = load half, half addrspace(1)* %a
110 %fcmp = fcmp olt half %a.val, 0xH3800
111 br i1 %fcmp, label %one, label %two
112
113one:
114 store half %a.val, half addrspace(1)* %r
115 ret void
116
117two:
118 store half 0xH3800, half addrspace(1)* %r
119 ret void
120}