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gerrit-public.fairphone.software / toolchain / llvm-project / 829da45631de0383ba9043dcee0fd78c90aaac1c / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 6d499e3489ac5803fd1107bc9ca73cfc0a5a0718 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
41/// InitLibcallNames - Set default libcall names.
42///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]43static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]44 Names[RTLIB::SHL_I16] = "__ashlhi3";
45 Names[RTLIB::SHL_I32] = "__ashlsi3";
46 Names[RTLIB::SHL_I64] = "__ashldi3";
47 Names[RTLIB::SHL_I128] = "__ashlti3";
48 Names[RTLIB::SRL_I16] = "__lshrhi3";
49 Names[RTLIB::SRL_I32] = "__lshrsi3";
50 Names[RTLIB::SRL_I64] = "__lshrdi3";
51 Names[RTLIB::SRL_I128] = "__lshrti3";
52 Names[RTLIB::SRA_I16] = "__ashrhi3";
53 Names[RTLIB::SRA_I32] = "__ashrsi3";
54 Names[RTLIB::SRA_I64] = "__ashrdi3";
55 Names[RTLIB::SRA_I128] = "__ashrti3";
56 Names[RTLIB::MUL_I8] = "__mulqi3";
57 Names[RTLIB::MUL_I16] = "__mulhi3";
58 Names[RTLIB::MUL_I32] = "__mulsi3";
59 Names[RTLIB::MUL_I64] = "__muldi3";
60 Names[RTLIB::MUL_I128] = "__multi3";
61 Names[RTLIB::MULO_I32] = "__mulosi4";
62 Names[RTLIB::MULO_I64] = "__mulodi4";
63 Names[RTLIB::MULO_I128] = "__muloti4";
64 Names[RTLIB::SDIV_I8] = "__divqi3";
65 Names[RTLIB::SDIV_I16] = "__divhi3";
66 Names[RTLIB::SDIV_I32] = "__divsi3";
67 Names[RTLIB::SDIV_I64] = "__divdi3";
68 Names[RTLIB::SDIV_I128] = "__divti3";
69 Names[RTLIB::UDIV_I8] = "__udivqi3";
70 Names[RTLIB::UDIV_I16] = "__udivhi3";
71 Names[RTLIB::UDIV_I32] = "__udivsi3";
72 Names[RTLIB::UDIV_I64] = "__udivdi3";
73 Names[RTLIB::UDIV_I128] = "__udivti3";
74 Names[RTLIB::SREM_I8] = "__modqi3";
75 Names[RTLIB::SREM_I16] = "__modhi3";
76 Names[RTLIB::SREM_I32] = "__modsi3";
77 Names[RTLIB::SREM_I64] = "__moddi3";
78 Names[RTLIB::SREM_I128] = "__modti3";
79 Names[RTLIB::UREM_I8] = "__umodqi3";
80 Names[RTLIB::UREM_I16] = "__umodhi3";
81 Names[RTLIB::UREM_I32] = "__umodsi3";
82 Names[RTLIB::UREM_I64] = "__umoddi3";
83 Names[RTLIB::UREM_I128] = "__umodti3";
84
85 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]86 Names[RTLIB::SDIVREM_I8] = nullptr;
87 Names[RTLIB::SDIVREM_I16] = nullptr;
88 Names[RTLIB::SDIVREM_I32] = nullptr;
89 Names[RTLIB::SDIVREM_I64] = nullptr;
90 Names[RTLIB::SDIVREM_I128] = nullptr;
91 Names[RTLIB::UDIVREM_I8] = nullptr;
92 Names[RTLIB::UDIVREM_I16] = nullptr;
93 Names[RTLIB::UDIVREM_I32] = nullptr;
94 Names[RTLIB::UDIVREM_I64] = nullptr;
95 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]96
97 Names[RTLIB::NEG_I32] = "__negsi2";
98 Names[RTLIB::NEG_I64] = "__negdi2";
99 Names[RTLIB::ADD_F32] = "__addsf3";
100 Names[RTLIB::ADD_F64] = "__adddf3";
101 Names[RTLIB::ADD_F80] = "__addxf3";
102 Names[RTLIB::ADD_F128] = "__addtf3";
103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
104 Names[RTLIB::SUB_F32] = "__subsf3";
105 Names[RTLIB::SUB_F64] = "__subdf3";
106 Names[RTLIB::SUB_F80] = "__subxf3";
107 Names[RTLIB::SUB_F128] = "__subtf3";
108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
109 Names[RTLIB::MUL_F32] = "__mulsf3";
110 Names[RTLIB::MUL_F64] = "__muldf3";
111 Names[RTLIB::MUL_F80] = "__mulxf3";
112 Names[RTLIB::MUL_F128] = "__multf3";
113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
114 Names[RTLIB::DIV_F32] = "__divsf3";
115 Names[RTLIB::DIV_F64] = "__divdf3";
116 Names[RTLIB::DIV_F80] = "__divxf3";
117 Names[RTLIB::DIV_F128] = "__divtf3";
118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
119 Names[RTLIB::REM_F32] = "fmodf";
120 Names[RTLIB::REM_F64] = "fmod";
121 Names[RTLIB::REM_F80] = "fmodl";
122 Names[RTLIB::REM_F128] = "fmodl";
123 Names[RTLIB::REM_PPCF128] = "fmodl";
124 Names[RTLIB::FMA_F32] = "fmaf";
125 Names[RTLIB::FMA_F64] = "fma";
126 Names[RTLIB::FMA_F80] = "fmal";
127 Names[RTLIB::FMA_F128] = "fmal";
128 Names[RTLIB::FMA_PPCF128] = "fmal";
129 Names[RTLIB::POWI_F32] = "__powisf2";
130 Names[RTLIB::POWI_F64] = "__powidf2";
131 Names[RTLIB::POWI_F80] = "__powixf2";
132 Names[RTLIB::POWI_F128] = "__powitf2";
133 Names[RTLIB::POWI_PPCF128] = "__powitf2";
134 Names[RTLIB::SQRT_F32] = "sqrtf";
135 Names[RTLIB::SQRT_F64] = "sqrt";
136 Names[RTLIB::SQRT_F80] = "sqrtl";
137 Names[RTLIB::SQRT_F128] = "sqrtl";
138 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
139 Names[RTLIB::LOG_F32] = "logf";
140 Names[RTLIB::LOG_F64] = "log";
141 Names[RTLIB::LOG_F80] = "logl";
142 Names[RTLIB::LOG_F128] = "logl";
143 Names[RTLIB::LOG_PPCF128] = "logl";
144 Names[RTLIB::LOG2_F32] = "log2f";
145 Names[RTLIB::LOG2_F64] = "log2";
146 Names[RTLIB::LOG2_F80] = "log2l";
147 Names[RTLIB::LOG2_F128] = "log2l";
148 Names[RTLIB::LOG2_PPCF128] = "log2l";
149 Names[RTLIB::LOG10_F32] = "log10f";
150 Names[RTLIB::LOG10_F64] = "log10";
151 Names[RTLIB::LOG10_F80] = "log10l";
152 Names[RTLIB::LOG10_F128] = "log10l";
153 Names[RTLIB::LOG10_PPCF128] = "log10l";
154 Names[RTLIB::EXP_F32] = "expf";
155 Names[RTLIB::EXP_F64] = "exp";
156 Names[RTLIB::EXP_F80] = "expl";
157 Names[RTLIB::EXP_F128] = "expl";
158 Names[RTLIB::EXP_PPCF128] = "expl";
159 Names[RTLIB::EXP2_F32] = "exp2f";
160 Names[RTLIB::EXP2_F64] = "exp2";
161 Names[RTLIB::EXP2_F80] = "exp2l";
162 Names[RTLIB::EXP2_F128] = "exp2l";
163 Names[RTLIB::EXP2_PPCF128] = "exp2l";
164 Names[RTLIB::SIN_F32] = "sinf";
165 Names[RTLIB::SIN_F64] = "sin";
166 Names[RTLIB::SIN_F80] = "sinl";
167 Names[RTLIB::SIN_F128] = "sinl";
168 Names[RTLIB::SIN_PPCF128] = "sinl";
169 Names[RTLIB::COS_F32] = "cosf";
170 Names[RTLIB::COS_F64] = "cos";
171 Names[RTLIB::COS_F80] = "cosl";
172 Names[RTLIB::COS_F128] = "cosl";
173 Names[RTLIB::COS_PPCF128] = "cosl";
174 Names[RTLIB::POW_F32] = "powf";
175 Names[RTLIB::POW_F64] = "pow";
176 Names[RTLIB::POW_F80] = "powl";
177 Names[RTLIB::POW_F128] = "powl";
178 Names[RTLIB::POW_PPCF128] = "powl";
179 Names[RTLIB::CEIL_F32] = "ceilf";
180 Names[RTLIB::CEIL_F64] = "ceil";
181 Names[RTLIB::CEIL_F80] = "ceill";
182 Names[RTLIB::CEIL_F128] = "ceill";
183 Names[RTLIB::CEIL_PPCF128] = "ceill";
184 Names[RTLIB::TRUNC_F32] = "truncf";
185 Names[RTLIB::TRUNC_F64] = "trunc";
186 Names[RTLIB::TRUNC_F80] = "truncl";
187 Names[RTLIB::TRUNC_F128] = "truncl";
188 Names[RTLIB::TRUNC_PPCF128] = "truncl";
189 Names[RTLIB::RINT_F32] = "rintf";
190 Names[RTLIB::RINT_F64] = "rint";
191 Names[RTLIB::RINT_F80] = "rintl";
192 Names[RTLIB::RINT_F128] = "rintl";
193 Names[RTLIB::RINT_PPCF128] = "rintl";
194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
195 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]199 Names[RTLIB::ROUND_F32] = "roundf";
200 Names[RTLIB::ROUND_F64] = "round";
201 Names[RTLIB::ROUND_F80] = "roundl";
202 Names[RTLIB::ROUND_F128] = "roundl";
203 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]204 Names[RTLIB::FLOOR_F32] = "floorf";
205 Names[RTLIB::FLOOR_F64] = "floor";
206 Names[RTLIB::FLOOR_F80] = "floorl";
207 Names[RTLIB::FLOOR_F128] = "floorl";
208 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]209 Names[RTLIB::FMIN_F32] = "fminf";
210 Names[RTLIB::FMIN_F64] = "fmin";
211 Names[RTLIB::FMIN_F80] = "fminl";
212 Names[RTLIB::FMIN_F128] = "fminl";
213 Names[RTLIB::FMIN_PPCF128] = "fminl";
214 Names[RTLIB::FMAX_F32] = "fmaxf";
215 Names[RTLIB::FMAX_F64] = "fmax";
216 Names[RTLIB::FMAX_F80] = "fmaxl";
217 Names[RTLIB::FMAX_F128] = "fmaxl";
218 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]219 Names[RTLIB::ROUND_F32] = "roundf";
220 Names[RTLIB::ROUND_F64] = "round";
221 Names[RTLIB::ROUND_F80] = "roundl";
222 Names[RTLIB::ROUND_F128] = "roundl";
223 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]224 Names[RTLIB::COPYSIGN_F32] = "copysignf";
225 Names[RTLIB::COPYSIGN_F64] = "copysign";
226 Names[RTLIB::COPYSIGN_F80] = "copysignl";
227 Names[RTLIB::COPYSIGN_F128] = "copysignl";
228 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
229 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
230 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
231 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
232 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
233 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]234 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
235 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
236 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
237 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]238 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
239 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
240 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
241 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
242 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
243 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
244 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
245 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
246 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
247 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
248 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
249 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
250 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
251 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
252 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
253 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
254 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
255 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
256 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
257 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
258 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
259 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
260 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
261 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
262 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
263 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
264 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
265 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
266 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
267 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
268 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
269 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
270 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
271 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
272 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
273 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
274 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
275 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
276 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
277 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
278 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
279 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
280 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
281 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
282 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
283 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
284 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
285 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
286 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
287 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
288 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
289 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
290 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
291 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
292 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
293 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
294 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
295 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
296 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
297 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
298 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
299 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
300 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
301 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
302 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
303 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
304 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
305 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
306 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
307 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
308 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
309 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
310 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
311 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
312 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
313 Names[RTLIB::OEQ_F32] = "__eqsf2";
314 Names[RTLIB::OEQ_F64] = "__eqdf2";
315 Names[RTLIB::OEQ_F128] = "__eqtf2";
316 Names[RTLIB::UNE_F32] = "__nesf2";
317 Names[RTLIB::UNE_F64] = "__nedf2";
318 Names[RTLIB::UNE_F128] = "__netf2";
319 Names[RTLIB::OGE_F32] = "__gesf2";
320 Names[RTLIB::OGE_F64] = "__gedf2";
321 Names[RTLIB::OGE_F128] = "__getf2";
322 Names[RTLIB::OLT_F32] = "__ltsf2";
323 Names[RTLIB::OLT_F64] = "__ltdf2";
324 Names[RTLIB::OLT_F128] = "__lttf2";
325 Names[RTLIB::OLE_F32] = "__lesf2";
326 Names[RTLIB::OLE_F64] = "__ledf2";
327 Names[RTLIB::OLE_F128] = "__letf2";
328 Names[RTLIB::OGT_F32] = "__gtsf2";
329 Names[RTLIB::OGT_F64] = "__gtdf2";
330 Names[RTLIB::OGT_F128] = "__gttf2";
331 Names[RTLIB::UO_F32] = "__unordsf2";
332 Names[RTLIB::UO_F64] = "__unorddf2";
333 Names[RTLIB::UO_F128] = "__unordtf2";
334 Names[RTLIB::O_F32] = "__unordsf2";
335 Names[RTLIB::O_F64] = "__unorddf2";
336 Names[RTLIB::O_F128] = "__unordtf2";
337 Names[RTLIB::MEMCPY] = "memcpy";
338 Names[RTLIB::MEMMOVE] = "memmove";
339 Names[RTLIB::MEMSET] = "memset";
340 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
341 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
342 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
343 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
347 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
348 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]351 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
352 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
353 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
354 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]355 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]356 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
357 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
358 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
359 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
362 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
363 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
364 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
367 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
368 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
369 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]371 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
372 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
373 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
374 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]375 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]376 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
377 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
378 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
379 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]380 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]381 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
382 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
383 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
384 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
385 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
386 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
387 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
388 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
389 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
390 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
391 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
392 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
393 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
394 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
395 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
396 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
397 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
398 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
399 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
400 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]401
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]402 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]403 Names[RTLIB::SINCOS_F32] = "sincosf";
404 Names[RTLIB::SINCOS_F64] = "sincos";
405 Names[RTLIB::SINCOS_F80] = "sincosl";
406 Names[RTLIB::SINCOS_F128] = "sincosl";
407 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
408 } else {
409 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]410 Names[RTLIB::SINCOS_F32] = nullptr;
411 Names[RTLIB::SINCOS_F64] = nullptr;
412 Names[RTLIB::SINCOS_F80] = nullptr;
413 Names[RTLIB::SINCOS_F128] = nullptr;
414 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]415 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]416
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]417 if (TT.getOS() != Triple::OpenBSD) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]418 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
419 } else {
420 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]421 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]422 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]423}
424
425/// InitLibcallCallingConvs - Set default libcall CallingConvs.
426///
427static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
428 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
429 CCs[i] = CallingConv::C;
430 }
431}
432
433/// getFPEXT - Return the FPEXT_*_* value for the given types, or
434/// UNKNOWN_LIBCALL if there is none.
435RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]436 if (OpVT == MVT::f16) {
437 if (RetVT == MVT::f32)
438 return FPEXT_F16_F32;
439 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]440 if (RetVT == MVT::f64)
441 return FPEXT_F32_F64;
442 if (RetVT == MVT::f128)
443 return FPEXT_F32_F128;
444 } else if (OpVT == MVT::f64) {
445 if (RetVT == MVT::f128)
446 return FPEXT_F64_F128;
447 }
448
449 return UNKNOWN_LIBCALL;
450}
451
452/// getFPROUND - Return the FPROUND_*_* value for the given types, or
453/// UNKNOWN_LIBCALL if there is none.
454RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]455 if (RetVT == MVT::f16) {
456 if (OpVT == MVT::f32)
457 return FPROUND_F32_F16;
458 if (OpVT == MVT::f64)
459 return FPROUND_F64_F16;
460 if (OpVT == MVT::f80)
461 return FPROUND_F80_F16;
462 if (OpVT == MVT::f128)
463 return FPROUND_F128_F16;
464 if (OpVT == MVT::ppcf128)
465 return FPROUND_PPCF128_F16;
466 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]467 if (OpVT == MVT::f64)
468 return FPROUND_F64_F32;
469 if (OpVT == MVT::f80)
470 return FPROUND_F80_F32;
471 if (OpVT == MVT::f128)
472 return FPROUND_F128_F32;
473 if (OpVT == MVT::ppcf128)
474 return FPROUND_PPCF128_F32;
475 } else if (RetVT == MVT::f64) {
476 if (OpVT == MVT::f80)
477 return FPROUND_F80_F64;
478 if (OpVT == MVT::f128)
479 return FPROUND_F128_F64;
480 if (OpVT == MVT::ppcf128)
481 return FPROUND_PPCF128_F64;
482 }
483
484 return UNKNOWN_LIBCALL;
485}
486
487/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::f32) {
491 if (RetVT == MVT::i8)
492 return FPTOSINT_F32_I8;
493 if (RetVT == MVT::i16)
494 return FPTOSINT_F32_I16;
495 if (RetVT == MVT::i32)
496 return FPTOSINT_F32_I32;
497 if (RetVT == MVT::i64)
498 return FPTOSINT_F32_I64;
499 if (RetVT == MVT::i128)
500 return FPTOSINT_F32_I128;
501 } else if (OpVT == MVT::f64) {
502 if (RetVT == MVT::i8)
503 return FPTOSINT_F64_I8;
504 if (RetVT == MVT::i16)
505 return FPTOSINT_F64_I16;
506 if (RetVT == MVT::i32)
507 return FPTOSINT_F64_I32;
508 if (RetVT == MVT::i64)
509 return FPTOSINT_F64_I64;
510 if (RetVT == MVT::i128)
511 return FPTOSINT_F64_I128;
512 } else if (OpVT == MVT::f80) {
513 if (RetVT == MVT::i32)
514 return FPTOSINT_F80_I32;
515 if (RetVT == MVT::i64)
516 return FPTOSINT_F80_I64;
517 if (RetVT == MVT::i128)
518 return FPTOSINT_F80_I128;
519 } else if (OpVT == MVT::f128) {
520 if (RetVT == MVT::i32)
521 return FPTOSINT_F128_I32;
522 if (RetVT == MVT::i64)
523 return FPTOSINT_F128_I64;
524 if (RetVT == MVT::i128)
525 return FPTOSINT_F128_I128;
526 } else if (OpVT == MVT::ppcf128) {
527 if (RetVT == MVT::i32)
528 return FPTOSINT_PPCF128_I32;
529 if (RetVT == MVT::i64)
530 return FPTOSINT_PPCF128_I64;
531 if (RetVT == MVT::i128)
532 return FPTOSINT_PPCF128_I128;
533 }
534 return UNKNOWN_LIBCALL;
535}
536
537/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
538/// UNKNOWN_LIBCALL if there is none.
539RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
540 if (OpVT == MVT::f32) {
541 if (RetVT == MVT::i8)
542 return FPTOUINT_F32_I8;
543 if (RetVT == MVT::i16)
544 return FPTOUINT_F32_I16;
545 if (RetVT == MVT::i32)
546 return FPTOUINT_F32_I32;
547 if (RetVT == MVT::i64)
548 return FPTOUINT_F32_I64;
549 if (RetVT == MVT::i128)
550 return FPTOUINT_F32_I128;
551 } else if (OpVT == MVT::f64) {
552 if (RetVT == MVT::i8)
553 return FPTOUINT_F64_I8;
554 if (RetVT == MVT::i16)
555 return FPTOUINT_F64_I16;
556 if (RetVT == MVT::i32)
557 return FPTOUINT_F64_I32;
558 if (RetVT == MVT::i64)
559 return FPTOUINT_F64_I64;
560 if (RetVT == MVT::i128)
561 return FPTOUINT_F64_I128;
562 } else if (OpVT == MVT::f80) {
563 if (RetVT == MVT::i32)
564 return FPTOUINT_F80_I32;
565 if (RetVT == MVT::i64)
566 return FPTOUINT_F80_I64;
567 if (RetVT == MVT::i128)
568 return FPTOUINT_F80_I128;
569 } else if (OpVT == MVT::f128) {
570 if (RetVT == MVT::i32)
571 return FPTOUINT_F128_I32;
572 if (RetVT == MVT::i64)
573 return FPTOUINT_F128_I64;
574 if (RetVT == MVT::i128)
575 return FPTOUINT_F128_I128;
576 } else if (OpVT == MVT::ppcf128) {
577 if (RetVT == MVT::i32)
578 return FPTOUINT_PPCF128_I32;
579 if (RetVT == MVT::i64)
580 return FPTOUINT_PPCF128_I64;
581 if (RetVT == MVT::i128)
582 return FPTOUINT_PPCF128_I128;
583 }
584 return UNKNOWN_LIBCALL;
585}
586
587/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
588/// UNKNOWN_LIBCALL if there is none.
589RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
590 if (OpVT == MVT::i32) {
591 if (RetVT == MVT::f32)
592 return SINTTOFP_I32_F32;
593 if (RetVT == MVT::f64)
594 return SINTTOFP_I32_F64;
595 if (RetVT == MVT::f80)
596 return SINTTOFP_I32_F80;
597 if (RetVT == MVT::f128)
598 return SINTTOFP_I32_F128;
599 if (RetVT == MVT::ppcf128)
600 return SINTTOFP_I32_PPCF128;
601 } else if (OpVT == MVT::i64) {
602 if (RetVT == MVT::f32)
603 return SINTTOFP_I64_F32;
604 if (RetVT == MVT::f64)
605 return SINTTOFP_I64_F64;
606 if (RetVT == MVT::f80)
607 return SINTTOFP_I64_F80;
608 if (RetVT == MVT::f128)
609 return SINTTOFP_I64_F128;
610 if (RetVT == MVT::ppcf128)
611 return SINTTOFP_I64_PPCF128;
612 } else if (OpVT == MVT::i128) {
613 if (RetVT == MVT::f32)
614 return SINTTOFP_I128_F32;
615 if (RetVT == MVT::f64)
616 return SINTTOFP_I128_F64;
617 if (RetVT == MVT::f80)
618 return SINTTOFP_I128_F80;
619 if (RetVT == MVT::f128)
620 return SINTTOFP_I128_F128;
621 if (RetVT == MVT::ppcf128)
622 return SINTTOFP_I128_PPCF128;
623 }
624 return UNKNOWN_LIBCALL;
625}
626
627/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
628/// UNKNOWN_LIBCALL if there is none.
629RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
630 if (OpVT == MVT::i32) {
631 if (RetVT == MVT::f32)
632 return UINTTOFP_I32_F32;
633 if (RetVT == MVT::f64)
634 return UINTTOFP_I32_F64;
635 if (RetVT == MVT::f80)
636 return UINTTOFP_I32_F80;
637 if (RetVT == MVT::f128)
638 return UINTTOFP_I32_F128;
639 if (RetVT == MVT::ppcf128)
640 return UINTTOFP_I32_PPCF128;
641 } else if (OpVT == MVT::i64) {
642 if (RetVT == MVT::f32)
643 return UINTTOFP_I64_F32;
644 if (RetVT == MVT::f64)
645 return UINTTOFP_I64_F64;
646 if (RetVT == MVT::f80)
647 return UINTTOFP_I64_F80;
648 if (RetVT == MVT::f128)
649 return UINTTOFP_I64_F128;
650 if (RetVT == MVT::ppcf128)
651 return UINTTOFP_I64_PPCF128;
652 } else if (OpVT == MVT::i128) {
653 if (RetVT == MVT::f32)
654 return UINTTOFP_I128_F32;
655 if (RetVT == MVT::f64)
656 return UINTTOFP_I128_F64;
657 if (RetVT == MVT::f80)
658 return UINTTOFP_I128_F80;
659 if (RetVT == MVT::f128)
660 return UINTTOFP_I128_F128;
661 if (RetVT == MVT::ppcf128)
662 return UINTTOFP_I128_PPCF128;
663 }
664 return UNKNOWN_LIBCALL;
665}
666
667/// InitCmpLibcallCCs - Set default comparison libcall CC.
668///
669static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
670 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
671 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
672 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
673 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
674 CCs[RTLIB::UNE_F32] = ISD::SETNE;
675 CCs[RTLIB::UNE_F64] = ISD::SETNE;
676 CCs[RTLIB::UNE_F128] = ISD::SETNE;
677 CCs[RTLIB::OGE_F32] = ISD::SETGE;
678 CCs[RTLIB::OGE_F64] = ISD::SETGE;
679 CCs[RTLIB::OGE_F128] = ISD::SETGE;
680 CCs[RTLIB::OLT_F32] = ISD::SETLT;
681 CCs[RTLIB::OLT_F64] = ISD::SETLT;
682 CCs[RTLIB::OLT_F128] = ISD::SETLT;
683 CCs[RTLIB::OLE_F32] = ISD::SETLE;
684 CCs[RTLIB::OLE_F64] = ISD::SETLE;
685 CCs[RTLIB::OLE_F128] = ISD::SETLE;
686 CCs[RTLIB::OGT_F32] = ISD::SETGT;
687 CCs[RTLIB::OGT_F64] = ISD::SETGT;
688 CCs[RTLIB::OGT_F128] = ISD::SETGT;
689 CCs[RTLIB::UO_F32] = ISD::SETNE;
690 CCs[RTLIB::UO_F64] = ISD::SETNE;
691 CCs[RTLIB::UO_F128] = ISD::SETNE;
692 CCs[RTLIB::O_F32] = ISD::SETEQ;
693 CCs[RTLIB::O_F64] = ISD::SETEQ;
694 CCs[RTLIB::O_F128] = ISD::SETEQ;
695}
696
697/// NOTE: The constructor takes ownership of TLOF.
698TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
699 const TargetLoweringObjectFile *tlof)
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]700 : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()), TLOF(*tlof) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]701 initActions();
702
703 // Perform these initializations only once.
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]704 IsLittleEndian = DL->isLittleEndian();
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]705 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
706 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
707 = MaxStoresPerMemmoveOptSize = 4;
708 UseUnderscoreSetJmp = false;
709 UseUnderscoreLongJmp = false;
710 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]711 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]712 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]713 IntDivIsCheap = false;
Sanjay Patel2cdea4c2014-08-21 22:31:48 +0000[diff] [blame]714 Pow2SDivIsCheap = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]715 JumpIsExpensive = false;
716 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]717 MaskAndBranchFoldingIsLegal = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]718 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]719 StackPointerRegisterToSaveRestore = 0;
720 ExceptionPointerRegister = 0;
721 ExceptionSelectorRegister = 0;
722 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]723 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]724 BooleanVectorContents = UndefinedBooleanContent;
725 SchedPreferenceInfo = Sched::ILP;
726 JumpBufSize = 0;
727 JumpBufAlignment = 0;
728 MinFunctionAlignment = 0;
729 PrefFunctionAlignment = 0;
730 PrefLoopAlignment = 0;
731 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]732 InsertFencesForAtomic = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]733 MinimumJumpTableEntries = 4;
734
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]735 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]736 InitCmpLibcallCCs(CmpLibcallCCs);
737 InitLibcallCallingConvs(LibcallCallingConvs);
738}
739
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]740void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]741 // All operations default to being supported.
742 memset(OpActions, 0, sizeof(OpActions));
743 memset(LoadExtActions, 0, sizeof(LoadExtActions));
744 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
745 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
746 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]747 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
748 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]749
750 // Set default actions for various operations.
751 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
752 // Default all indexed load / store to expand.
753 for (unsigned IM = (unsigned)ISD::PRE_INC;
754 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
755 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
756 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
757 }
758
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]759 // Most backends expect to see the node which just returns the value loaded.
760 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
761 (MVT::SimpleValueType)VT, Expand);
762
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]763 // These operations default to expand.
764 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]766 setOperationAction(ISD::FMINNUM, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::FMAXNUM, (MVT::SimpleValueType)VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]768
769 // These library functions default to expand.
770 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]771
772 // These operations default to expand for vector types.
773 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]774 VT <= MVT::LAST_VECTOR_VALUETYPE) {
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]775 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
Chandler Carruth0b666e02014-07-10 12:32:32 +0000[diff] [blame]776 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,
777 (MVT::SimpleValueType)VT, Expand);
778 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG,
779 (MVT::SimpleValueType)VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]780 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG,
781 (MVT::SimpleValueType)VT, Expand);
782 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]783 }
784
785 // Most targets ignore the @llvm.prefetch intrinsic.
786 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
787
788 // ConstantFP nodes default to expand. Targets can either change this to
789 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
790 // to optimize expansions for certain constants.
791 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
792 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
793 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
794 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
795 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
796
797 // These library functions default to expand.
798 setOperationAction(ISD::FLOG , MVT::f16, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
801 setOperationAction(ISD::FEXP , MVT::f16, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
803 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]804 setOperationAction(ISD::FMINNUM, MVT::f16, Expand);
805 setOperationAction(ISD::FMAXNUM, MVT::f16, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]806 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
807 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
808 setOperationAction(ISD::FRINT, MVT::f16, Expand);
809 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]810 setOperationAction(ISD::FROUND, MVT::f16, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]811 setOperationAction(ISD::FLOG , MVT::f32, Expand);
812 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
813 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
814 setOperationAction(ISD::FEXP , MVT::f32, Expand);
815 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
816 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]817 setOperationAction(ISD::FMINNUM, MVT::f32, Expand);
818 setOperationAction(ISD::FMAXNUM, MVT::f32, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]819 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
820 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
821 setOperationAction(ISD::FRINT, MVT::f32, Expand);
822 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]823 setOperationAction(ISD::FROUND, MVT::f32, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]824 setOperationAction(ISD::FLOG , MVT::f64, Expand);
825 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
826 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
827 setOperationAction(ISD::FEXP , MVT::f64, Expand);
828 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
829 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]830 setOperationAction(ISD::FMINNUM, MVT::f64, Expand);
831 setOperationAction(ISD::FMAXNUM, MVT::f64, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]832 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
833 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
834 setOperationAction(ISD::FRINT, MVT::f64, Expand);
835 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]836 setOperationAction(ISD::FROUND, MVT::f64, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]837 setOperationAction(ISD::FLOG , MVT::f128, Expand);
838 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
839 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
840 setOperationAction(ISD::FEXP , MVT::f128, Expand);
841 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
842 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]843 setOperationAction(ISD::FMINNUM, MVT::f128, Expand);
844 setOperationAction(ISD::FMAXNUM, MVT::f128, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]845 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
846 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
847 setOperationAction(ISD::FRINT, MVT::f128, Expand);
848 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]849 setOperationAction(ISD::FROUND, MVT::f128, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]850
851 // Default ISD::TRAP to expand (which turns it into abort).
852 setOperationAction(ISD::TRAP, MVT::Other, Expand);
853
854 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
855 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
856 //
857 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]858}
859
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]860MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
861 return MVT::getIntegerVT(getPointerSizeInBits(AS));
862}
863
864unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]865 return DL->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]866}
867
868unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
869 assert(Ty->isPointerTy());
870 return getPointerSizeInBits(Ty->getPointerAddressSpace());
871}
872
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]873MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]874 return MVT::getIntegerVT(8*DL->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]875}
876
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]877EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
878 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
879 if (LHSTy.isVector())
880 return LHSTy;
881 return getScalarShiftAmountTy(LHSTy);
882}
883
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]884/// canOpTrap - Returns true if the operation can trap for the value type.
885/// VT must be a legal type.
886bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
887 assert(isTypeLegal(VT));
888 switch (Op) {
889 default:
890 return false;
891 case ISD::FDIV:
892 case ISD::FREM:
893 case ISD::SDIV:
894 case ISD::UDIV:
895 case ISD::SREM:
896 case ISD::UREM:
897 return true;
898 }
899}
900
901
902static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
903 unsigned &NumIntermediates,
904 MVT &RegisterVT,
905 TargetLoweringBase *TLI) {
906 // Figure out the right, legal destination reg to copy into.
907 unsigned NumElts = VT.getVectorNumElements();
908 MVT EltTy = VT.getVectorElementType();
909
910 unsigned NumVectorRegs = 1;
911
912 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
913 // could break down into LHS/RHS like LegalizeDAG does.
914 if (!isPowerOf2_32(NumElts)) {
915 NumVectorRegs = NumElts;
916 NumElts = 1;
917 }
918
919 // Divide the input until we get to a supported size. This will always
920 // end with a scalar if the target doesn't support vectors.
921 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
922 NumElts >>= 1;
923 NumVectorRegs <<= 1;
924 }
925
926 NumIntermediates = NumVectorRegs;
927
928 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
929 if (!TLI->isTypeLegal(NewVT))
930 NewVT = EltTy;
931 IntermediateVT = NewVT;
932
933 unsigned NewVTSize = NewVT.getSizeInBits();
934
935 // Convert sizes such as i33 to i64.
936 if (!isPowerOf2_32(NewVTSize))
937 NewVTSize = NextPowerOf2(NewVTSize);
938
939 MVT DestVT = TLI->getRegisterType(NewVT);
940 RegisterVT = DestVT;
941 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
942 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
943
944 // Otherwise, promotion or legal types use the same number of registers as
945 // the vector decimated to the appropriate level.
946 return NumVectorRegs;
947}
948
949/// isLegalRC - Return true if the value types that can be represented by the
950/// specified register class are all legal.
951bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
952 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
953 I != E; ++I) {
954 if (isTypeLegal(*I))
955 return true;
956 }
957 return false;
958}
959
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]960/// Replace/modify any TargetFrameIndex operands with a targte-dependent
961/// sequence of memory operands that is recognized by PrologEpilogInserter.
962MachineBasicBlock*
963TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
964 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]965 MachineFunction &MF = *MI->getParent()->getParent();
966
967 // MI changes inside this loop as we grow operands.
968 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
969 MachineOperand &MO = MI->getOperand(OperIdx);
970 if (!MO.isFI())
971 continue;
972
973 // foldMemoryOperand builds a new MI after replacing a single FI operand
974 // with the canonical set of five x86 addressing-mode operands.
975 int FI = MO.getIndex();
976 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
977
978 // Copy operands before the frame-index.
979 for (unsigned i = 0; i < OperIdx; ++i)
980 MIB.addOperand(MI->getOperand(i));
981 // Add frame index operands: direct-mem-ref tag, #FI, offset.
982 MIB.addImm(StackMaps::DirectMemRefOp);
983 MIB.addOperand(MI->getOperand(OperIdx));
984 MIB.addImm(0);
985 // Copy the operands after the frame index.
986 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
987 MIB.addOperand(MI->getOperand(i));
988
989 // Inherit previous memory operands.
990 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
991 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
992
993 // Add a new memory operand for this FI.
994 const MachineFrameInfo &MFI = *MF.getFrameInfo();
995 assert(MFI.getObjectOffset(FI) != -1);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]996 MachineMemOperand *MMO = MF.getMachineMemOperand(
997 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
998 TM.getSubtargetImpl()->getDataLayout()->getPointerSize(),
999 MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1000 MIB->addMemOperand(MF, MMO);
1001
1002 // Replace the instruction and update the operand index.
1003 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1004 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1005 MI->eraseFromParent();
1006 MI = MIB;
1007 }
1008 return MBB;
1009}
1010
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1011/// findRepresentativeClass - Return the largest legal super-reg register class
1012/// of the register class for the specified type and its associated "cost".
1013std::pair<const TargetRegisterClass*, uint8_t>
1014TargetLoweringBase::findRepresentativeClass(MVT VT) const {
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1015 const TargetRegisterInfo *TRI =
1016 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1017 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1018 if (!RC)
1019 return std::make_pair(RC, 0);
1020
1021 // Compute the set of all super-register classes.
1022 BitVector SuperRegRC(TRI->getNumRegClasses());
1023 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1024 SuperRegRC.setBitsInMask(RCI.getMask());
1025
1026 // Find the first legal register class with the largest spill size.
1027 const TargetRegisterClass *BestRC = RC;
1028 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1029 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1030 // We want the largest possible spill size.
1031 if (SuperRC->getSize() <= BestRC->getSize())
1032 continue;
1033 if (!isLegalRC(SuperRC))
1034 continue;
1035 BestRC = SuperRC;
1036 }
1037 return std::make_pair(BestRC, 1);
1038}
1039
1040/// computeRegisterProperties - Once all of the register classes are added,
1041/// this allows us to compute derived properties we expose.
1042void TargetLoweringBase::computeRegisterProperties() {
1043 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1044 "Too many value types for ValueTypeActions to hold!");
1045
1046 // Everything defaults to needing one register.
1047 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1048 NumRegistersForVT[i] = 1;
1049 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1050 }
1051 // ...except isVoid, which doesn't need any registers.
1052 NumRegistersForVT[MVT::isVoid] = 0;
1053
1054 // Find the largest integer register class.
1055 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1056 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1057 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1058
1059 // Every integer value type larger than this largest register takes twice as
1060 // many registers to represent as the previous ValueType.
1061 for (unsigned ExpandedReg = LargestIntReg + 1;
1062 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1063 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1064 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1065 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1066 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1067 TypeExpandInteger);
1068 }
1069
1070 // Inspect all of the ValueType's smaller than the largest integer
1071 // register to see which ones need promotion.
1072 unsigned LegalIntReg = LargestIntReg;
1073 for (unsigned IntReg = LargestIntReg - 1;
1074 IntReg >= (unsigned)MVT::i1; --IntReg) {
1075 MVT IVT = (MVT::SimpleValueType)IntReg;
1076 if (isTypeLegal(IVT)) {
1077 LegalIntReg = IntReg;
1078 } else {
1079 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1080 (const MVT::SimpleValueType)LegalIntReg;
1081 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1082 }
1083 }
1084
1085 // ppcf128 type is really two f64's.
1086 if (!isTypeLegal(MVT::ppcf128)) {
1087 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1088 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1089 TransformToType[MVT::ppcf128] = MVT::f64;
1090 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1091 }
1092
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1093 // Decide how to handle f128. If the target does not have native f128 support,
1094 // expand it to i128 and we will be generating soft float library calls.
1095 if (!isTypeLegal(MVT::f128)) {
1096 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1097 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1098 TransformToType[MVT::f128] = MVT::i128;
1099 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1100 }
1101
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1102 // Decide how to handle f64. If the target does not have native f64 support,
1103 // expand it to i64 and we will be generating soft float library calls.
1104 if (!isTypeLegal(MVT::f64)) {
1105 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1106 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1107 TransformToType[MVT::f64] = MVT::i64;
1108 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1109 }
1110
1111 // Decide how to handle f32. If the target does not have native support for
1112 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1113 if (!isTypeLegal(MVT::f32)) {
1114 if (isTypeLegal(MVT::f64)) {
1115 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1116 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1117 TransformToType[MVT::f32] = MVT::f64;
1118 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1119 } else {
1120 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1121 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1122 TransformToType[MVT::f32] = MVT::i32;
1123 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1124 }
1125 }
1126
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1127 if (!isTypeLegal(MVT::f16)) {
1128 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1129 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1130 TransformToType[MVT::f16] = MVT::i16;
1131 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1132 }
1133
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1134 // Loop over all of the vector value types to see which need transformations.
1135 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1136 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1137 MVT VT = (MVT::SimpleValueType) i;
1138 if (isTypeLegal(VT))
1139 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1140
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1141 MVT EltVT = VT.getVectorElementType();
1142 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1143 bool IsLegalWiderType = false;
1144 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1145 switch (PreferredAction) {
1146 case TypePromoteInteger: {
1147 // Try to promote the elements of integer vectors. If no legal
1148 // promotion was found, fall through to the widen-vector method.
1149 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1150 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1151 // Promote vectors of integers to vectors with the same number
1152 // of elements, with a wider element type.
1153 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1154 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1155 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1156 TransformToType[i] = SVT;
1157 RegisterTypeForVT[i] = SVT;
1158 NumRegistersForVT[i] = 1;
1159 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1160 IsLegalWiderType = true;
1161 break;
1162 }
1163 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1164 if (IsLegalWiderType)
1165 break;
1166 }
1167 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1168 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1169 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1170 MVT SVT = (MVT::SimpleValueType) nVT;
1171 if (SVT.getVectorElementType() == EltVT
1172 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1173 TransformToType[i] = SVT;
1174 RegisterTypeForVT[i] = SVT;
1175 NumRegistersForVT[i] = 1;
1176 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1177 IsLegalWiderType = true;
1178 break;
1179 }
1180 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1181 if (IsLegalWiderType)
1182 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1183 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1184 case TypeSplitVector:
1185 case TypeScalarizeVector: {
1186 MVT IntermediateVT;
1187 MVT RegisterVT;
1188 unsigned NumIntermediates;
1189 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1190 NumIntermediates, RegisterVT, this);
1191 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1192
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1193 MVT NVT = VT.getPow2VectorType();
1194 if (NVT == VT) {
1195 // Type is already a power of 2. The default action is to split.
1196 TransformToType[i] = MVT::Other;
1197 if (PreferredAction == TypeScalarizeVector)
1198 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1199 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1200 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1201 else
1202 // Set type action according to the number of elements.
1203 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1204 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1205 } else {
1206 TransformToType[i] = NVT;
1207 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1208 }
1209 break;
1210 }
1211 default:
1212 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1213 }
1214 }
1215
1216 // Determine the 'representative' register class for each value type.
1217 // An representative register class is the largest (meaning one which is
1218 // not a sub-register class / subreg register class) legal register class for
1219 // a group of value types. For example, on i386, i8, i16, and i32
1220 // representative would be GR32; while on x86_64 it's GR64.
1221 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1222 const TargetRegisterClass* RRC;
1223 uint8_t Cost;
Benjamin Kramerd6f1f842014-03-02 13:30:33 +0000[diff] [blame]1224 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1225 RepRegClassForVT[i] = RRC;
1226 RepRegClassCostForVT[i] = Cost;
1227 }
1228}
1229
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1230EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1231 assert(!VT.isVector() && "No default SetCC type for vectors!");
1232 return getPointerTy(0).SimpleTy;
1233}
1234
1235MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1236 return MVT::i32; // return the default value
1237}
1238
1239/// getVectorTypeBreakdown - Vector types are broken down into some number of
1240/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1241/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1242/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1243///
1244/// This method returns the number of registers needed, and the VT for each
1245/// register. It also returns the VT and quantity of the intermediate values
1246/// before they are promoted/expanded.
1247///
1248unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1249 EVT &IntermediateVT,
1250 unsigned &NumIntermediates,
1251 MVT &RegisterVT) const {
1252 unsigned NumElts = VT.getVectorNumElements();
1253
1254 // If there is a wider vector type with the same element type as this one,
1255 // or a promoted vector type that has the same number of elements which
1256 // are wider, then we should convert to that legal vector type.
1257 // This handles things like <2 x float> -> <4 x float> and
1258 // <4 x i1> -> <4 x i32>.
1259 LegalizeTypeAction TA = getTypeAction(Context, VT);
1260 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1261 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1262 if (isTypeLegal(RegisterEVT)) {
1263 IntermediateVT = RegisterEVT;
1264 RegisterVT = RegisterEVT.getSimpleVT();
1265 NumIntermediates = 1;
1266 return 1;
1267 }
1268 }
1269
1270 // Figure out the right, legal destination reg to copy into.
1271 EVT EltTy = VT.getVectorElementType();
1272
1273 unsigned NumVectorRegs = 1;
1274
1275 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1276 // could break down into LHS/RHS like LegalizeDAG does.
1277 if (!isPowerOf2_32(NumElts)) {
1278 NumVectorRegs = NumElts;
1279 NumElts = 1;
1280 }
1281
1282 // Divide the input until we get to a supported size. This will always
1283 // end with a scalar if the target doesn't support vectors.
1284 while (NumElts > 1 && !isTypeLegal(
1285 EVT::getVectorVT(Context, EltTy, NumElts))) {
1286 NumElts >>= 1;
1287 NumVectorRegs <<= 1;
1288 }
1289
1290 NumIntermediates = NumVectorRegs;
1291
1292 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1293 if (!isTypeLegal(NewVT))
1294 NewVT = EltTy;
1295 IntermediateVT = NewVT;
1296
1297 MVT DestVT = getRegisterType(Context, NewVT);
1298 RegisterVT = DestVT;
1299 unsigned NewVTSize = NewVT.getSizeInBits();
1300
1301 // Convert sizes such as i33 to i64.
1302 if (!isPowerOf2_32(NewVTSize))
1303 NewVTSize = NextPowerOf2(NewVTSize);
1304
1305 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1306 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1307
1308 // Otherwise, promotion or legal types use the same number of registers as
1309 // the vector decimated to the appropriate level.
1310 return NumVectorRegs;
1311}
1312
1313/// Get the EVTs and ArgFlags collections that represent the legalized return
1314/// type of the given function. This does not require a DAG or a return value,
1315/// and is suitable for use before any DAGs for the function are constructed.
1316/// TODO: Move this out of TargetLowering.cpp.
1317void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1318 SmallVectorImpl<ISD::OutputArg> &Outs,
1319 const TargetLowering &TLI) {
1320 SmallVector<EVT, 4> ValueVTs;
1321 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1322 unsigned NumValues = ValueVTs.size();
1323 if (NumValues == 0) return;
1324
1325 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1326 EVT VT = ValueVTs[j];
1327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1328
1329 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1330 ExtendKind = ISD::SIGN_EXTEND;
1331 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1332 ExtendKind = ISD::ZERO_EXTEND;
1333
1334 // FIXME: C calling convention requires the return type to be promoted to
1335 // at least 32-bit. But this is not necessary for non-C calling
1336 // conventions. The frontend should mark functions whose return values
1337 // require promoting with signext or zeroext attributes.
1338 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1339 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1340 if (VT.bitsLT(MinVT))
1341 VT = MinVT;
1342 }
1343
1344 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1345 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1346
1347 // 'inreg' on function refers to return value
1348 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1349 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1350 Flags.setInReg();
1351
1352 // Propagate extension type if any
1353 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1354 Flags.setSExt();
1355 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1356 Flags.setZExt();
1357
1358 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1359 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1360 }
1361}
1362
1363/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1364/// function arguments in the caller parameter area. This is the actual
1365/// alignment, not its logarithm.
1366unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]1367 return DL->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1368}
1369
1370//===----------------------------------------------------------------------===//
1371// TargetTransformInfo Helpers
1372//===----------------------------------------------------------------------===//
1373
1374int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1375 enum InstructionOpcodes {
1376#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1377#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1378#include "llvm/IR/Instruction.def"
1379 };
1380 switch (static_cast<InstructionOpcodes>(Opcode)) {
1381 case Ret: return 0;
1382 case Br: return 0;
1383 case Switch: return 0;
1384 case IndirectBr: return 0;
1385 case Invoke: return 0;
1386 case Resume: return 0;
1387 case Unreachable: return 0;
1388 case Add: return ISD::ADD;
1389 case FAdd: return ISD::FADD;
1390 case Sub: return ISD::SUB;
1391 case FSub: return ISD::FSUB;
1392 case Mul: return ISD::MUL;
1393 case FMul: return ISD::FMUL;
1394 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1395 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1396 case FDiv: return ISD::FDIV;
1397 case URem: return ISD::UREM;
1398 case SRem: return ISD::SREM;
1399 case FRem: return ISD::FREM;
1400 case Shl: return ISD::SHL;
1401 case LShr: return ISD::SRL;
1402 case AShr: return ISD::SRA;
1403 case And: return ISD::AND;
1404 case Or: return ISD::OR;
1405 case Xor: return ISD::XOR;
1406 case Alloca: return 0;
1407 case Load: return ISD::LOAD;
1408 case Store: return ISD::STORE;
1409 case GetElementPtr: return 0;
1410 case Fence: return 0;
1411 case AtomicCmpXchg: return 0;
1412 case AtomicRMW: return 0;
1413 case Trunc: return ISD::TRUNCATE;
1414 case ZExt: return ISD::ZERO_EXTEND;
1415 case SExt: return ISD::SIGN_EXTEND;
1416 case FPToUI: return ISD::FP_TO_UINT;
1417 case FPToSI: return ISD::FP_TO_SINT;
1418 case UIToFP: return ISD::UINT_TO_FP;
1419 case SIToFP: return ISD::SINT_TO_FP;
1420 case FPTrunc: return ISD::FP_ROUND;
1421 case FPExt: return ISD::FP_EXTEND;
1422 case PtrToInt: return ISD::BITCAST;
1423 case IntToPtr: return ISD::BITCAST;
1424 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1425 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1426 case ICmp: return ISD::SETCC;
1427 case FCmp: return ISD::SETCC;
1428 case PHI: return 0;
1429 case Call: return 0;
1430 case Select: return ISD::SELECT;
1431 case UserOp1: return 0;
1432 case UserOp2: return 0;
1433 case VAArg: return 0;
1434 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1435 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1436 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1437 case ExtractValue: return ISD::MERGE_VALUES;
1438 case InsertValue: return ISD::MERGE_VALUES;
1439 case LandingPad: return 0;
1440 }
1441
1442 llvm_unreachable("Unknown instruction type encountered!");
1443}
1444
1445std::pair<unsigned, MVT>
1446TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1447 LLVMContext &C = Ty->getContext();
1448 EVT MTy = getValueType(Ty);
1449
1450 unsigned Cost = 1;
1451 // We keep legalizing the type until we find a legal kind. We assume that
1452 // the only operation that costs anything is the split. After splitting
1453 // we need to handle two types.
1454 while (true) {
1455 LegalizeKind LK = getTypeConversion(C, MTy);
1456
1457 if (LK.first == TypeLegal)
1458 return std::make_pair(Cost, MTy.getSimpleVT());
1459
1460 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1461 Cost *= 2;
1462
1463 // Keep legalizing the type.
1464 MTy = LK.second;
1465 }
1466}
1467
1468//===----------------------------------------------------------------------===//
1469// Loop Strength Reduction hooks
1470//===----------------------------------------------------------------------===//
1471
1472/// isLegalAddressingMode - Return true if the addressing mode represented
1473/// by AM is legal for this target, for a load/store of the specified type.
1474bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1475 Type *Ty) const {
1476 // The default implementation of this implements a conservative RISCy, r+r and
1477 // r+i addr mode.
1478
1479 // Allows a sign-extended 16-bit immediate field.
1480 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1481 return false;
1482
1483 // No global is ever allowed as a base.
1484 if (AM.BaseGV)
1485 return false;
1486
1487 // Only support r+r,
1488 switch (AM.Scale) {
1489 case 0: // "r+i" or just "i", depending on HasBaseReg.
1490 break;
1491 case 1:
1492 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1493 return false;
1494 // Otherwise we have r+r or r+i.
1495 break;
1496 case 2:
1497 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1498 return false;
1499 // Allow 2*r as r+r.
1500 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1501 default: // Don't allow n * r
1502 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1503 }
1504
1505 return true;
1506}