Blame - llvm/lib/Target/R600/AMDGPU.td - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- AMDIL.td - AMDIL Tablegen files --- tablegen --------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//==-----------------------------------------------------------------------===//
				9
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	10	include "llvm/Target/Target.td"
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	11
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	12	//===----------------------------------------------------------------------===//
				13	// Subtarget Features
				14	//===----------------------------------------------------------------------===//
				15
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	16	// Debugging Features
				17
				18	def FeatureDumpCode : SubtargetFeature <"DumpCode",
				19	"DumpCode",
				20	"true",
				21	"Dump MachineInstrs in the CodeEmitter">;
				22
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	23	def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	24	"EnableIRStructurizer",
Tom Stellard	66df8a2	2013-11-18 19:43:44 +0000	[diff] [blame]	25	"false",
				26	"Disable IR Structurizer">;
Tom Stellard	ed0ceec	2013-10-10 17:11:12 +0000	[diff] [blame]	27
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	28	// Target features
				29
Tom Stellard	783893a	2013-11-18 19:43:33 +0000	[diff] [blame]	30	def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
				31	"EnableIfCvt",
				32	"false",
				33	"Disable the if conversion pass">;
				34
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	35	def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	36	"FP64",
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	37	"true",
				38	"Enable 64bit double precision operations">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	39
				40	def Feature64BitPtr : SubtargetFeature<"64BitPtr",
				41	"Is64bit",
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	42	"true",
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	43	"Specify if 64bit addressing should be used.">;
				44
				45	def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
				46	"Is32on64bit",
				47	"false",
				48	"Specify if 64bit sized pointers with 32bit addressing should be used.">;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	49
				50	def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
				51	"R600ALUInst",
				52	"false",
				53	"Older version of ALU instructions encoding.">;
				54
				55	def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
				56	"HasVertexCache",
				57	"true",
				58	"Specify use of dedicated vertex cache.">;
				59
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	60	def FeatureCaymanISA : SubtargetFeature<"caymanISA",
				61	"CaymanISA",
				62	"true",
				63	"Use Cayman ISA">;
				64
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	65	def FeatureCFALUBug : SubtargetFeature<"cfalubug",
				66	"CFALUBug",
				67	"true",
				68	"GPU has CF_ALU bug">;
				69
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	70	class SubtargetFeatureFetchLimit <string Value> :
				71	SubtargetFeature <"fetch"#Value,
				72	"TexVTXClauseSize",
				73	Value,
				74	"Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard	9979277	2013-06-07 20:28:49 +0000	[diff] [blame]	75
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	76	def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
				77	def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
				78
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	79	class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
				80	"wavefrontsize"#Value,
				81	"WavefrontSize",
				82	!cast<string>(Value),
				83	"The number of threads per wavefront">;
				84
				85	def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
				86	def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
				87	def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
				88
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	89	class SubtargetFeatureGeneration <string Value,
				90	list<SubtargetFeature> Implies> :
				91	SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
				92	Value#" GPU generation", Implies>;
				93
				94	def FeatureR600 : SubtargetFeatureGeneration<"R600",
				95	[FeatureR600ALUInst, FeatureFetchLimit8]>;
				96
				97	def FeatureR700 : SubtargetFeatureGeneration<"R700",
				98	[FeatureFetchLimit16]>;
				99
				100	def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
				101	[FeatureFetchLimit16]>;
				102
				103	def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	104	[FeatureFetchLimit16, FeatureWavefrontSize64]>;
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	105
				106	def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
				107	[Feature64BitPtr, FeatureFP64]>;
				108
Tom Stellard	6e1ee47	2013-10-29 16:37:28 +0000	[diff] [blame]	109	def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
				110	[Feature64BitPtr, FeatureFP64]>;
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	111	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	112
				113	def AMDGPUInstrInfo : InstrInfo {
				114	let guessInstructionProperties = 1;
				115	}
				116
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	117	def AMDGPU : Target {
				118	// Pull in Instruction Info:
				119	let InstructionSet = AMDGPUInstrInfo;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	120	}
				121
Tom Stellard	bc5b537	2014-06-13 16:38:59 +0000	[diff] [blame]	122	// Dummy Instruction itineraries for pseudo instructions
				123	def ALU_NULL : FuncUnit;
				124	def NullALU : InstrItinClass;
				125
Tom Stellard	0e70de5	2014-05-16 20:56:45 +0000	[diff] [blame]	126	//===----------------------------------------------------------------------===//
				127	// Predicate helper class
				128	//===----------------------------------------------------------------------===//
				129
				130	class PredicateControl {
				131	Predicate SubtargetPredicate;
				132	list<Predicate> OtherPredicates = [];
				133	list<Predicate> Predicates = !listconcat([SubtargetPredicate],
				134	OtherPredicates);
				135	}
				136
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	137	// Include AMDGPU TD files
				138	include "R600Schedule.td"
				139	include "SISchedule.td"
				140	include "Processors.td"
				141	include "AMDGPUInstrInfo.td"
				142	include "AMDGPUIntrinsics.td"
				143	include "AMDGPURegisterInfo.td"
				144	include "AMDGPUInstructions.td"
Christian Konig	2c8f6d5	2013-03-07 09:03:52 +0000	[diff] [blame]	145	include "AMDGPUCallingConv.td"