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gerrit-public.fairphone.software / toolchain / llvm-project / 8761a8f5c0edcc02e2904d646cb0b5ed73d991b5 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: ed90a4bca3ba3443c72ec3ea747df2b8501d3339 [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]394def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
398
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]399multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
409}
410
411defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
413 VEX_W;
414
415def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
417
418def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
420
421def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
424 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]425def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
426 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]427
428multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
429 X86MemOperand x86memop, PatFrag ld_frag,
430 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
431 RegisterClass KRC> {
432 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
434 [(set DstRC:$dst,
435 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
436 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
437 VR128X:$src),
438 !strconcat(OpcodeStr,
439 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
440 [(set DstRC:$dst,
441 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
442 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]443 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]444 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
446 [(set DstRC:$dst,
447 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
448 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
449 x86memop:$src),
450 !strconcat(OpcodeStr,
451 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
452 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
453 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]454 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]455}
456
457defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
458 loadi32, VR512, v16i32, v4i32, VK16WM>,
459 EVEX_V512, EVEX_CD8<32, CD8VT1>;
460defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
461 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
462 EVEX_CD8<64, CD8VT1>;
463
464def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
465 (VBROADCASTSSZrr VR128X:$src)>;
466def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
467 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame^]468
469def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
470 (VBROADCASTSSZrr VR128X:$src)>;
471def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
472 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]473
474// Provide fallback in case the load node that is used in the patterns above
475// is used by additional users, which prevents the pattern selection.
476def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
477 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
478def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
479 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
480
481
482let Predicates = [HasAVX512] in {
483def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
484 (EXTRACT_SUBREG
485 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
486 addr:$src)), sub_ymm)>;
487}
488//===----------------------------------------------------------------------===//
489// AVX-512 BROADCAST MASK TO VECTOR REGISTER
490//---
491
492multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
493 RegisterClass DstRC, RegisterClass KRC,
494 ValueType OpVT, ValueType SrcVT> {
495def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
497 []>, EVEX;
498}
499
500defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
501 VK16, v16i32, v16i1>, EVEX_V512;
502defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
503 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
504
505//===----------------------------------------------------------------------===//
506// AVX-512 - VPERM
507//
508// -- immediate form --
509multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
510 SDNode OpNode, PatFrag mem_frag,
511 X86MemOperand x86memop, ValueType OpVT> {
512 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
513 (ins RC:$src1, i8imm:$src2),
514 !strconcat(OpcodeStr,
515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
516 [(set RC:$dst,
517 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
518 EVEX;
519 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
520 (ins x86memop:$src1, i8imm:$src2),
521 !strconcat(OpcodeStr,
522 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
523 [(set RC:$dst,
524 (OpVT (OpNode (mem_frag addr:$src1),
525 (i8 imm:$src2))))]>, EVEX;
526}
527
528defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
529 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
530let ExeDomain = SSEPackedDouble in
531defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
532 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
533
534// -- VPERM - register form --
535multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
536 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
537
538 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
539 (ins RC:$src1, RC:$src2),
540 !strconcat(OpcodeStr,
541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
542 [(set RC:$dst,
543 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
544
545 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
546 (ins RC:$src1, x86memop:$src2),
547 !strconcat(OpcodeStr,
548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
549 [(set RC:$dst,
550 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
551 EVEX_4V;
552}
553
554defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
555 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
556defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
557 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
558let ExeDomain = SSEPackedSingle in
559defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
560 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
561let ExeDomain = SSEPackedDouble in
562defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
563 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
564
565// -- VPERM2I - 3 source operands form --
566multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
567 PatFrag mem_frag, X86MemOperand x86memop,
568 ValueType OpVT> {
569let Constraints = "$src1 = $dst" in {
570 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
571 (ins RC:$src1, RC:$src2, RC:$src3),
572 !strconcat(OpcodeStr,
573 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
574 [(set RC:$dst,
575 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
576 EVEX_4V;
577
578 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
579 (ins RC:$src1, RC:$src2, x86memop:$src3),
580 !strconcat(OpcodeStr,
581 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
582 [(set RC:$dst,
583 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
584 (mem_frag addr:$src3))))]>, EVEX_4V;
585 }
586}
587defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
588 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
589defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
590 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
591defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
592 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
593defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
594 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
595
596//===----------------------------------------------------------------------===//
597// AVX-512 - BLEND using mask
598//
599multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
600 RegisterClass KRC, RegisterClass RC,
601 X86MemOperand x86memop, PatFrag mem_frag,
602 SDNode OpNode, ValueType vt> {
603 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
604 (ins KRC:$mask, RC:$src1, RC:$src2),
605 !strconcat(OpcodeStr,
606 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
607 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
608 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
609
610 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
611 (ins KRC:$mask, RC:$src1, x86memop:$src2),
612 !strconcat(OpcodeStr,
613 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
614 []>,
615 EVEX_4V, EVEX_K;
616}
617
618let ExeDomain = SSEPackedSingle in
619defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
620 memopv16f32, vselect, v16f32>,
621 EVEX_CD8<32, CD8VF>, EVEX_V512;
622let ExeDomain = SSEPackedDouble in
623defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
624 memopv8f64, vselect, v8f64>,
625 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
626
627defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
628 memopv8i64, vselect, v16i32>,
629 EVEX_CD8<32, CD8VF>, EVEX_V512;
630
631defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
632 memopv8i64, vselect, v8i64>, VEX_W,
633 EVEX_CD8<64, CD8VF>, EVEX_V512;
634
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]635let Predicates = [HasAVX512] in {
636def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
637 (v8f32 VR256X:$src2))),
638 (EXTRACT_SUBREG
639 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
640 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
641 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
642
643def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
644 (v8i32 VR256X:$src2))),
645 (EXTRACT_SUBREG
646 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
647 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
648 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
649}
650
651multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
652 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
653 SDNode OpNode, ValueType vt> {
654 def rr : AVX512BI<opc, MRMSrcReg,
655 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
657 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
658 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
659 def rm : AVX512BI<opc, MRMSrcMem,
660 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
662 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
663 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
664}
665
666defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
667 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
668defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
669 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
670
671defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
672 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
673defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
674 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
675
676def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
677 (COPY_TO_REGCLASS (VPCMPGTDZrr
678 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
679 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
680
681def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
682 (COPY_TO_REGCLASS (VPCMPEQDZrr
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
685
686multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
687 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
688 SDNode OpNode, ValueType vt, Operand CC, string asm,
689 string asm_alt> {
690 def rri : AVX512AIi8<opc, MRMSrcReg,
691 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
692 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
693 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
694 def rmi : AVX512AIi8<opc, MRMSrcMem,
695 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
696 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
697 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
698 // Accept explicit immediate argument form instead of comparison code.
699 let neverHasSideEffects = 1 in {
700 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
701 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
702 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
703 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
704 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
706 }
707}
708
709defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
710 X86cmpm, v16i32, AVXCC,
711 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
712 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
713 EVEX_V512, EVEX_CD8<32, CD8VF>;
714defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
715 X86cmpmu, v16i32, AVXCC,
716 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
717 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
718 EVEX_V512, EVEX_CD8<32, CD8VF>;
719
720defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
721 X86cmpm, v8i64, AVXCC,
722 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
723 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
724 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
725defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
726 X86cmpmu, v8i64, AVXCC,
727 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
728 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
729 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
730
731// avx512_cmp_packed - sse 1 & 2 compare packed instructions
732multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
733 X86MemOperand x86memop, Operand CC,
734 SDNode OpNode, ValueType vt, string asm,
735 string asm_alt, Domain d> {
736 def rri : AVX512PIi8<0xC2, MRMSrcReg,
737 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
738 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
739 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
740 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
741 [(set KRC:$dst,
742 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
743
744 // Accept explicit immediate argument form instead of comparison code.
745 let neverHasSideEffects = 1 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]746 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]747 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]748 asm_alt, [], d>;
749 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]750 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]751 asm_alt, [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]752 }
753}
754
755defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
756 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]758 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]759defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
760 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
761 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]762 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]763 EVEX_CD8<64, CD8VF>;
764
765def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
766 (COPY_TO_REGCLASS (VCMPPSZrri
767 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
768 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
769 imm:$cc), VK8)>;
770def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
771 (COPY_TO_REGCLASS (VPCMPDZrri
772 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
773 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
774 imm:$cc), VK8)>;
775def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
776 (COPY_TO_REGCLASS (VPCMPUDZrri
777 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
778 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
779 imm:$cc), VK8)>;
780
781// Mask register copy, including
782// - copy between mask registers
783// - load/store mask registers
784// - copy from GPR to mask register and vice versa
785//
786multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
787 string OpcodeStr, RegisterClass KRC,
788 ValueType vt, X86MemOperand x86memop> {
789 let neverHasSideEffects = 1 in {
790 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
791 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
792 let mayLoad = 1 in
793 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
795 [(set KRC:$dst, (vt (load addr:$src)))]>;
796 let mayStore = 1 in
797 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
799 }
800}
801
802multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
803 string OpcodeStr,
804 RegisterClass KRC, RegisterClass GRC> {
805 let neverHasSideEffects = 1 in {
806 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
808 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
809 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
810 }
811}
812
813let Predicates = [HasAVX512] in {
814 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
815 VEX, TB;
816 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
817 VEX, TB;
818}
819
820let Predicates = [HasAVX512] in {
821 // GR16 from/to 16-bit mask
822 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
823 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
824 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
825 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
826
827 // Store kreg in memory
828 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
829 (KMOVWmk addr:$dst, VK16:$src)>;
830
831 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
832 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
833}
834// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
835let Predicates = [HasAVX512] in {
836 // GR from/to 8-bit mask without native support
837 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
838 (COPY_TO_REGCLASS
839 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
840 VK8)>;
841 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
842 (EXTRACT_SUBREG
843 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
844 sub_8bit)>;
845}
846
847// Mask unary operation
848// - KNOT
849multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
850 RegisterClass KRC, SDPatternOperator OpNode> {
851 let Predicates = [HasAVX512] in
852 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
853 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
854 [(set KRC:$dst, (OpNode KRC:$src))]>;
855}
856
857multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
858 SDPatternOperator OpNode> {
859 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
860 VEX, TB;
861}
862
863defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
864
865def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
866def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
867 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
868
869// With AVX-512, 8-bit mask is promoted to 16-bit mask.
870def : Pat<(not VK8:$src),
871 (COPY_TO_REGCLASS
872 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
873
874// Mask binary operation
875// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
876multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
877 RegisterClass KRC, SDPatternOperator OpNode> {
878 let Predicates = [HasAVX512] in
879 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
880 !strconcat(OpcodeStr,
881 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
882 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
883}
884
885multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
886 SDPatternOperator OpNode> {
887 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
888 VEX_4V, VEX_L, TB;
889}
890
891def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
892def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
893
894let isCommutable = 1 in {
895 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
896 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
897 let isCommutable = 0 in
898 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
899 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
900 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
901 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
902}
903
904multiclass avx512_mask_binop_int<string IntName, string InstName> {
905 let Predicates = [HasAVX512] in
906 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
907 VK16:$src1, VK16:$src2),
908 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
909}
910
911defm : avx512_mask_binop_int<"kadd", "KADD">;
912defm : avx512_mask_binop_int<"kand", "KAND">;
913defm : avx512_mask_binop_int<"kandn", "KANDN">;
914defm : avx512_mask_binop_int<"kor", "KOR">;
915defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
916defm : avx512_mask_binop_int<"kxor", "KXOR">;
917// With AVX-512, 8-bit mask is promoted to 16-bit mask.
918multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
919 let Predicates = [HasAVX512] in
920 def : Pat<(OpNode VK8:$src1, VK8:$src2),
921 (COPY_TO_REGCLASS
922 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
923 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
924}
925
926defm : avx512_binop_pat<and, KANDWrr>;
927defm : avx512_binop_pat<andn, KANDNWrr>;
928defm : avx512_binop_pat<or, KORWrr>;
929defm : avx512_binop_pat<xnor, KXNORWrr>;
930defm : avx512_binop_pat<xor, KXORWrr>;
931
932// Mask unpacking
933multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
934 RegisterClass KRC1, RegisterClass KRC2> {
935 let Predicates = [HasAVX512] in
936 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
937 !strconcat(OpcodeStr,
938 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
939}
940
941multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
942 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
943 VEX_4V, VEX_L, OpSize, TB;
944}
945
946defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
947
948multiclass avx512_mask_unpck_int<string IntName, string InstName> {
949 let Predicates = [HasAVX512] in
950 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
951 VK8:$src1, VK8:$src2),
952 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
953}
954
955defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
956// Mask bit testing
957multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
958 SDNode OpNode> {
959 let Predicates = [HasAVX512], Defs = [EFLAGS] in
960 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
961 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
962 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
963}
964
965multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
966 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
967 VEX, TB;
968}
969
970defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
971defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
972
973// Mask shift
974multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
975 SDNode OpNode> {
976 let Predicates = [HasAVX512] in
977 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
978 !strconcat(OpcodeStr,
979 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
980 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
981}
982
983multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
984 SDNode OpNode> {
985 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
986 VEX, OpSize, TA, VEX_W;
987}
988
989defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
990defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
991
992// Mask setting all 0s or 1s
993multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
994 let Predicates = [HasAVX512] in
995 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
996 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
997 [(set KRC:$dst, (VT Val))]>;
998}
999
1000multiclass avx512_mask_setop_w<PatFrag Val> {
1001 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1002 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1003}
1004
1005defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1006defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1007
1008// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1009let Predicates = [HasAVX512] in {
1010 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1011 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1012}
1013def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1014 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1015
1016def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1017 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1018
1019def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1020 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1021
1022//===----------------------------------------------------------------------===//
1023// AVX-512 - Aligned and unaligned load and store
1024//
1025
1026multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1027 X86MemOperand x86memop, PatFrag ld_frag,
1028 string asm, Domain d> {
1029let neverHasSideEffects = 1 in
1030 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1031 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1032 EVEX;
1033let canFoldAsLoad = 1 in
1034 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1035 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1036 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1037let Constraints = "$src1 = $dst" in {
1038 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1039 (ins RC:$src1, KRC:$mask, RC:$src2),
1040 !strconcat(asm,
1041 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1042 EVEX, EVEX_K;
1043 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1044 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1045 !strconcat(asm,
1046 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1047 [], d>, EVEX, EVEX_K;
1048}
1049}
1050
1051defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1052 "vmovaps", SSEPackedSingle>,
1053 EVEX_V512, EVEX_CD8<32, CD8VF>;
1054defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1055 "vmovapd", SSEPackedDouble>,
1056 OpSize, EVEX_V512, VEX_W,
1057 EVEX_CD8<64, CD8VF>;
1058defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1059 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1060 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1061defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1062 "vmovupd", SSEPackedDouble>,
1063 OpSize, EVEX_V512, VEX_W,
1064 EVEX_CD8<64, CD8VF>;
1065def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1066 "vmovaps\t{$src, $dst|$dst, $src}",
1067 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1068 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1069def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1070 "vmovapd\t{$src, $dst|$dst, $src}",
1071 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1072 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1073 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1074def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1075 "vmovups\t{$src, $dst|$dst, $src}",
1076 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1077 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1078def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1079 "vmovupd\t{$src, $dst|$dst, $src}",
1080 [(store (v8f64 VR512:$src), addr:$dst)],
1081 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1082 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1083
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1084let neverHasSideEffects = 1 in {
1085 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1086 (ins VR512:$src),
1087 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1088 EVEX, EVEX_V512;
1089 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1090 (ins VR512:$src),
1091 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1092 EVEX, EVEX_V512, VEX_W;
1093let mayStore = 1 in {
1094 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1095 (ins i512mem:$dst, VR512:$src),
1096 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1097 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1098 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1099 (ins i512mem:$dst, VR512:$src),
1100 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1101 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1102}
1103let mayLoad = 1 in {
1104def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1105 (ins i512mem:$src),
1106 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1108def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1109 (ins i512mem:$src),
1110 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1111 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1112}
1113}
1114
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1115// 512-bit aligned load/store
1116def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1117def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1118
1119def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1120 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1121def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1122 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1123
1124multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1125 RegisterClass RC, RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1126 PatFrag ld_frag, X86MemOperand x86memop> {
1127let neverHasSideEffects = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1128 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1129 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1130let canFoldAsLoad = 1 in
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1131 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1132 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1133 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1134let mayStore = 1 in
1135 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1136 (ins x86memop:$dst, VR512:$src),
1137 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1138let Constraints = "$src1 = $dst" in {
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1139 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1140 (ins RC:$src1, KRC:$mask, RC:$src2),
1141 !strconcat(asm,
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1143 EVEX, EVEX_K;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1144 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1145 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1146 !strconcat(asm,
1147 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1148 []>, EVEX, EVEX_K;
1149}
1150}
1151
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1152defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1153 memopv16i32, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1154 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1155defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1156 memopv8i64, i512mem>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1157 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1158
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1159// 512-bit unaligned load/store
1160def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1161def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1162
1163def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1164 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1165def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1166 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1167
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1168let AddedComplexity = 20 in {
1169def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1170 (v16f32 VR512:$src2))),
1171 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1172def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1173 (v8f64 VR512:$src2))),
1174 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1175def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1176 (v16i32 VR512:$src2))),
1177 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1178def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1179 (v8i64 VR512:$src2))),
1180 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1181}
1182// Move Int Doubleword to Packed Double Int
1183//
1184def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1185 "vmovd{z}\t{$src, $dst|$dst, $src}",
1186 [(set VR128X:$dst,
1187 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1188 EVEX, VEX_LIG;
1189def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1190 "vmovd{z}\t{$src, $dst|$dst, $src}",
1191 [(set VR128X:$dst,
1192 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1193 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1194def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1195 "vmovq{z}\t{$src, $dst|$dst, $src}",
1196 [(set VR128X:$dst,
1197 (v2i64 (scalar_to_vector GR64:$src)))],
1198 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1199let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1200def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1201 "vmovq{z}\t{$src, $dst|$dst, $src}",
1202 [(set FR64:$dst, (bitconvert GR64:$src))],
1203 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1204def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1205 "vmovq{z}\t{$src, $dst|$dst, $src}",
1206 [(set GR64:$dst, (bitconvert FR64:$src))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1208}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1209def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1210 "vmovq{z}\t{$src, $dst|$dst, $src}",
1211 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1212 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1213 EVEX_CD8<64, CD8VT1>;
1214
1215// Move Int Doubleword to Single Scalar
1216//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1217let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1218def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1219 "vmovd{z}\t{$src, $dst|$dst, $src}",
1220 [(set FR32X:$dst, (bitconvert GR32:$src))],
1221 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1222
1223def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1224 "vmovd{z}\t{$src, $dst|$dst, $src}",
1225 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1226 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1227}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1228
1229// Move Packed Doubleword Int to Packed Double Int
1230//
1231def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1232 "vmovd{z}\t{$src, $dst|$dst, $src}",
1233 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1234 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1235 EVEX, VEX_LIG;
1236def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1237 (ins i32mem:$dst, VR128X:$src),
1238 "vmovd{z}\t{$src, $dst|$dst, $src}",
1239 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1240 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1241 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1242
1243// Move Packed Doubleword Int first element to Doubleword Int
1244//
1245def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1246 "vmovq{z}\t{$src, $dst|$dst, $src}",
1247 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1248 (iPTR 0)))],
1249 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1250 Requires<[HasAVX512, In64BitMode]>;
1251
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1252def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253 (ins i64mem:$dst, VR128X:$src),
1254 "vmovq{z}\t{$src, $dst|$dst, $src}",
1255 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1256 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1257 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1258 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1259
1260// Move Scalar Single to Double Int
1261//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1262let isCodeGenOnly = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1263def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1264 (ins FR32X:$src),
1265 "vmovd{z}\t{$src, $dst|$dst, $src}",
1266 [(set GR32:$dst, (bitconvert FR32X:$src))],
1267 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1268def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1269 (ins i32mem:$dst, FR32X:$src),
1270 "vmovd{z}\t{$src, $dst|$dst, $src}",
1271 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1272 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]1273}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1274
1275// Move Quadword Int to Packed Quadword Int
1276//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1277def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1278 (ins i64mem:$src),
1279 "vmovq{z}\t{$src, $dst|$dst, $src}",
1280 [(set VR128X:$dst,
1281 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1282 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1283
1284//===----------------------------------------------------------------------===//
1285// AVX-512 MOVSS, MOVSD
1286//===----------------------------------------------------------------------===//
1287
1288multiclass avx512_move_scalar <string asm, RegisterClass RC,
1289 SDNode OpNode, ValueType vt,
1290 X86MemOperand x86memop, PatFrag mem_pat> {
1291 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1292 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1293 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1294 (scalar_to_vector RC:$src2))))],
1295 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1296 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1297 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1298 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1299 EVEX, VEX_LIG;
1300 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1301 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1302 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1303 EVEX, VEX_LIG;
1304}
1305
1306let ExeDomain = SSEPackedSingle in
1307defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1308 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1309
1310let ExeDomain = SSEPackedDouble in
1311defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1312 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1313
1314
1315// For the disassembler
1316let isCodeGenOnly = 1 in {
1317 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1318 (ins VR128X:$src1, FR32X:$src2),
1319 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1320 IIC_SSE_MOV_S_RR>,
1321 XS, EVEX_4V, VEX_LIG;
1322 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1323 (ins VR128X:$src1, FR64X:$src2),
1324 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1325 IIC_SSE_MOV_S_RR>,
1326 XD, EVEX_4V, VEX_LIG, VEX_W;
1327}
1328
1329let Predicates = [HasAVX512] in {
1330 let AddedComplexity = 15 in {
1331 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1332 // MOVS{S,D} to the lower bits.
1333 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1334 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1335 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1336 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1337 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1338 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1339 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1340 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1341
1342 // Move low f32 and clear high bits.
1343 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1344 (SUBREG_TO_REG (i32 0),
1345 (VMOVSSZrr (v4f32 (V_SET0)),
1346 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1347 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1348 (SUBREG_TO_REG (i32 0),
1349 (VMOVSSZrr (v4i32 (V_SET0)),
1350 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1351 }
1352
1353 let AddedComplexity = 20 in {
1354 // MOVSSrm zeros the high parts of the register; represent this
1355 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1356 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1357 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1358 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1359 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1360 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1361 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1362
1363 // MOVSDrm zeros the high parts of the register; represent this
1364 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1365 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1366 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1367 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1368 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1369 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1370 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1371 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1372 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1373 def : Pat<(v2f64 (X86vzload addr:$src)),
1374 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1375
1376 // Represent the same patterns above but in the form they appear for
1377 // 256-bit types
1378 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1379 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1380 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1381 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1382 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1383 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1384 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1385 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1386 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1387 }
1388 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1389 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1390 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1391 FR32X:$src)), sub_xmm)>;
1392 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1393 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1394 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1395 FR64X:$src)), sub_xmm)>;
1396 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1397 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1398 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1399
1400 // Move low f64 and clear high bits.
1401 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1402 (SUBREG_TO_REG (i32 0),
1403 (VMOVSDZrr (v2f64 (V_SET0)),
1404 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1405
1406 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1407 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1408 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1409
1410 // Extract and store.
1411 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1412 addr:$dst),
1413 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1414 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1415 addr:$dst),
1416 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1417
1418 // Shuffle with VMOVSS
1419 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1420 (VMOVSSZrr (v4i32 VR128X:$src1),
1421 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1422 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1423 (VMOVSSZrr (v4f32 VR128X:$src1),
1424 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1425
1426 // 256-bit variants
1427 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1431 sub_xmm)>;
1432 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1433 (SUBREG_TO_REG (i32 0),
1434 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1435 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1436 sub_xmm)>;
1437
1438 // Shuffle with VMOVSD
1439 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1440 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1441 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1442 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1443 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1444 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1445 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1446 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1447
1448 // 256-bit variants
1449 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1450 (SUBREG_TO_REG (i32 0),
1451 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1452 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1453 sub_xmm)>;
1454 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1455 (SUBREG_TO_REG (i32 0),
1456 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1457 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1458 sub_xmm)>;
1459
1460 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1461 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1462 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1463 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1464 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1465 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1466 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1467 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1468}
1469
1470let AddedComplexity = 15 in
1471def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1472 (ins VR128X:$src),
1473 "vmovq{z}\t{$src, $dst|$dst, $src}",
1474 [(set VR128X:$dst, (v2i64 (X86vzmovl
1475 (v2i64 VR128X:$src))))],
1476 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1477
1478let AddedComplexity = 20 in
1479def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1480 (ins i128mem:$src),
1481 "vmovq{z}\t{$src, $dst|$dst, $src}",
1482 [(set VR128X:$dst, (v2i64 (X86vzmovl
1483 (loadv2i64 addr:$src))))],
1484 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1485 EVEX_CD8<8, CD8VT8>;
1486
1487let Predicates = [HasAVX512] in {
1488 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1489 let AddedComplexity = 20 in {
1490 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1491 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1492 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1493 (VMOV64toPQIZrr GR64:$src)>;
1494 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1495 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1496
1497 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1498 (VMOVDI2PDIZrm addr:$src)>;
1499 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1500 (VMOVDI2PDIZrm addr:$src)>;
1501 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1502 (VMOVZPQILo2PQIZrm addr:$src)>;
1503 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1504 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1505 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1506
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1507 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1508 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1509 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1510 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1511 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1512 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1513 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1514}
1515
1516def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1517 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1518
1519def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1520 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1521
1522def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1523 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1524
1525def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1526 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1527
1528//===----------------------------------------------------------------------===//
1529// AVX-512 - Integer arithmetic
1530//
1531multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1532 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1533 X86MemOperand x86memop, PatFrag scalar_mfrag,
1534 X86MemOperand x86scalar_mop, string BrdcstStr,
1535 OpndItins itins, bit IsCommutable = 0> {
1536 let isCommutable = IsCommutable in
1537 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1538 (ins RC:$src1, RC:$src2),
1539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1540 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1541 itins.rr>, EVEX_4V;
1542 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1543 (ins RC:$src1, x86memop:$src2),
1544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1545 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1546 itins.rm>, EVEX_4V;
1547 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1548 (ins RC:$src1, x86scalar_mop:$src2),
1549 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1550 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1551 [(set RC:$dst, (OpNode RC:$src1,
1552 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1553 itins.rm>, EVEX_4V, EVEX_B;
1554}
1555multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1556 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1557 PatFrag memop_frag, X86MemOperand x86memop,
1558 OpndItins itins,
1559 bit IsCommutable = 0> {
1560 let isCommutable = IsCommutable in
1561 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1562 (ins RC:$src1, RC:$src2),
1563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1564 []>, EVEX_4V, VEX_W;
1565 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1566 (ins RC:$src1, x86memop:$src2),
1567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1568 []>, EVEX_4V, VEX_W;
1569}
1570
1571defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1572 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1573 EVEX_V512, EVEX_CD8<32, CD8VF>;
1574
1575defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1576 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1577 EVEX_V512, EVEX_CD8<32, CD8VF>;
1578
1579defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1580 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1581 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1582
1583defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1584 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1585 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1586
1587defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1588 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1589 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1590
1591defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1592 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1593 EVEX_V512, EVEX_CD8<64, CD8VF>;
1594
1595defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1596 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1597 EVEX_CD8<64, CD8VF>;
1598
1599def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1600 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1601
1602//===----------------------------------------------------------------------===//
1603// AVX-512 - Unpack Instructions
1604//===----------------------------------------------------------------------===//
1605
1606multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1607 PatFrag mem_frag, RegisterClass RC,
1608 X86MemOperand x86memop, string asm,
1609 Domain d> {
1610 def rr : AVX512PI<opc, MRMSrcReg,
1611 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1612 asm, [(set RC:$dst,
1613 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1614 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1615 def rm : AVX512PI<opc, MRMSrcMem,
1616 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1617 asm, [(set RC:$dst,
1618 (vt (OpNode RC:$src1,
1619 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1620 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1621}
1622
1623defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1624 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1625 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1626defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1627 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1628 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1629defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1630 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1631 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1632defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1633 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1634 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1635
1636multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1637 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1638 X86MemOperand x86memop> {
1639 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1640 (ins RC:$src1, RC:$src2),
1641 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1642 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1643 IIC_SSE_UNPCK>, EVEX_4V;
1644 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1645 (ins RC:$src1, x86memop:$src2),
1646 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1647 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1648 (bitconvert (memop_frag addr:$src2)))))],
1649 IIC_SSE_UNPCK>, EVEX_4V;
1650}
1651defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1652 VR512, memopv16i32, i512mem>, EVEX_V512,
1653 EVEX_CD8<32, CD8VF>;
1654defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1655 VR512, memopv8i64, i512mem>, EVEX_V512,
1656 VEX_W, EVEX_CD8<64, CD8VF>;
1657defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1658 VR512, memopv16i32, i512mem>, EVEX_V512,
1659 EVEX_CD8<32, CD8VF>;
1660defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1661 VR512, memopv8i64, i512mem>, EVEX_V512,
1662 VEX_W, EVEX_CD8<64, CD8VF>;
1663//===----------------------------------------------------------------------===//
1664// AVX-512 - PSHUFD
1665//
1666
1667multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1668 SDNode OpNode, PatFrag mem_frag,
1669 X86MemOperand x86memop, ValueType OpVT> {
1670 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1671 (ins RC:$src1, i8imm:$src2),
1672 !strconcat(OpcodeStr,
1673 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1674 [(set RC:$dst,
1675 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1676 EVEX;
1677 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1678 (ins x86memop:$src1, i8imm:$src2),
1679 !strconcat(OpcodeStr,
1680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1681 [(set RC:$dst,
1682 (OpVT (OpNode (mem_frag addr:$src1),
1683 (i8 imm:$src2))))]>, EVEX;
1684}
1685
1686defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1687 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1688
1689let ExeDomain = SSEPackedSingle in
1690defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1691 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1692 EVEX_CD8<32, CD8VF>;
1693let ExeDomain = SSEPackedDouble in
1694defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1695 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1696 VEX_W, EVEX_CD8<32, CD8VF>;
1697
1698def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1699 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1700def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1701 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1702
1703//===----------------------------------------------------------------------===//
1704// AVX-512 Logical Instructions
1705//===----------------------------------------------------------------------===//
1706
1707defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1708 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1709 EVEX_V512, EVEX_CD8<32, CD8VF>;
1710defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1711 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1712 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1713defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1714 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1715 EVEX_V512, EVEX_CD8<32, CD8VF>;
1716defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1717 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1718 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1719defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1720 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1721 EVEX_V512, EVEX_CD8<32, CD8VF>;
1722defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1723 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1724 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1725defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1726 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1727 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1728defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1729 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1730 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1731
1732//===----------------------------------------------------------------------===//
1733// AVX-512 FP arithmetic
1734//===----------------------------------------------------------------------===//
1735
1736multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1737 SizeItins itins> {
1738 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1739 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1740 EVEX_CD8<32, CD8VT1>;
1741 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1742 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1743 EVEX_CD8<64, CD8VT1>;
1744}
1745
1746let isCommutable = 1 in {
1747defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1748defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1749defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1750defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1751}
1752let isCommutable = 0 in {
1753defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1754defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1755}
1756
1757multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1758 RegisterClass RC, ValueType vt,
1759 X86MemOperand x86memop, PatFrag mem_frag,
1760 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1761 string BrdcstStr,
1762 Domain d, OpndItins itins, bit commutable> {
1763 let isCommutable = commutable in
1764 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1765 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1766 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1767 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1768 let mayLoad = 1 in {
1769 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1771 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1772 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1773 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1774 (ins RC:$src1, x86scalar_mop:$src2),
1775 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1776 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1777 [(set RC:$dst, (OpNode RC:$src1,
1778 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1779 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1780 }
1781}
1782
1783defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1784 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1785 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1786
1787defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1788 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1789 SSE_ALU_ITINS_P.d, 1>,
1790 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1791
1792defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1793 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1794 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1795defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1796 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1797 SSE_ALU_ITINS_P.d, 1>,
1798 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1799
1800defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1801 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1802 SSE_ALU_ITINS_P.s, 1>,
1803 EVEX_V512, EVEX_CD8<32, CD8VF>;
1804defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1805 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1806 SSE_ALU_ITINS_P.s, 1>,
1807 EVEX_V512, EVEX_CD8<32, CD8VF>;
1808
1809defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1810 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1811 SSE_ALU_ITINS_P.d, 1>,
1812 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1813defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1814 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1815 SSE_ALU_ITINS_P.d, 1>,
1816 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1817
1818defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1819 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1820 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1821defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1822 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1823 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1824
1825defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1826 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1827 SSE_ALU_ITINS_P.d, 0>,
1828 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1829defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1830 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1831 SSE_ALU_ITINS_P.d, 0>,
1832 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1833
1834//===----------------------------------------------------------------------===//
1835// AVX-512 VPTESTM instructions
1836//===----------------------------------------------------------------------===//
1837
1838multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1839 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1840 SDNode OpNode, ValueType vt> {
1841 def rr : AVX5128I<opc, MRMSrcReg,
1842 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1845 def rm : AVX5128I<opc, MRMSrcMem,
1846 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1847 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1848 [(set KRC:$dst, (OpNode (vt RC:$src1),
1849 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1850}
1851
1852defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1853 memopv16i32, X86testm, v16i32>, EVEX_V512,
1854 EVEX_CD8<32, CD8VF>;
1855defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1856 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1857 EVEX_CD8<64, CD8VF>;
1858
1859//===----------------------------------------------------------------------===//
1860// AVX-512 Shift instructions
1861//===----------------------------------------------------------------------===//
1862multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1863 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1864 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1865 RegisterClass KRC> {
1866 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1867 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1868 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1869 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1870 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1871 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1872 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1873 !strconcat(OpcodeStr,
1874 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1875 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1876 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1877 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1878 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1879 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1880 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1881 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]1882 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1883 !strconcat(OpcodeStr,
1884 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1885 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1886}
1887
1888multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1889 RegisterClass RC, ValueType vt, ValueType SrcVT,
1890 PatFrag bc_frag, RegisterClass KRC> {
1891 // src2 is always 128-bit
1892 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1893 (ins RC:$src1, VR128X:$src2),
1894 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1895 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1896 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1897 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1898 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1899 !strconcat(OpcodeStr,
1900 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1901 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1902 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1903 (ins RC:$src1, i128mem:$src2),
1904 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1905 [(set RC:$dst, (vt (OpNode RC:$src1,
1906 (bc_frag (memopv2i64 addr:$src2)))))],
1907 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1908 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1909 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1910 !strconcat(OpcodeStr,
1911 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1912 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1913}
1914
1915defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1916 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1917 EVEX_V512, EVEX_CD8<32, CD8VF>;
1918defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1919 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1920 EVEX_CD8<32, CD8VQ>;
1921
1922defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1923 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1924 EVEX_CD8<64, CD8VF>, VEX_W;
1925defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1926 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1927 EVEX_CD8<64, CD8VQ>, VEX_W;
1928
1929defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1930 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1931 EVEX_CD8<32, CD8VF>;
1932defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1933 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1934 EVEX_CD8<32, CD8VQ>;
1935
1936defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1937 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1938 EVEX_CD8<64, CD8VF>, VEX_W;
1939defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1940 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1941 EVEX_CD8<64, CD8VQ>, VEX_W;
1942
1943defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1944 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1945 EVEX_V512, EVEX_CD8<32, CD8VF>;
1946defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1947 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1948 EVEX_CD8<32, CD8VQ>;
1949
1950defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1951 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1952 EVEX_CD8<64, CD8VF>, VEX_W;
1953defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1954 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1955 EVEX_CD8<64, CD8VQ>, VEX_W;
1956
1957//===-------------------------------------------------------------------===//
1958// Variable Bit Shifts
1959//===-------------------------------------------------------------------===//
1960multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1961 RegisterClass RC, ValueType vt,
1962 X86MemOperand x86memop, PatFrag mem_frag> {
1963 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1964 (ins RC:$src1, RC:$src2),
1965 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1966 [(set RC:$dst,
1967 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1968 EVEX_4V;
1969 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1970 (ins RC:$src1, x86memop:$src2),
1971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1972 [(set RC:$dst,
1973 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1974 EVEX_4V;
1975}
1976
1977defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1978 i512mem, memopv16i32>, EVEX_V512,
1979 EVEX_CD8<32, CD8VF>;
1980defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1981 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1982 EVEX_CD8<64, CD8VF>;
1983defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1984 i512mem, memopv16i32>, EVEX_V512,
1985 EVEX_CD8<32, CD8VF>;
1986defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1987 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1988 EVEX_CD8<64, CD8VF>;
1989defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1990 i512mem, memopv16i32>, EVEX_V512,
1991 EVEX_CD8<32, CD8VF>;
1992defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1993 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1994 EVEX_CD8<64, CD8VF>;
1995
1996//===----------------------------------------------------------------------===//
1997// AVX-512 - MOVDDUP
1998//===----------------------------------------------------------------------===//
1999
2000multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2001 X86MemOperand x86memop, PatFrag memop_frag> {
2002def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2003 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2004 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2005def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2007 [(set RC:$dst,
2008 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2009}
2010
2011defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2012 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2013def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2014 (VMOVDDUPZrm addr:$src)>;
2015
2016def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2017 (ins VR128X:$src1, VR128X:$src2),
2018 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2019 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2020 IIC_SSE_MOV_LH>, EVEX_4V;
2021def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2022 (ins VR128X:$src1, VR128X:$src2),
2023 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2024 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2025 IIC_SSE_MOV_LH>, EVEX_4V;
2026
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2027let Predicates = [HasAVX512] in {
2028 // MOVLHPS patterns
2029 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2030 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2031 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2032 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2033
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2034 // MOVHLPS patterns
2035 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2036 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2037}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2038
2039//===----------------------------------------------------------------------===//
2040// FMA - Fused Multiply Operations
2041//
2042let Constraints = "$src1 = $dst" in {
2043multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2044 RegisterClass RC, X86MemOperand x86memop,
2045 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2046 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2047 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2048 (ins RC:$src1, RC:$src2, RC:$src3),
2049 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2050 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2051
2052 let mayLoad = 1 in
2053 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2054 (ins RC:$src1, RC:$src2, x86memop:$src3),
2055 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2056 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2057 (mem_frag addr:$src3))))]>;
2058 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2059 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2060 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2061 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2062 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2063 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2064}
2065} // Constraints = "$src1 = $dst"
2066
2067let ExeDomain = SSEPackedSingle in {
2068 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2069 memopv16f32, f32mem, loadf32, "{1to16}",
2070 X86Fmadd, v16f32>, EVEX_V512,
2071 EVEX_CD8<32, CD8VF>;
2072 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2073 memopv16f32, f32mem, loadf32, "{1to16}",
2074 X86Fmsub, v16f32>, EVEX_V512,
2075 EVEX_CD8<32, CD8VF>;
2076 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2077 memopv16f32, f32mem, loadf32, "{1to16}",
2078 X86Fmaddsub, v16f32>,
2079 EVEX_V512, EVEX_CD8<32, CD8VF>;
2080 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2081 memopv16f32, f32mem, loadf32, "{1to16}",
2082 X86Fmsubadd, v16f32>,
2083 EVEX_V512, EVEX_CD8<32, CD8VF>;
2084 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2085 memopv16f32, f32mem, loadf32, "{1to16}",
2086 X86Fnmadd, v16f32>, EVEX_V512,
2087 EVEX_CD8<32, CD8VF>;
2088 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2089 memopv16f32, f32mem, loadf32, "{1to16}",
2090 X86Fnmsub, v16f32>, EVEX_V512,
2091 EVEX_CD8<32, CD8VF>;
2092}
2093let ExeDomain = SSEPackedDouble in {
2094 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2095 memopv8f64, f64mem, loadf64, "{1to8}",
2096 X86Fmadd, v8f64>, EVEX_V512,
2097 VEX_W, EVEX_CD8<64, CD8VF>;
2098 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2099 memopv8f64, f64mem, loadf64, "{1to8}",
2100 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2101 EVEX_CD8<64, CD8VF>;
2102 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2103 memopv8f64, f64mem, loadf64, "{1to8}",
2104 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2105 EVEX_CD8<64, CD8VF>;
2106 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2107 memopv8f64, f64mem, loadf64, "{1to8}",
2108 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2109 EVEX_CD8<64, CD8VF>;
2110 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2111 memopv8f64, f64mem, loadf64, "{1to8}",
2112 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2113 EVEX_CD8<64, CD8VF>;
2114 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2115 memopv8f64, f64mem, loadf64, "{1to8}",
2116 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2117 EVEX_CD8<64, CD8VF>;
2118}
2119
2120let Constraints = "$src1 = $dst" in {
2121multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2122 RegisterClass RC, X86MemOperand x86memop,
2123 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2124 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2125 let mayLoad = 1 in
2126 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2127 (ins RC:$src1, RC:$src3, x86memop:$src2),
2128 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2129 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2130 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2131 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2132 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2133 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2134 [(set RC:$dst, (OpNode RC:$src1,
2135 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2136}
2137} // Constraints = "$src1 = $dst"
2138
2139
2140let ExeDomain = SSEPackedSingle in {
2141 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2142 memopv16f32, f32mem, loadf32, "{1to16}",
2143 X86Fmadd, v16f32>, EVEX_V512,
2144 EVEX_CD8<32, CD8VF>;
2145 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2146 memopv16f32, f32mem, loadf32, "{1to16}",
2147 X86Fmsub, v16f32>, EVEX_V512,
2148 EVEX_CD8<32, CD8VF>;
2149 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2150 memopv16f32, f32mem, loadf32, "{1to16}",
2151 X86Fmaddsub, v16f32>,
2152 EVEX_V512, EVEX_CD8<32, CD8VF>;
2153 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2154 memopv16f32, f32mem, loadf32, "{1to16}",
2155 X86Fmsubadd, v16f32>,
2156 EVEX_V512, EVEX_CD8<32, CD8VF>;
2157 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2158 memopv16f32, f32mem, loadf32, "{1to16}",
2159 X86Fnmadd, v16f32>, EVEX_V512,
2160 EVEX_CD8<32, CD8VF>;
2161 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2162 memopv16f32, f32mem, loadf32, "{1to16}",
2163 X86Fnmsub, v16f32>, EVEX_V512,
2164 EVEX_CD8<32, CD8VF>;
2165}
2166let ExeDomain = SSEPackedDouble in {
2167 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2168 memopv8f64, f64mem, loadf64, "{1to8}",
2169 X86Fmadd, v8f64>, EVEX_V512,
2170 VEX_W, EVEX_CD8<64, CD8VF>;
2171 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2172 memopv8f64, f64mem, loadf64, "{1to8}",
2173 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2174 EVEX_CD8<64, CD8VF>;
2175 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2176 memopv8f64, f64mem, loadf64, "{1to8}",
2177 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2178 EVEX_CD8<64, CD8VF>;
2179 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2180 memopv8f64, f64mem, loadf64, "{1to8}",
2181 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2182 EVEX_CD8<64, CD8VF>;
2183 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2184 memopv8f64, f64mem, loadf64, "{1to8}",
2185 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2186 EVEX_CD8<64, CD8VF>;
2187 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2188 memopv8f64, f64mem, loadf64, "{1to8}",
2189 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2190 EVEX_CD8<64, CD8VF>;
2191}
2192
2193// Scalar FMA
2194let Constraints = "$src1 = $dst" in {
2195multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2196 RegisterClass RC, ValueType OpVT,
2197 X86MemOperand x86memop, Operand memop,
2198 PatFrag mem_frag> {
2199 let isCommutable = 1 in
2200 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2201 (ins RC:$src1, RC:$src2, RC:$src3),
2202 !strconcat(OpcodeStr,
2203 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2204 [(set RC:$dst,
2205 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2206 let mayLoad = 1 in
2207 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2208 (ins RC:$src1, RC:$src2, f128mem:$src3),
2209 !strconcat(OpcodeStr,
2210 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2211 [(set RC:$dst,
2212 (OpVT (OpNode RC:$src2, RC:$src1,
2213 (mem_frag addr:$src3))))]>;
2214}
2215
2216} // Constraints = "$src1 = $dst"
2217
2218defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2219 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2220defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2221 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2222defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2223 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2224defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2225 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2226defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2227 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2228defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2229 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2230defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2231 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2232defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2233 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2234
2235//===----------------------------------------------------------------------===//
2236// AVX-512 Scalar convert from sign integer to float/double
2237//===----------------------------------------------------------------------===//
2238
2239multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2240 X86MemOperand x86memop, string asm> {
2241let neverHasSideEffects = 1 in {
2242 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2243 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2244 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2245 let mayLoad = 1 in
2246 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2247 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2248 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2249 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2250} // neverHasSideEffects = 1
2251}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2252let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2253defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2254 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2255defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2256 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2257defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2258 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2259defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2260 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2261
2262def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2263 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2264def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2265 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2266def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2267 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2268def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2269 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2270
2271def : Pat<(f32 (sint_to_fp GR32:$src)),
2272 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2273def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2274 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2275def : Pat<(f64 (sint_to_fp GR32:$src)),
2276 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2277def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2278 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2279
2280defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2281 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2282defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2283 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2284defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2285 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2286defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2287 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2288
2289def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2290 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2291def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2292 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2293def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2294 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2295def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2296 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2297
2298def : Pat<(f32 (uint_to_fp GR32:$src)),
2299 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2300def : Pat<(f32 (uint_to_fp GR64:$src)),
2301 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2302def : Pat<(f64 (uint_to_fp GR32:$src)),
2303 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2304def : Pat<(f64 (uint_to_fp GR64:$src)),
2305 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]2306}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2307
2308//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]2309// AVX-512 Scalar convert from float/double to integer
2310//===----------------------------------------------------------------------===//
2311multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2312 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2313 string asm> {
2314let neverHasSideEffects = 1 in {
2315 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2316 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2317 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2318 let mayLoad = 1 in
2319 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2320 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2321} // neverHasSideEffects = 1
2322}
2323let Predicates = [HasAVX512] in {
2324// Convert float/double to signed/unsigned int 32/64
2325defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2326 ssmem, sse_load_f32, "cvtss2si{z}">,
2327 XS, EVEX_CD8<32, CD8VT1>;
2328defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2329 ssmem, sse_load_f32, "cvtss2si{z}">,
2330 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2331defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2332 ssmem, sse_load_f32, "cvtss2usi{z}">,
2333 XS, EVEX_CD8<32, CD8VT1>;
2334defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2335 int_x86_avx512_cvtss2usi64, ssmem,
2336 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2337 EVEX_CD8<32, CD8VT1>;
2338defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2339 sdmem, sse_load_f64, "cvtsd2si{z}">,
2340 XD, EVEX_CD8<64, CD8VT1>;
2341defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2342 sdmem, sse_load_f64, "cvtsd2si{z}">,
2343 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2344defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2345 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2346 XD, EVEX_CD8<64, CD8VT1>;
2347defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2348 int_x86_avx512_cvtsd2usi64, sdmem,
2349 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2350 EVEX_CD8<64, CD8VT1>;
2351
2352defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2353 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2354 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2355defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2356 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2357 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2358defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2359 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2360 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2361defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2362 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2363 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2364
2365defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2366 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2367 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2368defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2369 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2370 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2371defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2372 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2373 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2374defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2375 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2376 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2377
2378// Convert float/double to signed/unsigned int 32/64 with truncation
2379defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2380 ssmem, sse_load_f32, "cvttss2si{z}">,
2381 XS, EVEX_CD8<32, CD8VT1>;
2382defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2383 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2384 "cvttss2si{z}">, XS, VEX_W,
2385 EVEX_CD8<32, CD8VT1>;
2386defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2387 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2388 EVEX_CD8<64, CD8VT1>;
2389defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2390 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2391 "cvttsd2si{z}">, XD, VEX_W,
2392 EVEX_CD8<64, CD8VT1>;
2393defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2394 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2395 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2396defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2397 int_x86_avx512_cvttss2usi64, ssmem,
2398 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2399 EVEX_CD8<32, CD8VT1>;
2400defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2401 int_x86_avx512_cvttsd2usi,
2402 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2403 EVEX_CD8<64, CD8VT1>;
2404defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2405 int_x86_avx512_cvttsd2usi64, sdmem,
2406 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2407 EVEX_CD8<64, CD8VT1>;
2408}
2409
2410multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2411 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2412 string asm> {
2413 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2414 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2415 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2416 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2417 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2418 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2419}
2420
2421defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2422 loadf32, "cvttss2si{z}">, XS,
2423 EVEX_CD8<32, CD8VT1>;
2424defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2425 loadf32, "cvttss2usi{z}">, XS,
2426 EVEX_CD8<32, CD8VT1>;
2427defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2428 loadf32, "cvttss2si{z}">, XS, VEX_W,
2429 EVEX_CD8<32, CD8VT1>;
2430defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2431 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2432 EVEX_CD8<32, CD8VT1>;
2433defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2434 loadf64, "cvttsd2si{z}">, XD,
2435 EVEX_CD8<64, CD8VT1>;
2436defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2437 loadf64, "cvttsd2usi{z}">, XD,
2438 EVEX_CD8<64, CD8VT1>;
2439defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2440 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2441 EVEX_CD8<64, CD8VT1>;
2442defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2443 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2444 EVEX_CD8<64, CD8VT1>;
2445//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2446// AVX-512 Convert form float to double and back
2447//===----------------------------------------------------------------------===//
2448let neverHasSideEffects = 1 in {
2449def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2450 (ins FR32X:$src1, FR32X:$src2),
2451 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2453let mayLoad = 1 in
2454def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2455 (ins FR32X:$src1, f32mem:$src2),
2456 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2457 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2458 EVEX_CD8<32, CD8VT1>;
2459
2460// Convert scalar double to scalar single
2461def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2462 (ins FR64X:$src1, FR64X:$src2),
2463 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2464 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2465let mayLoad = 1 in
2466def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2467 (ins FR64X:$src1, f64mem:$src2),
2468 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2469 []>, EVEX_4V, VEX_LIG, VEX_W,
2470 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2471}
2472
2473def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2474 Requires<[HasAVX512]>;
2475def : Pat<(fextend (loadf32 addr:$src)),
2476 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2477
2478def : Pat<(extloadf32 addr:$src),
2479 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2480 Requires<[HasAVX512, OptForSize]>;
2481
2482def : Pat<(extloadf32 addr:$src),
2483 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2484 Requires<[HasAVX512, OptForSpeed]>;
2485
2486def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2487 Requires<[HasAVX512]>;
2488
2489multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2490 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2491 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2492 Domain d> {
2493let neverHasSideEffects = 1 in {
2494 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2495 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2496 [(set DstRC:$dst,
2497 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2498 let mayLoad = 1 in
2499 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2500 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2501 [(set DstRC:$dst,
2502 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2503} // neverHasSideEffects = 1
2504}
2505
2506defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2507 memopv8f64, f512mem, v8f32, v8f64,
2508 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2509 EVEX_CD8<64, CD8VF>;
2510
2511defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2512 memopv4f64, f256mem, v8f64, v8f32,
2513 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2514def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2515 (VCVTPS2PDZrm addr:$src)>;
2516
2517//===----------------------------------------------------------------------===//
2518// AVX-512 Vector convert from sign integer to float/double
2519//===----------------------------------------------------------------------===//
2520
2521defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2522 memopv8i64, i512mem, v16f32, v16i32,
2523 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2524
2525defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2526 memopv4i64, i256mem, v8f64, v8i32,
2527 SSEPackedDouble>, EVEX_V512, XS,
2528 EVEX_CD8<32, CD8VH>;
2529
2530defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2531 memopv16f32, f512mem, v16i32, v16f32,
2532 SSEPackedSingle>, EVEX_V512, XS,
2533 EVEX_CD8<32, CD8VF>;
2534
2535defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2536 memopv8f64, f512mem, v8i32, v8f64,
2537 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2538 EVEX_CD8<64, CD8VF>;
2539
2540defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2541 memopv16f32, f512mem, v16i32, v16f32,
2542 SSEPackedSingle>, EVEX_V512,
2543 EVEX_CD8<32, CD8VF>;
2544
2545defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2546 memopv8f64, f512mem, v8i32, v8f64,
2547 SSEPackedDouble>, EVEX_V512, VEX_W,
2548 EVEX_CD8<64, CD8VF>;
2549
2550defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2551 memopv4i64, f256mem, v8f64, v8i32,
2552 SSEPackedDouble>, EVEX_V512, XS,
2553 EVEX_CD8<32, CD8VH>;
2554
2555defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2556 memopv16i32, f512mem, v16f32, v16i32,
2557 SSEPackedSingle>, EVEX_V512, XD,
2558 EVEX_CD8<32, CD8VF>;
2559
2560def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2561 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2562 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2563
2564
2565def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2566 (VCVTDQ2PSZrr VR512:$src)>;
2567def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2568 (VCVTDQ2PSZrm addr:$src)>;
2569
2570def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2571 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2572 [(set VR512:$dst,
2573 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2574 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2575def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2576 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2577 [(set VR512:$dst,
2578 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2579 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2580
2581
2582let Predicates = [HasAVX512] in {
2583 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2584 (VCVTPD2PSZrm addr:$src)>;
2585 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2586 (VCVTPS2PDZrm addr:$src)>;
2587}
2588
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]2589//===----------------------------------------------------------------------===//
2590// Half precision conversion instructions
2591//===----------------------------------------------------------------------===//
2592multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2593 X86MemOperand x86memop, Intrinsic Int> {
2594 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2595 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2596 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2597 let neverHasSideEffects = 1, mayLoad = 1 in
2598 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2599 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2600}
2601
2602multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2603 X86MemOperand x86memop, Intrinsic Int> {
2604 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2605 (ins srcRC:$src1, i32i8imm:$src2),
2606 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2607 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2608 let neverHasSideEffects = 1, mayStore = 1 in
2609 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2610 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2611 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2612}
2613
2614defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2615 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2616 EVEX_CD8<32, CD8VH>;
2617defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2618 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2619 EVEX_CD8<32, CD8VH>;
2620
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2621let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2622 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2623 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2624 EVEX_CD8<32, CD8VT1>;
2625 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2626 "ucomisd{z}">, TB, OpSize, EVEX,
2627 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2628 let Pattern = []<dag> in {
2629 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2630 "comiss{z}">, TB, EVEX, VEX_LIG,
2631 EVEX_CD8<32, CD8VT1>;
2632 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2633 "comisd{z}">, TB, OpSize, EVEX,
2634 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2635 }
2636 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2637 load, "ucomiss">, TB, EVEX, VEX_LIG,
2638 EVEX_CD8<32, CD8VT1>;
2639 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2640 load, "ucomisd">, TB, OpSize, EVEX,
2641 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2642
2643 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2644 load, "comiss">, TB, EVEX, VEX_LIG,
2645 EVEX_CD8<32, CD8VT1>;
2646 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2647 load, "comisd">, TB, OpSize, EVEX,
2648 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2649}
2650
2651/// avx512_unop_p - AVX-512 unops in packed form.
2652multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2653 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2654 !strconcat(OpcodeStr,
2655 "ps\t{$src, $dst|$dst, $src}"),
2656 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2657 EVEX, EVEX_V512;
2658 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2659 !strconcat(OpcodeStr,
2660 "ps\t{$src, $dst|$dst, $src}"),
2661 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2662 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2663 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2664 !strconcat(OpcodeStr,
2665 "pd\t{$src, $dst|$dst, $src}"),
2666 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2667 EVEX, EVEX_V512, VEX_W;
2668 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2669 !strconcat(OpcodeStr,
2670 "pd\t{$src, $dst|$dst, $src}"),
2671 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2672 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2673}
2674
2675/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2676multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2677 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2678 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2679 !strconcat(OpcodeStr,
2680 "ps\t{$src, $dst|$dst, $src}"),
2681 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2682 EVEX, EVEX_V512;
2683 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2684 !strconcat(OpcodeStr,
2685 "ps\t{$src, $dst|$dst, $src}"),
2686 [(set VR512:$dst,
2687 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2688 EVEX_V512, EVEX_CD8<32, CD8VF>;
2689 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2690 !strconcat(OpcodeStr,
2691 "pd\t{$src, $dst|$dst, $src}"),
2692 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2693 EVEX, EVEX_V512, VEX_W;
2694 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2695 !strconcat(OpcodeStr,
2696 "pd\t{$src, $dst|$dst, $src}"),
2697 [(set VR512:$dst,
2698 (V8F64Int (memopv8f64 addr:$src)))]>,
2699 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2700}
2701
2702/// avx512_fp_unop_s - AVX-512 unops in scalar form.
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2703multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2704 let hasSideEffects = 0 in {
2705 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2706 (ins FR32X:$src1, FR32X:$src2),
2707 !strconcat(OpcodeStr,
2708 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2709 []>, EVEX_4V;
2710 let mayLoad = 1 in {
2711 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2712 (ins FR32X:$src1, f32mem:$src2),
2713 !strconcat(OpcodeStr,
2714 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2715 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2716 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2717 (ins VR128X:$src1, ssmem:$src2),
2718 !strconcat(OpcodeStr,
2719 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2720 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2721 }
2722 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2723 (ins FR64X:$src1, FR64X:$src2),
2724 !strconcat(OpcodeStr,
2725 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2726 EVEX_4V, VEX_W;
2727 let mayLoad = 1 in {
2728 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2729 (ins FR64X:$src1, f64mem:$src2),
2730 !strconcat(OpcodeStr,
2731 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2732 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2733 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2734 (ins VR128X:$src1, sdmem:$src2),
2735 !strconcat(OpcodeStr,
2736 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2737 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2738 }
2739}
2740}
2741
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2742defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2743 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2744 avx512_fp_unop_p_int<0x4C, "vrcp14",
2745 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2746
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2747defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2748 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2749 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2750 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2751
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2752def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2753 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2754 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2755 VR128X)>;
2756def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2757 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2758
2759def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2760 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2761 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2762 VR128X)>;
2763def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2764 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2765
2766let AddedComplexity = 20, Predicates = [HasERI] in {
2767defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2768 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2769 avx512_fp_unop_p_int<0xCA, "vrcp28",
2770 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2771
2772defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2773 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2774 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2775 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2776}
2777
2778let Predicates = [HasERI] in {
2779 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2780 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2781 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2782 VR128X)>;
2783 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2784 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2785
2786 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2787 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2788 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2789 VR128X)>;
2790 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2791 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2792}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2793multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2794 Intrinsic V16F32Int, Intrinsic V8F64Int,
2795 OpndItins itins_s, OpndItins itins_d> {
2796 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2798 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2799 EVEX, EVEX_V512;
2800
2801 let mayLoad = 1 in
2802 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2803 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2804 [(set VR512:$dst,
2805 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2806 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2807
2808 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2809 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2810 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2811 EVEX, EVEX_V512;
2812
2813 let mayLoad = 1 in
2814 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2815 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2816 [(set VR512:$dst, (OpNode
2817 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2818 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2819
2820 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2821 !strconcat(OpcodeStr,
2822 "ps\t{$src, $dst|$dst, $src}"),
2823 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2824 EVEX, EVEX_V512;
2825 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2826 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2827 [(set VR512:$dst,
2828 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2829 EVEX_V512, EVEX_CD8<32, CD8VF>;
2830 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2831 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2832 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2833 EVEX, EVEX_V512, VEX_W;
2834 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2835 !strconcat(OpcodeStr,
2836 "pd\t{$src, $dst|$dst, $src}"),
2837 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2838 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2839}
2840
2841multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2842 Intrinsic F32Int, Intrinsic F64Int,
2843 OpndItins itins_s, OpndItins itins_d> {
2844 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2845 (ins FR32X:$src1, FR32X:$src2),
2846 !strconcat(OpcodeStr,
2847 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2848 [], itins_s.rr>, XS, EVEX_4V;
2849 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2850 (ins VR128X:$src1, VR128X:$src2),
2851 !strconcat(OpcodeStr,
2852 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2853 [(set VR128X:$dst,
2854 (F32Int VR128X:$src1, VR128X:$src2))],
2855 itins_s.rr>, XS, EVEX_4V;
2856 let mayLoad = 1 in {
2857 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2858 (ins FR32X:$src1, f32mem:$src2),
2859 !strconcat(OpcodeStr,
2860 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2861 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2862 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2863 (ins VR128X:$src1, ssmem:$src2),
2864 !strconcat(OpcodeStr,
2865 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2866 [(set VR128X:$dst,
2867 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2868 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2869 }
2870 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2871 (ins FR64X:$src1, FR64X:$src2),
2872 !strconcat(OpcodeStr,
2873 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2874 XD, EVEX_4V, VEX_W;
2875 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2876 (ins VR128X:$src1, VR128X:$src2),
2877 !strconcat(OpcodeStr,
2878 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2879 [(set VR128X:$dst,
2880 (F64Int VR128X:$src1, VR128X:$src2))],
2881 itins_s.rr>, XD, EVEX_4V, VEX_W;
2882 let mayLoad = 1 in {
2883 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2884 (ins FR64X:$src1, f64mem:$src2),
2885 !strconcat(OpcodeStr,
2886 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2887 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2888 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2889 (ins VR128X:$src1, sdmem:$src2),
2890 !strconcat(OpcodeStr,
2891 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2892 [(set VR128X:$dst,
2893 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2894 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2895 }
2896}
2897
2898
2899defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2900 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2901 SSE_SQRTSS, SSE_SQRTSD>,
2902 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2903 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2904 SSE_SQRTPS, SSE_SQRTPD>;
2905
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2906let Predicates = [HasAVX512] in {
2907 def : Pat<(f32 (fsqrt FR32X:$src)),
2908 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2909 def : Pat<(f32 (fsqrt (load addr:$src))),
2910 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2911 Requires<[OptForSize]>;
2912 def : Pat<(f64 (fsqrt FR64X:$src)),
2913 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2914 def : Pat<(f64 (fsqrt (load addr:$src))),
2915 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2916 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2917
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2918 def : Pat<(f32 (X86frsqrt FR32X:$src)),
2919 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2920 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2921 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2922 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2923
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]2924 def : Pat<(f32 (X86frcp FR32X:$src)),
2925 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2926 def : Pat<(f32 (X86frcp (load addr:$src))),
2927 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2928 Requires<[OptForSize]>;
2929
2930 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
2931 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
2932 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2933 VR128X)>;
2934 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2935 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2936
2937 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
2938 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
2939 (COPY_TO_REGCLASS VR128X:$src, FR64)),
2940 VR128X)>;
2941 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2942 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
2943}
2944
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2945
2946multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2947 X86MemOperand x86memop, RegisterClass RC,
2948 PatFrag mem_frag32, PatFrag mem_frag64,
2949 Intrinsic V4F32Int, Intrinsic V2F64Int,
2950 CD8VForm VForm> {
2951let ExeDomain = SSEPackedSingle in {
2952 // Intrinsic operation, reg.
2953 // Vector intrinsic operation, reg
2954 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2955 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2956 !strconcat(OpcodeStr,
2957 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2958 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2959
2960 // Vector intrinsic operation, mem
2961 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2962 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2963 !strconcat(OpcodeStr,
2964 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2965 [(set RC:$dst,
2966 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2967 EVEX_CD8<32, VForm>;
2968} // ExeDomain = SSEPackedSingle
2969
2970let ExeDomain = SSEPackedDouble in {
2971 // Vector intrinsic operation, reg
2972 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2973 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2974 !strconcat(OpcodeStr,
2975 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2976 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2977
2978 // Vector intrinsic operation, mem
2979 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2980 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2981 !strconcat(OpcodeStr,
2982 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2983 [(set RC:$dst,
2984 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2985 EVEX_CD8<64, VForm>;
2986} // ExeDomain = SSEPackedDouble
2987}
2988
2989multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2990 string OpcodeStr,
2991 Intrinsic F32Int,
2992 Intrinsic F64Int> {
2993let ExeDomain = GenericDomain in {
2994 // Operation, reg.
2995 let hasSideEffects = 0 in
2996 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2997 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2998 !strconcat(OpcodeStr,
2999 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3000 []>;
3001
3002 // Intrinsic operation, reg.
3003 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3004 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3005 !strconcat(OpcodeStr,
3006 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3007 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3008
3009 // Intrinsic operation, mem.
3010 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3011 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3012 !strconcat(OpcodeStr,
3013 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3014 [(set VR128X:$dst, (F32Int VR128X:$src1,
3015 sse_load_f32:$src2, imm:$src3))]>,
3016 EVEX_CD8<32, CD8VT1>;
3017
3018 // Operation, reg.
3019 let hasSideEffects = 0 in
3020 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3021 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3022 !strconcat(OpcodeStr,
3023 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3024 []>, VEX_W;
3025
3026 // Intrinsic operation, reg.
3027 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3028 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3029 !strconcat(OpcodeStr,
3030 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3031 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3032 VEX_W;
3033
3034 // Intrinsic operation, mem.
3035 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3036 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3037 !strconcat(OpcodeStr,
3038 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3039 [(set VR128X:$dst,
3040 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3041 VEX_W, EVEX_CD8<64, CD8VT1>;
3042} // ExeDomain = GenericDomain
3043}
3044
3045let Predicates = [HasAVX512] in {
3046 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3047 int_x86_avx512_rndscale_ss,
3048 int_x86_avx512_rndscale_sd>, EVEX_4V;
3049
3050 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3051 memopv16f32, memopv8f64,
3052 int_x86_avx512_rndscale_ps_512,
3053 int_x86_avx512_rndscale_pd_512, CD8VF>,
3054 EVEX, EVEX_V512;
3055}
3056
3057def : Pat<(ffloor FR32X:$src),
3058 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3059def : Pat<(f64 (ffloor FR64X:$src)),
3060 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3061def : Pat<(f32 (fnearbyint FR32X:$src)),
3062 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3063def : Pat<(f64 (fnearbyint FR64X:$src)),
3064 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3065def : Pat<(f32 (fceil FR32X:$src)),
3066 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3067def : Pat<(f64 (fceil FR64X:$src)),
3068 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3069def : Pat<(f32 (frint FR32X:$src)),
3070 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3071def : Pat<(f64 (frint FR64X:$src)),
3072 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3073def : Pat<(f32 (ftrunc FR32X:$src)),
3074 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3075def : Pat<(f64 (ftrunc FR64X:$src)),
3076 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3077
3078def : Pat<(v16f32 (ffloor VR512:$src)),
3079 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3080def : Pat<(v16f32 (fnearbyint VR512:$src)),
3081 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3082def : Pat<(v16f32 (fceil VR512:$src)),
3083 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3084def : Pat<(v16f32 (frint VR512:$src)),
3085 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3086def : Pat<(v16f32 (ftrunc VR512:$src)),
3087 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3088
3089def : Pat<(v8f64 (ffloor VR512:$src)),
3090 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3091def : Pat<(v8f64 (fnearbyint VR512:$src)),
3092 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3093def : Pat<(v8f64 (fceil VR512:$src)),
3094 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3095def : Pat<(v8f64 (frint VR512:$src)),
3096 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3097def : Pat<(v8f64 (ftrunc VR512:$src)),
3098 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3099
3100//-------------------------------------------------
3101// Integer truncate and extend operations
3102//-------------------------------------------------
3103
3104multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3105 RegisterClass dstRC, RegisterClass srcRC,
3106 RegisterClass KRC, X86MemOperand x86memop> {
3107 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3108 (ins srcRC:$src),
3109 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3110 []>, EVEX;
3111
3112 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3113 (ins KRC:$mask, srcRC:$src),
3114 !strconcat(OpcodeStr,
3115 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3116 []>, EVEX, EVEX_KZ;
3117
3118 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3120 []>, EVEX;
3121}
3122defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3123 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3124defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3125 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3126defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3127 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3128defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3129 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3130defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3131 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3132defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3133 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3134defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3135 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3136defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3137 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3138defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3139 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3140defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3141 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3142defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3143 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3144defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3145 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3146defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3147 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3148defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3149 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3150defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3151 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3152
3153def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3154def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3155def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3156def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3157def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3158
3159def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3160 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3161def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3162 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3163def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3164 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3165def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3166 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3167
3168
3169multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3170 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3171 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3172
3173 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3174 (ins SrcRC:$src),
3175 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3176 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3177 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3178 (ins x86memop:$src),
3179 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3180 [(set DstRC:$dst,
3181 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3182 EVEX;
3183}
3184
3185defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3186 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3187 EVEX_CD8<8, CD8VQ>;
3188defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3189 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3190 EVEX_CD8<8, CD8VO>;
3191defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3192 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3193 EVEX_CD8<16, CD8VH>;
3194defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3195 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3196 EVEX_CD8<16, CD8VQ>;
3197defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3198 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3199 EVEX_CD8<32, CD8VH>;
3200
3201defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3202 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3203 EVEX_CD8<8, CD8VQ>;
3204defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3205 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3206 EVEX_CD8<8, CD8VO>;
3207defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3208 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3209 EVEX_CD8<16, CD8VH>;
3210defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3211 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3212 EVEX_CD8<16, CD8VQ>;
3213defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3214 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3215 EVEX_CD8<32, CD8VH>;
3216
3217//===----------------------------------------------------------------------===//
3218// GATHER - SCATTER Operations
3219
3220multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3221 RegisterClass RC, X86MemOperand memop> {
3222let mayLoad = 1,
3223 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3224 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3225 (ins RC:$src1, KRC:$mask, memop:$src2),
3226 !strconcat(OpcodeStr,
3227 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3228 []>, EVEX, EVEX_K;
3229}
3230defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3231 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3232defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3233 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3234
3235defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3236 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3237defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3238 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3239
3240defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3242defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3243 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3244
3245defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3246 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3247defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3248 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3249
3250multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3251 RegisterClass RC, X86MemOperand memop> {
3252let mayStore = 1, Constraints = "$mask = $mask_wb" in
3253 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3254 (ins memop:$dst, KRC:$mask, RC:$src2),
3255 !strconcat(OpcodeStr,
3256 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3257 []>, EVEX, EVEX_K;
3258}
3259
3260defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3261 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3262defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3263 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3264
3265defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3266 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3267defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3268 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3269
3270defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3271 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3272defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3273 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3274
3275defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3276 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3277defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3278 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3279
3280//===----------------------------------------------------------------------===//
3281// VSHUFPS - VSHUFPD Operations
3282
3283multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3284 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3285 Domain d> {
3286 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3287 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3288 !strconcat(OpcodeStr,
3289 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3290 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3291 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3292 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3293 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3294 (ins RC:$src1, RC:$src2, i8imm:$src3),
3295 !strconcat(OpcodeStr,
3296 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3297 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3298 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3299 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3300}
3301
3302defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3303 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3304defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3305 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3306
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3307def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3308 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3309def : Pat<(v16i32 (X86Shufp VR512:$src1,
3310 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3311 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3312
3313def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3314 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3315def : Pat<(v8i64 (X86Shufp VR512:$src1,
3316 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3317 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3318
3319multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3320 X86MemOperand x86memop> {
3321 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3322 (ins RC:$src1, RC:$src2, i8imm:$src3),
3323 !strconcat(OpcodeStr,
3324 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3325 []>, EVEX_4V;
3326 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3327 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3328 !strconcat(OpcodeStr,
3329 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3330 []>, EVEX_4V;
3331}
3332defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3333 EVEX_V512, EVEX_CD8<32, CD8VF>;
3334defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3335 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3336
3337def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3338 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3339def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3340 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3341def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3342 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3343def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3344 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3345
3346multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3347 X86MemOperand x86memop> {
3348 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3349 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3350 EVEX;
3351 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3352 (ins x86memop:$src),
3353 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3354 EVEX;
3355}
3356
3357defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3358 EVEX_CD8<32, CD8VF>;
3359defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3360 EVEX_CD8<64, CD8VF>;
3361