blob: daccc86c709dc6108aad1e5d3ff1e41921c49d6a [file] [log] [blame]
Reid Kleckner08286992018-04-11 16:03:07 +00001; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
Tim Northover00ed9962014-03-29 10:18:08 +00002
3define void @t0(i32 %a) nounwind {
4entry:
5; CHECK: t0
6; CHECK: str {{w[0-9]+}}, [sp, #12]
7; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
8; CHECK-NEXT: str [[REGISTER]], [sp, #12]
9; CHECK: ret
10 %a.addr = alloca i32, align 4
11 store i32 %a, i32* %a.addr
David Blaikiea79ac142015-02-27 21:17:42 +000012 %tmp = load i32, i32* %a.addr
Tim Northover00ed9962014-03-29 10:18:08 +000013 store i32 %tmp, i32* %a.addr
14 ret void
15}
16
17define void @t1(i64 %a) nounwind {
18; CHECK: t1
19; CHECK: str {{x[0-9]+}}, [sp, #8]
20; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
21; CHECK-NEXT: str [[REGISTER]], [sp, #8]
22; CHECK: ret
23 %a.addr = alloca i64, align 4
24 store i64 %a, i64* %a.addr
David Blaikiea79ac142015-02-27 21:17:42 +000025 %tmp = load i64, i64* %a.addr
Tim Northover00ed9962014-03-29 10:18:08 +000026 store i64 %tmp, i64* %a.addr
27 ret void
28}
29
30define zeroext i1 @i1(i1 %a) nounwind {
31entry:
32; CHECK: @i1
Matthias Braunc045c552018-10-29 20:10:42 +000033; CHECK: and [[REG:w[0-9]+]], w0, #0x1
34; CHECK: strb [[REG]], [sp, #15]
35; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15]
36; CHECK: and [[REG2:w[0-9]+]], [[REG1]], #0x1
37; CHECK: and w0, [[REG2]], #0x1
Tim Northover00ed9962014-03-29 10:18:08 +000038; CHECK: add sp, sp, #16
39; CHECK: ret
40 %a.addr = alloca i1, align 1
41 store i1 %a, i1* %a.addr, align 1
David Blaikiea79ac142015-02-27 21:17:42 +000042 %0 = load i1, i1* %a.addr, align 1
Tim Northover00ed9962014-03-29 10:18:08 +000043 ret i1 %0
44}
45
46define i32 @t2(i32 *%ptr) nounwind {
47entry:
48; CHECK-LABEL: t2:
49; CHECK: ldur w0, [x0, #-4]
50; CHECK: ret
David Blaikie79e6c742015-02-27 19:29:02 +000051 %0 = getelementptr i32, i32 *%ptr, i32 -1
David Blaikiea79ac142015-02-27 21:17:42 +000052 %1 = load i32, i32* %0, align 4
Tim Northover00ed9962014-03-29 10:18:08 +000053 ret i32 %1
54}
55
56define i32 @t3(i32 *%ptr) nounwind {
57entry:
58; CHECK-LABEL: t3:
59; CHECK: ldur w0, [x0, #-256]
60; CHECK: ret
David Blaikie79e6c742015-02-27 19:29:02 +000061 %0 = getelementptr i32, i32 *%ptr, i32 -64
David Blaikiea79ac142015-02-27 21:17:42 +000062 %1 = load i32, i32* %0, align 4
Tim Northover00ed9962014-03-29 10:18:08 +000063 ret i32 %1
64}
65
66define void @t4(i32 *%ptr) nounwind {
67entry:
68; CHECK-LABEL: t4:
Juergen Ributzka100a9b72014-08-27 21:04:52 +000069; CHECK: stur wzr, [x0, #-4]
Tim Northover00ed9962014-03-29 10:18:08 +000070; CHECK: ret
David Blaikie79e6c742015-02-27 19:29:02 +000071 %0 = getelementptr i32, i32 *%ptr, i32 -1
Tim Northover00ed9962014-03-29 10:18:08 +000072 store i32 0, i32* %0, align 4
73 ret void
74}
75
76define void @t5(i32 *%ptr) nounwind {
77entry:
78; CHECK-LABEL: t5:
Juergen Ributzka100a9b72014-08-27 21:04:52 +000079; CHECK: stur wzr, [x0, #-256]
Tim Northover00ed9962014-03-29 10:18:08 +000080; CHECK: ret
David Blaikie79e6c742015-02-27 19:29:02 +000081 %0 = getelementptr i32, i32 *%ptr, i32 -64
Tim Northover00ed9962014-03-29 10:18:08 +000082 store i32 0, i32* %0, align 4
83 ret void
84}
85
86define void @t6() nounwind {
87; CHECK: t6
Tim Northover4b2f8a92014-04-30 11:19:28 +000088; CHECK: brk #0x1
Tim Northover00ed9962014-03-29 10:18:08 +000089 tail call void @llvm.trap()
90 ret void
91}
92
93declare void @llvm.trap() nounwind
Quentin Colombet329fa892015-04-30 22:27:20 +000094
95define void @ands(i32* %addr) {
96; CHECK-LABEL: ands:
97; CHECK: tst [[COND:w[0-9]+]], #0x1
Reid Kleckner3a7a2e42018-03-14 21:54:21 +000098; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2
99; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1
Quentin Colombet329fa892015-04-30 22:27:20 +0000100; CHECK-NEXT: csel [[COND]],
101entry:
102 %cond91 = select i1 undef, i32 1, i32 2
103 store i32 %cond91, i32* %addr, align 4
104 ret void
105}
Quentin Colombet9df2fa22015-05-01 20:57:11 +0000106
107define i64 @mul_umul(i64 %arg) {
108; CHECK-LABEL: mul_umul:
109; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
110; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
111entry:
112 %sub.ptr.div = sdiv exact i64 %arg, 8
113 %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
114 %tmp1 = extractvalue { i64, i1 } %tmp, 0
115 ret i64 %tmp1
116}
117
118declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
Quentin Colombet0de23462015-05-01 21:34:57 +0000119
120define void @logicalReg() {
121; Make sure we generate a logical reg = reg, reg instruction without any
122; machine verifier errors.
123; CHECK-LABEL: logicalReg:
124; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
125; CHECK: ret
126entry:
127 br i1 undef, label %cond.end, label %cond.false
128
129cond.false:
130 %cond = select i1 undef, i1 true, i1 false
131 br label %cond.end
132
133cond.end:
134 %cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
135 ret void
136}
137