Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s |
| 2 | |
| 3 | ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: |
Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 4 | ; GCN: v_cmp_eq_u32 |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 5 | ; GCN: s_and_saveexec_b64 |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 6 | ; GCN: ; mask branch [[RET:BB[0-9]+_[0-9]+]] |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 7 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 8 | ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable |
| 9 | ; GCN: ds_write_b32 |
| 10 | ; GCN: ; divergent unreachable |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 11 | |
| 12 | ; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 13 | ; GCN: s_endpgm |
| 14 | |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 15 | define amdgpu_kernel void @lower_control_flow_unreachable_terminator() #0 { |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 16 | bb: |
| 17 | %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y() |
| 18 | %tmp63 = icmp eq i32 %tmp15, 32 |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 19 | br i1 %tmp63, label %unreachable, label %ret |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 20 | |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 21 | unreachable: |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 22 | store volatile i32 0, i32 addrspace(3)* undef, align 4 |
| 23 | unreachable |
| 24 | |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 25 | ret: |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 26 | ret void |
| 27 | } |
| 28 | |
| 29 | ; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order: |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 30 | ; GCN: v_cmp_ne_u32 |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 31 | ; GCN: s_and_saveexec_b64 |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 32 | ; GCN: ; mask branch [[RETURN:BB[0-9]+_[0-9]+]] |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 33 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 34 | ; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 35 | ; GCN: ds_write_b32 |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 36 | ; GCN: ; divergent unreachable |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 37 | |
| 38 | ; GCN: [[RETURN]]: |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 39 | ; GCN-NEXT: s_endpgm |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 40 | define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 { |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 41 | bb: |
| 42 | %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y() |
| 43 | %tmp63 = icmp eq i32 %tmp15, 32 |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 44 | br i1 %tmp63, label %ret, label %unreachable |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 45 | |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 46 | ret: |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 47 | ret void |
| 48 | |
Matt Arsenault | 6bc43d8 | 2016-10-06 16:20:41 +0000 | [diff] [blame] | 49 | unreachable: |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 50 | store volatile i32 0, i32 addrspace(3)* undef, align 4 |
| 51 | unreachable |
| 52 | } |
| 53 | |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 54 | ; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator: |
| 55 | ; GCN: s_cmp_lg_u32 |
| 56 | ; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]] |
| 57 | |
Francis Visoiu Mistrih | 25528d6 | 2017-12-04 17:18:51 +0000 | [diff] [blame] | 58 | ; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 59 | ; GCN-NEXT: s_endpgm |
| 60 | |
| 61 | ; GCN: [[UNREACHABLE]]: |
| 62 | ; GCN: ds_write_b32 |
Matt Arsenault | b8f8dbc | 2017-03-24 19:52:05 +0000 | [diff] [blame] | 63 | define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 { |
| 64 | bb: |
| 65 | %tmp63 = icmp eq i32 %arg0, 32 |
| 66 | br i1 %tmp63, label %unreachable, label %ret |
| 67 | |
| 68 | unreachable: |
| 69 | store volatile i32 0, i32 addrspace(3)* undef, align 4 |
| 70 | unreachable |
| 71 | |
| 72 | ret: |
| 73 | ret void |
| 74 | } |
| 75 | |
Matt Arsenault | 701c21e | 2016-04-29 21:52:13 +0000 | [diff] [blame] | 76 | declare i32 @llvm.amdgcn.workitem.id.y() #1 |
| 77 | |
| 78 | attributes #0 = { nounwind } |
| 79 | attributes #1 = { nounwind readnone } |
| 80 | attributes #2 = { nounwind } |