blob: ce85a66634044c66e5dd6f74fc481453b3eb0a45 [file] [log] [blame]
Matt Arsenault701c21e2016-04-29 21:52:13 +00001; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator:
Matt Arsenault5d8eb252016-09-30 01:50:20 +00004; GCN: v_cmp_eq_u32
Matt Arsenault701c21e2016-04-29 21:52:13 +00005; GCN: s_and_saveexec_b64
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +00006; GCN: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
Matt Arsenault701c21e2016-04-29 21:52:13 +00007
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +00008; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable
9; GCN: ds_write_b32
10; GCN: ; divergent unreachable
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000011
12; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
Matt Arsenault701c21e2016-04-29 21:52:13 +000013; GCN: s_endpgm
14
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000015define amdgpu_kernel void @lower_control_flow_unreachable_terminator() #0 {
Matt Arsenault701c21e2016-04-29 21:52:13 +000016bb:
17 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
18 %tmp63 = icmp eq i32 %tmp15, 32
Matt Arsenault6bc43d82016-10-06 16:20:41 +000019 br i1 %tmp63, label %unreachable, label %ret
Matt Arsenault701c21e2016-04-29 21:52:13 +000020
Matt Arsenault6bc43d82016-10-06 16:20:41 +000021unreachable:
Matt Arsenault701c21e2016-04-29 21:52:13 +000022 store volatile i32 0, i32 addrspace(3)* undef, align 4
23 unreachable
24
Matt Arsenault6bc43d82016-10-06 16:20:41 +000025ret:
Matt Arsenault701c21e2016-04-29 21:52:13 +000026 ret void
27}
28
29; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order:
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000030; GCN: v_cmp_ne_u32
Matt Arsenault701c21e2016-04-29 21:52:13 +000031; GCN: s_and_saveexec_b64
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000032; GCN: ; mask branch [[RETURN:BB[0-9]+_[0-9]+]]
Matt Arsenault701c21e2016-04-29 21:52:13 +000033
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000034; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable
Matt Arsenault701c21e2016-04-29 21:52:13 +000035; GCN: ds_write_b32
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000036; GCN: ; divergent unreachable
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000037
38; GCN: [[RETURN]]:
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000039; GCN-NEXT: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000040define amdgpu_kernel void @lower_control_flow_unreachable_terminator_swap_block_order() #0 {
Matt Arsenault701c21e2016-04-29 21:52:13 +000041bb:
42 %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y()
43 %tmp63 = icmp eq i32 %tmp15, 32
Matt Arsenault6bc43d82016-10-06 16:20:41 +000044 br i1 %tmp63, label %ret, label %unreachable
Matt Arsenault701c21e2016-04-29 21:52:13 +000045
Matt Arsenault6bc43d82016-10-06 16:20:41 +000046ret:
Matt Arsenault701c21e2016-04-29 21:52:13 +000047 ret void
48
Matt Arsenault6bc43d82016-10-06 16:20:41 +000049unreachable:
Matt Arsenault701c21e2016-04-29 21:52:13 +000050 store volatile i32 0, i32 addrspace(3)* undef, align 4
51 unreachable
52}
53
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000054; GCN-LABEL: {{^}}uniform_lower_control_flow_unreachable_terminator:
55; GCN: s_cmp_lg_u32
56; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]]
57
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000058; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000059; GCN-NEXT: s_endpgm
60
61; GCN: [[UNREACHABLE]]:
62; GCN: ds_write_b32
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +000063define amdgpu_kernel void @uniform_lower_control_flow_unreachable_terminator(i32 %arg0) #0 {
64bb:
65 %tmp63 = icmp eq i32 %arg0, 32
66 br i1 %tmp63, label %unreachable, label %ret
67
68unreachable:
69 store volatile i32 0, i32 addrspace(3)* undef, align 4
70 unreachable
71
72ret:
73 ret void
74}
75
Matt Arsenault701c21e2016-04-29 21:52:13 +000076declare i32 @llvm.amdgcn.workitem.id.y() #1
77
78attributes #0 = { nounwind }
79attributes #1 = { nounwind readnone }
80attributes #2 = { nounwind }