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gerrit-public.fairphone.software / toolchain / llvm-project / 16b65394ee3ee612b9a16855d5511630cb3baf1c / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: c8afdacd465539f5414bc0eeb2a5224f1698ba00 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]27#include "llvm/DerivedTypes.h"
28#include "llvm/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]29#include "llvm/MC/MCAsmInfo.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]30#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]31#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]32#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]35#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]36#include <limits>
37
Evan Cheng703a0fb2011-07-01 17:57:27 +0000[diff] [blame]38#define GET_INSTRINFO_CTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]39#include "X86GenInstrInfo.inc"
40
Brian Gaeke960707c2003-11-11 22:41:34 +0000[diff] [blame]41using namespace llvm;
42
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]43static cl::opt<bool>
44NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
46static cl::opt<bool>
47PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
50 cl::Hidden);
51static cl::opt<bool>
52ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]55
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]56enum {
57 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]58 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]59 TB_INDEX_0 = 0,
60 TB_INDEX_1 = 1,
61 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]62 TB_INDEX_3 = 3,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 TB_INDEX_MASK = 0xf,
64
65 // Do not insert the reverse map (MemOp -> RegOp) into the table.
66 // This may be needed because there is a many -> one mapping.
67 TB_NO_REVERSE = 1 << 4,
68
69 // Do not insert the forward map (RegOp -> MemOp) into the table.
70 // This is needed for Native Client, which prohibits branch
71 // instructions from using a memory operand.
72 TB_NO_FORWARD = 1 << 5,
73
74 TB_FOLDED_LOAD = 1 << 6,
75 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76
77 // Minimum alignment required for load/store.
78 // Used for RegOp->MemOp conversion.
79 // (stored in bits 8 - 15)
80 TB_ALIGN_SHIFT = 8,
81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]85};
86
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]87struct X86OpTblEntry {
88 uint16_t RegOp;
89 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]90 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]91};
92
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]93X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
Evan Cheng703a0fb2011-07-01 17:57:27 +0000[diff] [blame]94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
95 ? X86::ADJCALLSTACKDOWN64
96 : X86::ADJCALLSTACKDOWN32),
97 (tm.getSubtarget<X86Subtarget>().is64Bit()
98 ? X86::ADJCALLSTACKUP64
99 : X86::ADJCALLSTACKUP32)),
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]100 TM(tm), RI(tm, *this) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]101
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]102 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]103 { X86::ADC32ri, X86::ADC32mi, 0 },
104 { X86::ADC32ri8, X86::ADC32mi8, 0 },
105 { X86::ADC32rr, X86::ADC32mr, 0 },
106 { X86::ADC64ri32, X86::ADC64mi32, 0 },
107 { X86::ADC64ri8, X86::ADC64mi8, 0 },
108 { X86::ADC64rr, X86::ADC64mr, 0 },
109 { X86::ADD16ri, X86::ADD16mi, 0 },
110 { X86::ADD16ri8, X86::ADD16mi8, 0 },
111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
113 { X86::ADD16rr, X86::ADD16mr, 0 },
114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
115 { X86::ADD32ri, X86::ADD32mi, 0 },
116 { X86::ADD32ri8, X86::ADD32mi8, 0 },
117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
119 { X86::ADD32rr, X86::ADD32mr, 0 },
120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
121 { X86::ADD64ri32, X86::ADD64mi32, 0 },
122 { X86::ADD64ri8, X86::ADD64mi8, 0 },
123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
125 { X86::ADD64rr, X86::ADD64mr, 0 },
126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
127 { X86::ADD8ri, X86::ADD8mi, 0 },
128 { X86::ADD8rr, X86::ADD8mr, 0 },
129 { X86::AND16ri, X86::AND16mi, 0 },
130 { X86::AND16ri8, X86::AND16mi8, 0 },
131 { X86::AND16rr, X86::AND16mr, 0 },
132 { X86::AND32ri, X86::AND32mi, 0 },
133 { X86::AND32ri8, X86::AND32mi8, 0 },
134 { X86::AND32rr, X86::AND32mr, 0 },
135 { X86::AND64ri32, X86::AND64mi32, 0 },
136 { X86::AND64ri8, X86::AND64mi8, 0 },
137 { X86::AND64rr, X86::AND64mr, 0 },
138 { X86::AND8ri, X86::AND8mi, 0 },
139 { X86::AND8rr, X86::AND8mr, 0 },
140 { X86::DEC16r, X86::DEC16m, 0 },
141 { X86::DEC32r, X86::DEC32m, 0 },
142 { X86::DEC64_16r, X86::DEC64_16m, 0 },
143 { X86::DEC64_32r, X86::DEC64_32m, 0 },
144 { X86::DEC64r, X86::DEC64m, 0 },
145 { X86::DEC8r, X86::DEC8m, 0 },
146 { X86::INC16r, X86::INC16m, 0 },
147 { X86::INC32r, X86::INC32m, 0 },
148 { X86::INC64_16r, X86::INC64_16m, 0 },
149 { X86::INC64_32r, X86::INC64_32m, 0 },
150 { X86::INC64r, X86::INC64m, 0 },
151 { X86::INC8r, X86::INC8m, 0 },
152 { X86::NEG16r, X86::NEG16m, 0 },
153 { X86::NEG32r, X86::NEG32m, 0 },
154 { X86::NEG64r, X86::NEG64m, 0 },
155 { X86::NEG8r, X86::NEG8m, 0 },
156 { X86::NOT16r, X86::NOT16m, 0 },
157 { X86::NOT32r, X86::NOT32m, 0 },
158 { X86::NOT64r, X86::NOT64m, 0 },
159 { X86::NOT8r, X86::NOT8m, 0 },
160 { X86::OR16ri, X86::OR16mi, 0 },
161 { X86::OR16ri8, X86::OR16mi8, 0 },
162 { X86::OR16rr, X86::OR16mr, 0 },
163 { X86::OR32ri, X86::OR32mi, 0 },
164 { X86::OR32ri8, X86::OR32mi8, 0 },
165 { X86::OR32rr, X86::OR32mr, 0 },
166 { X86::OR64ri32, X86::OR64mi32, 0 },
167 { X86::OR64ri8, X86::OR64mi8, 0 },
168 { X86::OR64rr, X86::OR64mr, 0 },
169 { X86::OR8ri, X86::OR8mi, 0 },
170 { X86::OR8rr, X86::OR8mr, 0 },
171 { X86::ROL16r1, X86::ROL16m1, 0 },
172 { X86::ROL16rCL, X86::ROL16mCL, 0 },
173 { X86::ROL16ri, X86::ROL16mi, 0 },
174 { X86::ROL32r1, X86::ROL32m1, 0 },
175 { X86::ROL32rCL, X86::ROL32mCL, 0 },
176 { X86::ROL32ri, X86::ROL32mi, 0 },
177 { X86::ROL64r1, X86::ROL64m1, 0 },
178 { X86::ROL64rCL, X86::ROL64mCL, 0 },
179 { X86::ROL64ri, X86::ROL64mi, 0 },
180 { X86::ROL8r1, X86::ROL8m1, 0 },
181 { X86::ROL8rCL, X86::ROL8mCL, 0 },
182 { X86::ROL8ri, X86::ROL8mi, 0 },
183 { X86::ROR16r1, X86::ROR16m1, 0 },
184 { X86::ROR16rCL, X86::ROR16mCL, 0 },
185 { X86::ROR16ri, X86::ROR16mi, 0 },
186 { X86::ROR32r1, X86::ROR32m1, 0 },
187 { X86::ROR32rCL, X86::ROR32mCL, 0 },
188 { X86::ROR32ri, X86::ROR32mi, 0 },
189 { X86::ROR64r1, X86::ROR64m1, 0 },
190 { X86::ROR64rCL, X86::ROR64mCL, 0 },
191 { X86::ROR64ri, X86::ROR64mi, 0 },
192 { X86::ROR8r1, X86::ROR8m1, 0 },
193 { X86::ROR8rCL, X86::ROR8mCL, 0 },
194 { X86::ROR8ri, X86::ROR8mi, 0 },
195 { X86::SAR16r1, X86::SAR16m1, 0 },
196 { X86::SAR16rCL, X86::SAR16mCL, 0 },
197 { X86::SAR16ri, X86::SAR16mi, 0 },
198 { X86::SAR32r1, X86::SAR32m1, 0 },
199 { X86::SAR32rCL, X86::SAR32mCL, 0 },
200 { X86::SAR32ri, X86::SAR32mi, 0 },
201 { X86::SAR64r1, X86::SAR64m1, 0 },
202 { X86::SAR64rCL, X86::SAR64mCL, 0 },
203 { X86::SAR64ri, X86::SAR64mi, 0 },
204 { X86::SAR8r1, X86::SAR8m1, 0 },
205 { X86::SAR8rCL, X86::SAR8mCL, 0 },
206 { X86::SAR8ri, X86::SAR8mi, 0 },
207 { X86::SBB32ri, X86::SBB32mi, 0 },
208 { X86::SBB32ri8, X86::SBB32mi8, 0 },
209 { X86::SBB32rr, X86::SBB32mr, 0 },
210 { X86::SBB64ri32, X86::SBB64mi32, 0 },
211 { X86::SBB64ri8, X86::SBB64mi8, 0 },
212 { X86::SBB64rr, X86::SBB64mr, 0 },
213 { X86::SHL16rCL, X86::SHL16mCL, 0 },
214 { X86::SHL16ri, X86::SHL16mi, 0 },
215 { X86::SHL32rCL, X86::SHL32mCL, 0 },
216 { X86::SHL32ri, X86::SHL32mi, 0 },
217 { X86::SHL64rCL, X86::SHL64mCL, 0 },
218 { X86::SHL64ri, X86::SHL64mi, 0 },
219 { X86::SHL8rCL, X86::SHL8mCL, 0 },
220 { X86::SHL8ri, X86::SHL8mi, 0 },
221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
227 { X86::SHR16r1, X86::SHR16m1, 0 },
228 { X86::SHR16rCL, X86::SHR16mCL, 0 },
229 { X86::SHR16ri, X86::SHR16mi, 0 },
230 { X86::SHR32r1, X86::SHR32m1, 0 },
231 { X86::SHR32rCL, X86::SHR32mCL, 0 },
232 { X86::SHR32ri, X86::SHR32mi, 0 },
233 { X86::SHR64r1, X86::SHR64m1, 0 },
234 { X86::SHR64rCL, X86::SHR64mCL, 0 },
235 { X86::SHR64ri, X86::SHR64mi, 0 },
236 { X86::SHR8r1, X86::SHR8m1, 0 },
237 { X86::SHR8rCL, X86::SHR8mCL, 0 },
238 { X86::SHR8ri, X86::SHR8mi, 0 },
239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
245 { X86::SUB16ri, X86::SUB16mi, 0 },
246 { X86::SUB16ri8, X86::SUB16mi8, 0 },
247 { X86::SUB16rr, X86::SUB16mr, 0 },
248 { X86::SUB32ri, X86::SUB32mi, 0 },
249 { X86::SUB32ri8, X86::SUB32mi8, 0 },
250 { X86::SUB32rr, X86::SUB32mr, 0 },
251 { X86::SUB64ri32, X86::SUB64mi32, 0 },
252 { X86::SUB64ri8, X86::SUB64mi8, 0 },
253 { X86::SUB64rr, X86::SUB64mr, 0 },
254 { X86::SUB8ri, X86::SUB8mi, 0 },
255 { X86::SUB8rr, X86::SUB8mr, 0 },
256 { X86::XOR16ri, X86::XOR16mi, 0 },
257 { X86::XOR16ri8, X86::XOR16mi8, 0 },
258 { X86::XOR16rr, X86::XOR16mr, 0 },
259 { X86::XOR32ri, X86::XOR32mi, 0 },
260 { X86::XOR32ri8, X86::XOR32mi8, 0 },
261 { X86::XOR32rr, X86::XOR32mr, 0 },
262 { X86::XOR64ri32, X86::XOR64mi32, 0 },
263 { X86::XOR64ri8, X86::XOR64mi8, 0 },
264 { X86::XOR64rr, X86::XOR64mr, 0 },
265 { X86::XOR8ri, X86::XOR8mi, 0 },
266 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]267 };
268
269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]270 unsigned RegOp = OpTbl2Addr[i].RegOp;
271 unsigned MemOp = OpTbl2Addr[i].MemOp;
272 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274 RegOp, MemOp,
275 // Index 0, folded load and store, no alignment requirement.
276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]277 }
278
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]279 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
357 // AVX 128-bit versions of foldable instructions
358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
371 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]378 };
379
380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]381 unsigned RegOp = OpTbl0[i].RegOp;
382 unsigned MemOp = OpTbl0[i].MemOp;
383 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]386 }
387
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]388 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]389 { X86::CMP16rr, X86::CMP16rm, 0 },
390 { X86::CMP32rr, X86::CMP32rm, 0 },
391 { X86::CMP64rr, X86::CMP64rm, 0 },
392 { X86::CMP8rr, X86::CMP8rm, 0 },
393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]405 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
407 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]417 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
418 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
419 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
420 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
421 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
422 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
423 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
424 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]425 { X86::MOV16rr, X86::MOV16rm, 0 },
426 { X86::MOV32rr, X86::MOV32rm, 0 },
427 { X86::MOV64rr, X86::MOV64rm, 0 },
428 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
429 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
430 { X86::MOV8rr, X86::MOV8rm, 0 },
431 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
432 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]433 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
434 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
435 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
436 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]437 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
438 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
439 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
440 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
441 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
442 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
443 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
444 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
445 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
446 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]447 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
454 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
455 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
456 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]457 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
458 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
459 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]460 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
461 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
462 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
463 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
464 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
465 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
466 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
467 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
468 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
469 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
470 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
471 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
472 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
473 { X86::SQRTSDr, X86::SQRTSDm, 0 },
474 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
475 { X86::SQRTSSr, X86::SQRTSSm, 0 },
476 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
477 { X86::TEST16rr, X86::TEST16rm, 0 },
478 { X86::TEST32rr, X86::TEST32rm, 0 },
479 { X86::TEST64rr, X86::TEST64rm, 0 },
480 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]481 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]482 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
483 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]484 // AVX 128-bit versions of foldable instructions
485 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
486 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]487 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
488 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]489 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
490 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]491 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]492 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
493 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
494 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
495 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
496 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
497 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
498 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
499 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
500 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]501 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
502 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
503 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
504 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
505 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
506 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
507 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
508 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
509 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
510 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
511 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
512 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
513 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
514 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
515 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
516 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
517 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]518 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
519 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
520 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]521 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]522 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]523 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
524 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
525 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
526 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
527 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
528 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
529 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
530 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
531 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
532 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
533 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]534 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]535 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]536 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
537
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]538 // AVX 256-bit foldable instructions
539 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
540 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]541 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]542 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]543 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]544 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 },
545 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]546
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]547 // AVX2 foldable instructions
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]548 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 },
549 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 },
550 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 },
551 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 },
552 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 },
553 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 },
554 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 },
555 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 },
556 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 },
557 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 },
558 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 },
559 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 },
560 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 },
561 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]562 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
563 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]564
565 // BMI/BMI2 foldable instructions
566 { X86::RORX32ri, X86::RORX32mi, 0 },
567 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]568 { X86::SARX32rr, X86::SARX32rm, 0 },
569 { X86::SARX64rr, X86::SARX64rm, 0 },
570 { X86::SHRX32rr, X86::SHRX32rm, 0 },
571 { X86::SHRX64rr, X86::SHRX64rm, 0 },
572 { X86::SHLX32rr, X86::SHLX32rm, 0 },
573 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]574 };
575
576 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]577 unsigned RegOp = OpTbl1[i].RegOp;
578 unsigned MemOp = OpTbl1[i].MemOp;
579 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]580 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
581 RegOp, MemOp,
582 // Index 1, folded load
583 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]584 }
585
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]586 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]587 { X86::ADC32rr, X86::ADC32rm, 0 },
588 { X86::ADC64rr, X86::ADC64rm, 0 },
589 { X86::ADD16rr, X86::ADD16rm, 0 },
590 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
591 { X86::ADD32rr, X86::ADD32rm, 0 },
592 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
593 { X86::ADD64rr, X86::ADD64rm, 0 },
594 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
595 { X86::ADD8rr, X86::ADD8rm, 0 },
596 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
597 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
598 { X86::ADDSDrr, X86::ADDSDrm, 0 },
599 { X86::ADDSSrr, X86::ADDSSrm, 0 },
600 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
601 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
602 { X86::AND16rr, X86::AND16rm, 0 },
603 { X86::AND32rr, X86::AND32rm, 0 },
604 { X86::AND64rr, X86::AND64rm, 0 },
605 { X86::AND8rr, X86::AND8rm, 0 },
606 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
607 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
608 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
609 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]610 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
611 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
612 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
613 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]614 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
615 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
616 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
617 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
618 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
619 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
620 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
621 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
622 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
623 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
624 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
625 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
626 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
627 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
628 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
629 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
630 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
631 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
632 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
633 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
634 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
635 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
636 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
637 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
638 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
639 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
640 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
641 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
642 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
643 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
644 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
645 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
646 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
647 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
648 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
649 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
650 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
651 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
652 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
653 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
654 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
655 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
656 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
657 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
658 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
659 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
660 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
661 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
662 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
663 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
664 { X86::CMPSDrr, X86::CMPSDrm, 0 },
665 { X86::CMPSSrr, X86::CMPSSrm, 0 },
666 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
667 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
668 { X86::DIVSDrr, X86::DIVSDrm, 0 },
669 { X86::DIVSSrr, X86::DIVSSrm, 0 },
670 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
671 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
672 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
673 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
674 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
675 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
676 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
677 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
678 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
679 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
680 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
681 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
682 { X86::IMUL16rr, X86::IMUL16rm, 0 },
683 { X86::IMUL32rr, X86::IMUL32rm, 0 },
684 { X86::IMUL64rr, X86::IMUL64rm, 0 },
685 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
686 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]687 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
688 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
689 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
690 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
691 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
692 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]693 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
694 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
695 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
696 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
697 { X86::MAXSDrr, X86::MAXSDrm, 0 },
698 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
699 { X86::MAXSSrr, X86::MAXSSrm, 0 },
700 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
701 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
702 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
703 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
704 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
705 { X86::MINSDrr, X86::MINSDrm, 0 },
706 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
707 { X86::MINSSrr, X86::MINSSrm, 0 },
708 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]709 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]710 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
711 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
712 { X86::MULSDrr, X86::MULSDrm, 0 },
713 { X86::MULSSrr, X86::MULSSrm, 0 },
714 { X86::OR16rr, X86::OR16rm, 0 },
715 { X86::OR32rr, X86::OR32rm, 0 },
716 { X86::OR64rr, X86::OR64rm, 0 },
717 { X86::OR8rr, X86::OR8rm, 0 },
718 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
719 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
720 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
721 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]722 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]723 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
724 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
725 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
726 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
727 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
728 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]729 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
730 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]731 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]732 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]733 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
734 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
735 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
736 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]737 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]738 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
739 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]740 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]741 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
742 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
743 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]744 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]745 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]746 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
747 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]748 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]749 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]750 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]751 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]752 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]753 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]754 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
755 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
756 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
757 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
758 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
759 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]760 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]761 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
762 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
763 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
764 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
765 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
766 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
767 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]768 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
769 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
770 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
771 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]772 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
773 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
774 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
775 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
776 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
777 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
778 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
779 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
780 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
781 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
782 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
783 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
784 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
785 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
786 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
787 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
788 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
789 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
790 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
791 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
792 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
793 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
794 { X86::SBB32rr, X86::SBB32rm, 0 },
795 { X86::SBB64rr, X86::SBB64rm, 0 },
796 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
797 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
798 { X86::SUB16rr, X86::SUB16rm, 0 },
799 { X86::SUB32rr, X86::SUB32rm, 0 },
800 { X86::SUB64rr, X86::SUB64rm, 0 },
801 { X86::SUB8rr, X86::SUB8rm, 0 },
802 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
803 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
804 { X86::SUBSDrr, X86::SUBSDrm, 0 },
805 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]806 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]807 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
808 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
809 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
810 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
811 { X86::XOR16rr, X86::XOR16rm, 0 },
812 { X86::XOR32rr, X86::XOR32rm, 0 },
813 { X86::XOR64rr, X86::XOR64rm, 0 },
814 { X86::XOR8rr, X86::XOR8rm, 0 },
815 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]816 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
817 // AVX 128-bit versions of foldable instructions
818 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
819 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
820 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
821 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
822 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
823 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
824 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
825 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
826 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
827 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
828 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
829 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Craig Topperb6eb5132012-06-25 06:16:00 +0000[diff] [blame]830 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]831 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
832 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
833 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
834 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
835 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
836 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
837 { X86::VADDSDrr, X86::VADDSDrm, 0 },
838 { X86::VADDSSrr, X86::VADDSSrm, 0 },
839 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
840 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
841 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
842 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
843 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
844 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]845 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 },
846 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 },
847 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 },
848 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]849 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
850 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
851 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
852 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
853 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
854 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
855 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
856 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
857 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
858 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
859 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
860 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
861 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
862 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
863 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
864 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
865 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
866 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
867 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
868 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
869 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
870 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
871 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
872 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
873 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
874 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
875 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
876 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
877 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
878 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
879 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
880 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
881 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
882 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
883 { X86::VMINSDrr, X86::VMINSDrm, 0 },
884 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
885 { X86::VMINSSrr, X86::VMINSSrm, 0 },
886 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]887 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]888 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
889 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
890 { X86::VMULSDrr, X86::VMULSDrm, 0 },
891 { X86::VMULSSrr, X86::VMULSSrm, 0 },
892 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
893 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
894 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
895 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]896 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]897 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
898 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
899 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
900 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
901 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
902 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]903 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
904 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]905 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]906 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]907 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
908 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]909 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
910 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]911 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]912 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
913 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]914 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]915 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
916 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
917 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]918 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]919 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]920 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]921 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]922 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 },
923 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]924 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]925 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]926 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 },
927 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]928 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]929 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]930 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
931 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
932 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
933 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
934 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
935 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]936 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]937 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
938 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
939 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
940 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
941 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
942 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
943 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]944 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 },
945 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 },
946 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 },
947 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]948 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
949 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
950 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
951 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
952 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
953 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
954 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
955 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
956 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
957 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
958 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
959 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
960 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
961 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
962 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
963 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
964 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
965 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
966 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
967 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
968 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
969 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
970 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
971 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
972 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
973 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
974 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
975 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
976 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
977 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
978 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
979 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
980 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]981 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]982 // AVX 256-bit foldable instructions
983 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 },
984 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 },
985 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 },
986 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 },
987 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 },
988 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 },
989 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 },
990 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 },
991 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 },
992 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 },
993 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 },
994 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 },
995 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 },
996 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 },
997 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 },
998 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 },
999 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 },
1000 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 },
1001 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 },
1002 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 },
1003 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 },
1004 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 },
1005 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 },
1006 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 },
1007 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 },
1008 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 },
1009 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 },
1010 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 },
1011 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 },
1012 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 },
1013 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 },
1014 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 },
1015 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 },
1016 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 },
1017 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 },
1018 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 },
1019 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 },
1020 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 },
1021 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 },
1022 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 },
1023 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 },
1024 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 },
1025 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 },
1026 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 },
1027 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 },
1028 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1029 // AVX2 foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1030 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 },
1031 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 },
1032 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 },
1033 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 },
1034 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 },
1035 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 },
1036 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 },
1037 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 },
1038 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 },
1039 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 },
1040 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 },
1041 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 },
1042 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 },
1043 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 },
1044 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 },
1045 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 },
1046 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 },
1047 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 },
1048 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 },
1049 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 },
1050 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 },
1051 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 },
1052 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 },
1053 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 },
1054 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 },
1055 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 },
1056 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 },
1057 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 },
1058 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 },
1059 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]1060 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 },
Elena Demikhovsky779a72b2012-04-15 11:18:59 +0000[diff] [blame]1061 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]1062 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 },
Elena Demikhovsky779a72b2012-04-15 11:18:59 +0000[diff] [blame]1063 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1064 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1065 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1066 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 },
1067 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1068 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1069 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1070 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 },
1071 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 },
1072 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 },
1073 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 },
1074 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 },
1075 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 },
1076 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 },
1077 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 },
1078 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 },
1079 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 },
1080 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 },
1081 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 },
1082 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 },
1083 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
1084 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
1085 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1086 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 },
1087 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 },
1088 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 },
1089 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1090 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
1091 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
1092 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
1093 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1094 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1095 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1096 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1097 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1098 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1099 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1100 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1101 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1102 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1103 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1104 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1105 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1106 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1107 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 },
1108 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 },
1109 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 },
1110 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 },
1111 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 },
1112 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 },
1113 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 },
1114 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1115 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1116 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 },
1117 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 },
1118 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 },
1119 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 },
1120 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 },
1121 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1122 // FIXME: add AVX 256-bit foldable instructions
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1123
1124 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1125 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 },
1126 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1127 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 },
1128 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 },
1129 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 },
1130 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1131 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 },
1132 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1133 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 },
1134 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 },
1135 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 },
1136 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1137 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 },
1138 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1139 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 },
1140 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 },
1141 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 },
1142 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1143 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 },
1144 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1145 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 },
1146 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 },
1147 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 },
1148 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 },
1149 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 },
1150 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 },
1151 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 },
1152 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 },
1153 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 },
1154 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 },
1155 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 },
1156 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1157
1158 // BMI/BMI2 foldable instructions
1159 { X86::MULX32rr, X86::MULX32rm, 0 },
1160 { X86::MULX64rr, X86::MULX64rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1161 };
1162
1163 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1164 unsigned RegOp = OpTbl2[i].RegOp;
1165 unsigned MemOp = OpTbl2[i].MemOp;
1166 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1167 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1168 RegOp, MemOp,
1169 // Index 2, folded load
1170 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1171 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1172
1173 static const X86OpTblEntry OpTbl3[] = {
1174 // FMA foldable instructions
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1175 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 },
1176 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 },
1177 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 },
1178 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 },
1179 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 },
1180 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 },
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]1181 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 },
1182 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1183
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1184 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 },
1185 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 },
1186 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 },
1187 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 },
1188 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 },
1189 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 },
1190 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 },
1191 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 },
1192 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 },
1193 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
1194 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
1195 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1196
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1197 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
1198 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
1199 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 },
1200 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 },
1201 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 },
1202 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 },
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]1203 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 },
1204 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1205
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1206 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 },
1207 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 },
1208 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 },
1209 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 },
1210 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 },
1211 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 },
1212 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 },
1213 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 },
1214 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 },
1215 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
1216 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
1217 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1218
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1219 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
1220 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
1221 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 },
1222 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 },
1223 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 },
1224 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 },
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]1225 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 },
1226 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1227
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1228 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 },
1229 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 },
1230 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 },
1231 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 },
1232 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 },
1233 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 },
1234 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 },
1235 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 },
1236 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 },
1237 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
1238 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
1239 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1240
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1241 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 },
1242 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 },
1243 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 },
1244 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 },
1245 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 },
1246 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 },
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]1247 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 },
1248 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1249
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1250 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 },
1251 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 },
1252 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 },
1253 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 },
1254 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 },
1255 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 },
1256 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 },
1257 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 },
1258 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 },
1259 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 },
1260 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 },
1261 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1262
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1263 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 },
1264 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 },
1265 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 },
1266 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 },
1267 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 },
1268 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 },
1269 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 },
1270 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 },
1271 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 },
1272 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 },
1273 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 },
1274 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1275
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame]1276 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 },
1277 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 },
1278 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 },
1279 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 },
1280 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 },
1281 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 },
1282 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 },
1283 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 },
1284 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 },
1285 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 },
1286 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 },
1287 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1288
1289 // FMA4 foldable patterns
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1290 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 },
1291 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1292 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 },
1293 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 },
1294 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 },
1295 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1296 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 },
1297 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1298 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 },
1299 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 },
1300 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 },
1301 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1302 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 },
1303 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1304 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 },
1305 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 },
1306 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 },
1307 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 },
Craig Topper3b530ea2012-11-04 04:40:08 +0000[diff] [blame]1308 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 },
1309 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1310 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 },
1311 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 },
1312 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 },
1313 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 },
1314 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 },
1315 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 },
1316 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 },
1317 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 },
1318 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 },
1319 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 },
1320 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 },
1321 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1322 };
1323
1324 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1325 unsigned RegOp = OpTbl3[i].RegOp;
1326 unsigned MemOp = OpTbl3[i].MemOp;
1327 unsigned Flags = OpTbl3[i].Flags;
1328 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1329 RegOp, MemOp,
1330 // Index 3, folded load
1331 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1332 }
1333
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1334}
1335
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1336void
1337X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1338 MemOp2RegOpTableType &M2RTable,
1339 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1340 if ((Flags & TB_NO_FORWARD) == 0) {
1341 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1342 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1343 }
1344 if ((Flags & TB_NO_REVERSE) == 0) {
1345 assert(!M2RTable.count(MemOp) &&
1346 "Duplicated entries in unfolding maps?");
1347 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1348 }
1349}
1350
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1351bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1352X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1353 unsigned &SrcReg, unsigned &DstReg,
1354 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1355 switch (MI.getOpcode()) {
1356 default: break;
1357 case X86::MOVSX16rr8:
1358 case X86::MOVZX16rr8:
1359 case X86::MOVSX32rr8:
1360 case X86::MOVZX32rr8:
1361 case X86::MOVSX64rr8:
1362 case X86::MOVZX64rr8:
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1363 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1364 // It's not always legal to reference the low 8-bit of the larger
1365 // register in 32-bit mode.
1366 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1367 case X86::MOVSX32rr16:
1368 case X86::MOVZX32rr16:
1369 case X86::MOVSX64rr16:
1370 case X86::MOVZX64rr16:
1371 case X86::MOVSX64rr32:
1372 case X86::MOVZX64rr32: {
1373 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1374 // Be conservative.
1375 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1376 SrcReg = MI.getOperand(1).getReg();
1377 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1378 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1379 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1380 case X86::MOVSX16rr8:
1381 case X86::MOVZX16rr8:
1382 case X86::MOVSX32rr8:
1383 case X86::MOVZX32rr8:
1384 case X86::MOVSX64rr8:
1385 case X86::MOVZX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1386 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1387 break;
1388 case X86::MOVSX32rr16:
1389 case X86::MOVZX32rr16:
1390 case X86::MOVSX64rr16:
1391 case X86::MOVZX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1392 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1393 break;
1394 case X86::MOVSX64rr32:
1395 case X86::MOVZX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1396 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1397 break;
1398 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1399 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1400 }
1401 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1402 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1403}
1404
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1405/// isFrameOperand - Return true and the FrameIndex if the specified
1406/// operand and follow operands form a reference to the stack frame.
1407bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1408 int &FrameIndex) const {
1409 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1410 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1411 MI->getOperand(Op+1).getImm() == 1 &&
1412 MI->getOperand(Op+2).getReg() == 0 &&
1413 MI->getOperand(Op+3).getImm() == 0) {
1414 FrameIndex = MI->getOperand(Op).getIndex();
1415 return true;
1416 }
1417 return false;
1418}
1419
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1420static bool isFrameLoadOpcode(int Opcode) {
1421 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]1422 default:
1423 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1424 case X86::MOV8rm:
1425 case X86::MOV16rm:
1426 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]1427 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]1428 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1429 case X86::MOVSSrm:
1430 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]1431 case X86::MOVAPSrm:
1432 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1433 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1434 case X86::VMOVSSrm:
1435 case X86::VMOVSDrm:
1436 case X86::VMOVAPSrm:
1437 case X86::VMOVAPDrm:
1438 case X86::VMOVDQArm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1439 case X86::VMOVAPSYrm:
1440 case X86::VMOVAPDYrm:
1441 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]1442 case X86::MMX_MOVD64rm:
1443 case X86::MMX_MOVQ64rm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1444 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1445 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1446}
1447
1448static bool isFrameStoreOpcode(int Opcode) {
1449 switch (Opcode) {
1450 default: break;
1451 case X86::MOV8mr:
1452 case X86::MOV16mr:
1453 case X86::MOV32mr:
1454 case X86::MOV64mr:
1455 case X86::ST_FpP64m:
1456 case X86::MOVSSmr:
1457 case X86::MOVSDmr:
1458 case X86::MOVAPSmr:
1459 case X86::MOVAPDmr:
1460 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1461 case X86::VMOVSSmr:
1462 case X86::VMOVSDmr:
1463 case X86::VMOVAPSmr:
1464 case X86::VMOVAPDmr:
1465 case X86::VMOVDQAmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1466 case X86::VMOVAPSYmr:
1467 case X86::VMOVAPDYmr:
1468 case X86::VMOVDQAYmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1469 case X86::MMX_MOVD64mr:
1470 case X86::MMX_MOVQ64mr:
1471 case X86::MMX_MOVNTQmr:
1472 return true;
1473 }
1474 return false;
1475}
1476
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1477unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1478 int &FrameIndex) const {
1479 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1480 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1481 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1482 return 0;
1483}
1484
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1485unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1486 int &FrameIndex) const {
1487 if (isFrameLoadOpcode(MI->getOpcode())) {
1488 unsigned Reg;
1489 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1490 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1491 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1492 const MachineMemOperand *Dummy;
1493 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1494 }
1495 return 0;
1496}
1497
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]1498unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1499 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1500 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1501 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1502 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]1503 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1504 return 0;
1505}
1506
1507unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1508 int &FrameIndex) const {
1509 if (isFrameStoreOpcode(MI->getOpcode())) {
1510 unsigned Reg;
1511 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1512 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1513 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1514 const MachineMemOperand *Dummy;
1515 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1516 }
1517 return 0;
1518}
1519
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1520/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1521/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1522static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]1523 // Don't waste compile time scanning use-def chains of physregs.
1524 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1525 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1526 bool isPICBase = false;
1527 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1528 E = MRI.def_end(); I != E; ++I) {
1529 MachineInstr *DefMI = I.getOperand().getParent();
1530 if (DefMI->getOpcode() != X86::MOVPC32r)
1531 return false;
1532 assert(!isPICBase && "More than one PIC base?");
1533 isPICBase = true;
1534 }
1535 return isPICBase;
1536}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]1537
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]1538bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1539X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1540 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1541 switch (MI->getOpcode()) {
1542 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1543 case X86::MOV8rm:
1544 case X86::MOV16rm:
1545 case X86::MOV32rm:
1546 case X86::MOV64rm:
1547 case X86::LD_Fp64m:
1548 case X86::MOVSSrm:
1549 case X86::MOVSDrm:
1550 case X86::MOVAPSrm:
1551 case X86::MOVUPSrm:
1552 case X86::MOVAPDrm:
1553 case X86::MOVDQArm:
1554 case X86::VMOVSSrm:
1555 case X86::VMOVSDrm:
1556 case X86::VMOVAPSrm:
1557 case X86::VMOVUPSrm:
1558 case X86::VMOVAPDrm:
1559 case X86::VMOVDQArm:
1560 case X86::VMOVAPSYrm:
1561 case X86::VMOVUPSYrm:
1562 case X86::VMOVAPDYrm:
1563 case X86::VMOVDQAYrm:
1564 case X86::MMX_MOVD64rm:
1565 case X86::MMX_MOVQ64rm:
1566 case X86::FsVMOVAPSrm:
1567 case X86::FsVMOVAPDrm:
1568 case X86::FsMOVAPSrm:
1569 case X86::FsMOVAPDrm: {
1570 // Loads from constant pools are trivially rematerializable.
1571 if (MI->getOperand(1).isReg() &&
1572 MI->getOperand(2).isImm() &&
1573 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1574 MI->isInvariantLoad(AA)) {
1575 unsigned BaseReg = MI->getOperand(1).getReg();
1576 if (BaseReg == 0 || BaseReg == X86::RIP)
1577 return true;
1578 // Allow re-materialization of PIC load.
1579 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1580 return false;
1581 const MachineFunction &MF = *MI->getParent()->getParent();
1582 const MachineRegisterInfo &MRI = MF.getRegInfo();
1583 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]1584 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1585 return false;
1586 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1587
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]1588 case X86::LEA32r:
1589 case X86::LEA64r: {
1590 if (MI->getOperand(2).isImm() &&
1591 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1592 !MI->getOperand(4).isReg()) {
1593 // lea fi#, lea GV, etc. are all rematerializable.
1594 if (!MI->getOperand(1).isReg())
1595 return true;
1596 unsigned BaseReg = MI->getOperand(1).getReg();
1597 if (BaseReg == 0)
1598 return true;
1599 // Allow re-materialization of lea PICBase + x.
1600 const MachineFunction &MF = *MI->getParent()->getParent();
1601 const MachineRegisterInfo &MRI = MF.getRegInfo();
1602 return regIsPICBase(BaseReg, MRI);
1603 }
1604 return false;
1605 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1606 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1607
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]1608 // All other instructions marked M_REMATERIALIZABLE are always trivially
1609 // rematerializable.
1610 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1611}
1612
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1613/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1614/// would clobber the EFLAGS condition register. Note the result may be
1615/// conservative. If it cannot definitely determine the safety after visiting
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1616/// a few instructions in each direction it assumes it's not safe.
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1617static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1618 MachineBasicBlock::iterator I) {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1619 MachineBasicBlock::iterator E = MBB.end();
1620
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1621 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1622 // safety after visiting 4 instructions in each direction, we will assume
1623 // it's not safe.
1624 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1625 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1626 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1627 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1628 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1629 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1630 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1631 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1632 continue;
1633 if (MO.getReg() == X86::EFLAGS) {
1634 if (MO.isUse())
1635 return false;
1636 SeenDef = true;
1637 }
1638 }
1639
1640 if (SeenDef)
1641 // This instruction defines EFLAGS, no need to look any further.
1642 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1643 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1644 // Skip over DBG_VALUE.
1645 while (Iter != E && Iter->isDebugValue())
1646 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1647 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1648
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1649 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1650 // live in.
1651 if (Iter == E) {
1652 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1653 SE = MBB.succ_end(); SI != SE; ++SI)
1654 if ((*SI)->isLiveIn(X86::EFLAGS))
1655 return false;
1656 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1657 }
1658
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1659 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1660 Iter = I;
1661 for (unsigned i = 0; i < 4; ++i) {
1662 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]1663 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1664 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1665 return !MBB.isLiveIn(X86::EFLAGS);
1666
1667 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1668 // Skip over DBG_VALUE.
1669 while (Iter != B && Iter->isDebugValue())
1670 --Iter;
1671
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1672 bool SawKill = false;
1673 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1674 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1675 // A register mask may clobber EFLAGS, but we should still look for a
1676 // live EFLAGS def.
1677 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1678 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1679 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1680 if (MO.isDef()) return MO.isDead();
1681 if (MO.isKill()) SawKill = true;
1682 }
1683 }
1684
1685 if (SawKill)
1686 // This instruction kills EFLAGS and doesn't redefine it, so
1687 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1688 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1689 }
1690
1691 // Conservative answer.
1692 return false;
1693}
1694
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1695void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1696 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1697 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]1698 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1699 const TargetRegisterInfo &TRI) const {
Dan Gohman90c600d2010-05-07 01:28:10 +0000[diff] [blame]1700 DebugLoc DL = Orig->getDebugLoc();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1701
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1702 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1703 // Re-materialize them as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1704 bool Clone = true;
1705 unsigned Opc = Orig->getOpcode();
1706 switch (Opc) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1707 default: break;
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1708 case X86::MOV8r0:
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]1709 case X86::MOV16r0:
1710 case X86::MOV32r0:
1711 case X86::MOV64r0: {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1712 if (!isSafeToClobberEFLAGS(MBB, I)) {
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1713 switch (Opc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1714 default: llvm_unreachable("Unreachable!");
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1715 case X86::MOV8r0: Opc = X86::MOV8ri; break;
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]1716 case X86::MOV16r0: Opc = X86::MOV16ri; break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1717 case X86::MOV32r0: Opc = X86::MOV32ri; break;
Dan Gohman952f6f92010-02-26 16:49:27 +0000[diff] [blame]1718 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1719 }
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1720 Clone = false;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1721 }
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1722 break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1723 }
1724 }
1725
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1726 if (Clone) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1727 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1728 MBB.insert(I, MI);
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1729 } else {
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1730 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1731 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]1732
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1733 MachineInstr *NewMI = prior(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1734 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1735}
1736
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1737/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1738/// is not marked dead.
1739static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1740 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1741 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1742 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1743 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1744 return true;
1745 }
1746 }
1747 return false;
1748}
1749
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1750/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1751/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1752/// to a 32-bit superregister and then truncating back down to a 16-bit
1753/// subregister.
1754MachineInstr *
1755X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1756 MachineFunction::iterator &MFI,
1757 MachineBasicBlock::iterator &MBBI,
1758 LiveVariables *LV) const {
1759 MachineInstr *MI = MBBI;
1760 unsigned Dest = MI->getOperand(0).getReg();
1761 unsigned Src = MI->getOperand(1).getReg();
1762 bool isDead = MI->getOperand(0).isDead();
1763 bool isKill = MI->getOperand(1).isKill();
1764
1765 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1766 ? X86::LEA64_32r : X86::LEA32r;
1767 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1768 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1769 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1770
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1771 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1772 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1773 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]1774 // movw (%rbp,%rcx,2), %dx
1775 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1776 // But testing has shown this *does* help performance in 64-bit mode (at
1777 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1778 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1779 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]1780 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1781 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1782 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1783
1784 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1785 get(Opc), leaOutReg);
1786 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]1787 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1788 case X86::SHL16ri: {
1789 unsigned ShAmt = MI->getOperand(2).getImm();
1790 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1791 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1792 break;
1793 }
1794 case X86::INC16r:
1795 case X86::INC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1796 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1797 break;
1798 case X86::DEC16r:
1799 case X86::DEC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1800 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1801 break;
1802 case X86::ADD16ri:
1803 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]1804 case X86::ADD16ri_DB:
1805 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1806 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1807 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]1808 case X86::ADD16rr:
1809 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1810 unsigned Src2 = MI->getOperand(2).getReg();
1811 bool isKill2 = MI->getOperand(2).isKill();
1812 unsigned leaInReg2 = 0;
1813 MachineInstr *InsMI2 = 0;
1814 if (Src == Src2) {
1815 // ADD16rr %reg1028<kill>, %reg1028
1816 // just a single insert_subreg.
1817 addRegReg(MIB, leaInReg, true, leaInReg, false);
1818 } else {
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1819 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1820 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1821 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]1822 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1823 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]1824 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]1825 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1826 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1827 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1828 }
1829 if (LV && isKill2 && InsMI2)
1830 LV->replaceKillInstruction(Src2, MI, InsMI2);
1831 break;
1832 }
1833 }
1834
1835 MachineInstr *NewMI = MIB;
1836 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]1837 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1838 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]1839 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1840
1841 if (LV) {
1842 // Update live variables
1843 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1844 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1845 if (isKill)
1846 LV->replaceKillInstruction(Src, MI, InsMI);
1847 if (isDead)
1848 LV->replaceKillInstruction(Dest, MI, ExtMI);
1849 }
1850
1851 return ExtMI;
1852}
1853
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1854/// convertToThreeAddress - This method must be implemented by targets that
1855/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1856/// may be able to convert a two-address instruction into a true
1857/// three-address instruction on demand. This allows the X86 target (for
1858/// example) to convert ADD and SHL instructions into LEA instructions if they
1859/// would require register copies due to two-addressness.
1860///
1861/// This method returns a null pointer if the transformation cannot be
1862/// performed, otherwise it returns the new instruction.
1863///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1864MachineInstr *
1865X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1866 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]1867 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1868 MachineInstr *MI = MBBI;
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1869 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1870 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1871 const MachineOperand &Dest = MI->getOperand(0);
1872 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1873
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]1874 MachineInstr *NewMI = NULL;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1875 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1876 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1877 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1878 bool DisableLEA16 = true;
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1879 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1880
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1881 unsigned MIOpc = MI->getOpcode();
1882 switch (MIOpc) {
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1883 case X86::SHUFPSrri: {
1884 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1885 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1886
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]1887 unsigned B = MI->getOperand(1).getReg();
1888 unsigned C = MI->getOperand(2).getReg();
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1889 if (B != C) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1890 unsigned M = MI->getOperand(3).getImm();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1891 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1892 .addOperand(Dest).addOperand(Src).addImm(M);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1893 break;
1894 }
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]1895 case X86::SHUFPDrri: {
1896 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1897 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1898
1899 unsigned B = MI->getOperand(1).getReg();
1900 unsigned C = MI->getOperand(2).getReg();
1901 if (B != C) return 0;
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]1902 unsigned M = MI->getOperand(3).getImm();
1903
1904 // Convert to PSHUFD mask.
1905 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1906
1907 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1908 .addOperand(Dest).addOperand(Src).addImm(M);
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]1909 break;
1910 }
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1911 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1912 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1913 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1914 // the flags produced by a shift yet, so this is safe.
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1915 unsigned ShAmt = MI->getOperand(2).getImm();
1916 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1917
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1918 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1919 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
1920 !MF.getRegInfo().constrainRegClass(Src.getReg(),
1921 &X86::GR64_NOSPRegClass))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1922 return 0;
1923
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1924 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1925 .addOperand(Dest)
1926 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1927 break;
1928 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1929 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1930 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1931 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1932 // the flags produced by a shift yet, so this is safe.
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1933 unsigned ShAmt = MI->getOperand(2).getImm();
1934 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1935
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1936 // LEA can't handle ESP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1937 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
1938 !MF.getRegInfo().constrainRegClass(Src.getReg(),
1939 &X86::GR32_NOSPRegClass))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1940 return 0;
1941
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1942 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1943 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1944 .addOperand(Dest)
1945 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1946 break;
1947 }
1948 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1949 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Evan Cheng189df732007-09-06 00:14:41 +0000[diff] [blame]1950 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1951 // the flags produced by a shift yet, so this is safe.
Evan Cheng189df732007-09-06 00:14:41 +0000[diff] [blame]1952 unsigned ShAmt = MI->getOperand(2).getImm();
1953 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1954
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1955 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1956 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1957 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1958 .addOperand(Dest)
1959 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1960 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1961 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1962 default: {
1963 // The following opcodes also sets the condition code register(s). Only
1964 // convert them to equivalent lea if the condition code register def's
1965 // are dead!
1966 if (hasLiveCondCodeDef(MI))
1967 return 0;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1968
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1969 switch (MIOpc) {
1970 default: return 0;
1971 case X86::INC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]1972 case X86::INC32r:
1973 case X86::INC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1974 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]1975 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1976 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]1977 const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
1978 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1979 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1980
1981 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1982 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
1983 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1984 return 0;
1985
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1986 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1987 .addOperand(Dest).addOperand(Src), 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1988 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1989 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1990 case X86::INC16r:
1991 case X86::INC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1992 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1993 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1994 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]1995 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1996 .addOperand(Dest).addOperand(Src), 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1997 break;
1998 case X86::DEC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]1999 case X86::DEC32r:
2000 case X86::DEC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2001 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]2002 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2003 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]2004 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
2005 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
2006 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2007 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2008 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2009 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2010 return 0;
2011
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2012 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2013 .addOperand(Dest).addOperand(Src), -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2014 break;
2015 }
2016 case X86::DEC16r:
2017 case X86::DEC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2018 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2019 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2020 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2021 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2022 .addOperand(Dest).addOperand(Src), -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2023 break;
2024 case X86::ADD64rr:
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2025 case X86::ADD64rr_DB:
2026 case X86::ADD32rr:
2027 case X86::ADD32rr_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2028 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2029 unsigned Opc;
Craig Topper760b1342012-02-22 05:59:10 +0000[diff] [blame]2030 const TargetRegisterClass *RC;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2031 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
2032 Opc = X86::LEA64r;
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]2033 RC = &X86::GR64_NOSPRegClass;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2034 } else {
2035 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]2036 RC = &X86::GR32_NOSPRegClass;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2037 }
2038
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2039
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2040 unsigned Src2 = MI->getOperand(2).getReg();
2041 bool isKill2 = MI->getOperand(2).isKill();
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2042
2043 // LEA can't handle RSP.
2044 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2045 !MF.getRegInfo().constrainRegClass(Src2, RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2046 return 0;
2047
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2048 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2049 .addOperand(Dest),
2050 Src.getReg(), Src.isKill(), Src2, isKill2);
Nadav Rotem4968e452012-07-16 10:52:25 +0000[diff] [blame]2051
2052 // Preserve undefness of the operands.
2053 bool isUndef = MI->getOperand(1).isUndef();
2054 bool isUndef2 = MI->getOperand(2).isUndef();
2055 NewMI->getOperand(1).setIsUndef(isUndef);
2056 NewMI->getOperand(3).setIsUndef(isUndef2);
2057
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2058 if (LV && isKill2)
2059 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2060 break;
2061 }
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2062 case X86::ADD16rr:
2063 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2064 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2065 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2066 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2067 unsigned Src2 = MI->getOperand(2).getReg();
2068 bool isKill2 = MI->getOperand(2).isKill();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2069 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2070 .addOperand(Dest),
2071 Src.getReg(), Src.isKill(), Src2, isKill2);
2072
2073 // Preserve undefness of the operands.
2074 bool isUndef = MI->getOperand(1).isUndef();
2075 bool isUndef2 = MI->getOperand(2).isUndef();
2076 NewMI->getOperand(1).setIsUndef(isUndef);
2077 NewMI->getOperand(3).setIsUndef(isUndef2);
2078
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2079 if (LV && isKill2)
2080 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2081 break;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2082 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2083 case X86::ADD64ri32:
2084 case X86::ADD64ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2085 case X86::ADD64ri32_DB:
2086 case X86::ADD64ri8_DB:
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2087 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2088 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2089 .addOperand(Dest).addOperand(Src),
2090 MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2091 break;
2092 case X86::ADD32ri:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2093 case X86::ADD32ri8:
2094 case X86::ADD32ri_DB:
2095 case X86::ADD32ri8_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2096 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2097 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2098 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2099 .addOperand(Dest).addOperand(Src),
2100 MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2101 break;
2102 }
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2103 case X86::ADD16ri:
2104 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2105 case X86::ADD16ri_DB:
2106 case X86::ADD16ri8_DB:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2107 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2108 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2109 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2110 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2111 .addOperand(Dest).addOperand(Src),
2112 MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2113 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2114 }
2115 }
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2116 }
2117
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2118 if (!NewMI) return 0;
2119
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2120 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2121 if (Src.isKill())
2122 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2123 if (Dest.isDead())
2124 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2125 }
2126
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2127 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2128 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2129}
2130
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2131/// commuteInstruction - We have a few instructions that must be hacked on to
2132/// commute them.
2133///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2134MachineInstr *
2135X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2136 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2137 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2138 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2139 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2140 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2141 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2142 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2143 unsigned Opc;
2144 unsigned Size;
2145 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2146 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2147 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2148 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2149 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2150 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2151 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2152 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2153 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2154 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2155 if (NewMI) {
2156 MachineFunction &MF = *MI->getParent()->getParent();
2157 MI = MF.CloneMachineInstr(MI);
2158 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2159 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2160 MI->setDesc(get(Opc));
2161 MI->getOperand(3).setImm(Size-Amt);
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2162 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2163 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2164 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
2165 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2166 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
2167 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2168 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2169 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
2170 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
2171 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2172 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2173 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
2174 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
2175 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2176 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
2177 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2178 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
2179 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2180 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2181 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]2182 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2183 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2184 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2185 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2186 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2187 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2188 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2189 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2190 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2191 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2192 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2193 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2194 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2195 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2196 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2197 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2198 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2199 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2200 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2201 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2202 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2203 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2204 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2205 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2206 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2207 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2208 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2209 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2210 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2211 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2212 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2213 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2214 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2215 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2216 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2217 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2218 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2219 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2220 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2221 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2222 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2223 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2224 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2225 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2226 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2227 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2228 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2229 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2230 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2231 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2232 if (NewMI) {
2233 MachineFunction &MF = *MI->getParent()->getParent();
2234 MI = MF.CloneMachineInstr(MI);
2235 NewMI = false;
2236 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2237 MI->setDesc(get(Opc));
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2238 // Fallthrough intended.
2239 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2240 default:
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]2241 return TargetInstrInfo::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2242 }
2243}
2244
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2245static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2246 switch (BrOpc) {
2247 default: return X86::COND_INVALID;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2248 case X86::JE_4: return X86::COND_E;
2249 case X86::JNE_4: return X86::COND_NE;
2250 case X86::JL_4: return X86::COND_L;
2251 case X86::JLE_4: return X86::COND_LE;
2252 case X86::JG_4: return X86::COND_G;
2253 case X86::JGE_4: return X86::COND_GE;
2254 case X86::JB_4: return X86::COND_B;
2255 case X86::JBE_4: return X86::COND_BE;
2256 case X86::JA_4: return X86::COND_A;
2257 case X86::JAE_4: return X86::COND_AE;
2258 case X86::JS_4: return X86::COND_S;
2259 case X86::JNS_4: return X86::COND_NS;
2260 case X86::JP_4: return X86::COND_P;
2261 case X86::JNP_4: return X86::COND_NP;
2262 case X86::JO_4: return X86::COND_O;
2263 case X86::JNO_4: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2264 }
2265}
2266
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2267/// getCondFromSETOpc - return condition code of a SET opcode.
2268static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2269 switch (Opc) {
2270 default: return X86::COND_INVALID;
2271 case X86::SETAr: case X86::SETAm: return X86::COND_A;
2272 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2273 case X86::SETBr: case X86::SETBm: return X86::COND_B;
2274 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2275 case X86::SETEr: case X86::SETEm: return X86::COND_E;
2276 case X86::SETGr: case X86::SETGm: return X86::COND_G;
2277 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2278 case X86::SETLr: case X86::SETLm: return X86::COND_L;
2279 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2280 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2281 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2282 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2283 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2284 case X86::SETOr: case X86::SETOm: return X86::COND_O;
2285 case X86::SETPr: case X86::SETPm: return X86::COND_P;
2286 case X86::SETSr: case X86::SETSm: return X86::COND_S;
2287 }
2288}
2289
2290/// getCondFromCmovOpc - return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]2291X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2292 switch (Opc) {
2293 default: return X86::COND_INVALID;
2294 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
2295 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
2296 return X86::COND_A;
2297 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2298 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2299 return X86::COND_AE;
2300 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
2301 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
2302 return X86::COND_B;
2303 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2304 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2305 return X86::COND_BE;
2306 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
2307 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
2308 return X86::COND_E;
2309 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
2310 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
2311 return X86::COND_G;
2312 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2313 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2314 return X86::COND_GE;
2315 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
2316 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
2317 return X86::COND_L;
2318 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2319 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2320 return X86::COND_LE;
2321 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2322 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2323 return X86::COND_NE;
2324 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2325 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2326 return X86::COND_NO;
2327 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2328 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2329 return X86::COND_NP;
2330 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2331 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2332 return X86::COND_NS;
2333 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
2334 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
2335 return X86::COND_O;
2336 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
2337 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
2338 return X86::COND_P;
2339 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
2340 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
2341 return X86::COND_S;
2342 }
2343}
2344
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2345unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2346 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2347 default: llvm_unreachable("Illegal condition code!");
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2348 case X86::COND_E: return X86::JE_4;
2349 case X86::COND_NE: return X86::JNE_4;
2350 case X86::COND_L: return X86::JL_4;
2351 case X86::COND_LE: return X86::JLE_4;
2352 case X86::COND_G: return X86::JG_4;
2353 case X86::COND_GE: return X86::JGE_4;
2354 case X86::COND_B: return X86::JB_4;
2355 case X86::COND_BE: return X86::JBE_4;
2356 case X86::COND_A: return X86::JA_4;
2357 case X86::COND_AE: return X86::JAE_4;
2358 case X86::COND_S: return X86::JS_4;
2359 case X86::COND_NS: return X86::JNS_4;
2360 case X86::COND_P: return X86::JP_4;
2361 case X86::COND_NP: return X86::JNP_4;
2362 case X86::COND_O: return X86::JO_4;
2363 case X86::COND_NO: return X86::JNO_4;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2364 }
2365}
2366
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2367/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2368/// e.g. turning COND_E to COND_NE.
2369X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2370 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2371 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2372 case X86::COND_E: return X86::COND_NE;
2373 case X86::COND_NE: return X86::COND_E;
2374 case X86::COND_L: return X86::COND_GE;
2375 case X86::COND_LE: return X86::COND_G;
2376 case X86::COND_G: return X86::COND_LE;
2377 case X86::COND_GE: return X86::COND_L;
2378 case X86::COND_B: return X86::COND_AE;
2379 case X86::COND_BE: return X86::COND_A;
2380 case X86::COND_A: return X86::COND_BE;
2381 case X86::COND_AE: return X86::COND_B;
2382 case X86::COND_S: return X86::COND_NS;
2383 case X86::COND_NS: return X86::COND_S;
2384 case X86::COND_P: return X86::COND_NP;
2385 case X86::COND_NP: return X86::COND_P;
2386 case X86::COND_O: return X86::COND_NO;
2387 case X86::COND_NO: return X86::COND_O;
2388 }
2389}
2390
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2391/// getSwappedCondition - assume the flags are set by MI(a,b), return
2392/// the condition code if we modify the instructions such that flags are
2393/// set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]2394static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2395 switch (CC) {
2396 default: return X86::COND_INVALID;
2397 case X86::COND_E: return X86::COND_E;
2398 case X86::COND_NE: return X86::COND_NE;
2399 case X86::COND_L: return X86::COND_G;
2400 case X86::COND_LE: return X86::COND_GE;
2401 case X86::COND_G: return X86::COND_L;
2402 case X86::COND_GE: return X86::COND_LE;
2403 case X86::COND_B: return X86::COND_A;
2404 case X86::COND_BE: return X86::COND_AE;
2405 case X86::COND_A: return X86::COND_B;
2406 case X86::COND_AE: return X86::COND_BE;
2407 }
2408}
2409
2410/// getSETFromCond - Return a set opcode for the given condition and
2411/// whether it has memory operand.
2412static unsigned getSETFromCond(X86::CondCode CC,
2413 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2414 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2415 { X86::SETAr, X86::SETAm },
2416 { X86::SETAEr, X86::SETAEm },
2417 { X86::SETBr, X86::SETBm },
2418 { X86::SETBEr, X86::SETBEm },
2419 { X86::SETEr, X86::SETEm },
2420 { X86::SETGr, X86::SETGm },
2421 { X86::SETGEr, X86::SETGEm },
2422 { X86::SETLr, X86::SETLm },
2423 { X86::SETLEr, X86::SETLEm },
2424 { X86::SETNEr, X86::SETNEm },
2425 { X86::SETNOr, X86::SETNOm },
2426 { X86::SETNPr, X86::SETNPm },
2427 { X86::SETNSr, X86::SETNSm },
2428 { X86::SETOr, X86::SETOm },
2429 { X86::SETPr, X86::SETPm },
2430 { X86::SETSr, X86::SETSm }
2431 };
2432
2433 assert(CC < 16 && "Can only handle standard cond codes");
2434 return Opc[CC][HasMemoryOperand ? 1 : 0];
2435}
2436
2437/// getCMovFromCond - Return a cmov opcode for the given condition,
2438/// register size in bytes, and operand type.
2439static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2440 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]2441 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2442 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
2443 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2444 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
2445 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2446 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
2447 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
2448 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2449 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
2450 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2451 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2452 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2453 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2454 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2455 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
2456 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2457 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
2458 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
2459 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2460 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
2461 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2462 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
2463 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
2464 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2465 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
2466 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2467 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2468 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2469 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2470 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2471 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
2472 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
2473 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2474 };
2475
2476 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2477 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2478 switch(RegBytes) {
2479 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2480 case 2: return Opc[Idx][0];
2481 case 4: return Opc[Idx][1];
2482 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2483 }
2484}
2485
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2486bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2487 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2488
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2489 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2490 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2491 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2492 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2493 return true;
2494 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2495}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2496
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2497bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2498 MachineBasicBlock *&TBB,
2499 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2500 SmallVectorImpl<MachineOperand> &Cond,
2501 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2502 // Start from the bottom of the block and work up, examining the
2503 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2504 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2505 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2506 while (I != MBB.begin()) {
2507 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2508 if (I->isDebugValue())
2509 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2510
2511 // Working from the bottom, when we see a non-terminator instruction, we're
2512 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]2513 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2514 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2515
2516 // A terminator that isn't a branch can't easily be handled by this
2517 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2518 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2519 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2520
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2521 // Handle unconditional branches.
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2522 if (I->getOpcode() == X86::JMP_4) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2523 UnCondBrIter = I;
2524
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2525 if (!AllowModify) {
2526 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]2527 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2528 }
2529
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2530 // If the block has any instructions after a JMP, delete them.
Chris Lattnera48f44d2009-12-03 00:50:42 +0000[diff] [blame]2531 while (llvm::next(I) != MBB.end())
2532 llvm::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2533
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2534 Cond.clear();
2535 FBB = 0;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2536
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2537 // Delete the JMP if it's equivalent to a fall-through.
2538 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2539 TBB = 0;
2540 I->eraseFromParent();
2541 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2542 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2543 continue;
2544 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2545
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2546 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2547 TBB = I->getOperand(0).getMBB();
2548 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2549 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2550
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2551 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2552 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2553 if (BranchCode == X86::COND_INVALID)
2554 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2555
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2556 // Working from the bottom, handle the first conditional branch.
2557 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2558 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2559 if (AllowModify && UnCondBrIter != MBB.end() &&
2560 MBB.isLayoutSuccessor(TargetBB)) {
2561 // If we can modify the code and it ends in something like:
2562 //
2563 // jCC L1
2564 // jmp L2
2565 // L1:
2566 // ...
2567 // L2:
2568 //
2569 // Then we can change this to:
2570 //
2571 // jnCC L2
2572 // L1:
2573 // ...
2574 // L2:
2575 //
2576 // Which is a bit more efficient.
2577 // We conditionally jump to the fall-through block.
2578 BranchCode = GetOppositeBranchCondition(BranchCode);
2579 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2580 MachineBasicBlock::iterator OldInst = I;
2581
2582 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2583 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2584 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2585 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2586
2587 OldInst->eraseFromParent();
2588 UnCondBrIter->eraseFromParent();
2589
2590 // Restart the analysis.
2591 UnCondBrIter = MBB.end();
2592 I = MBB.end();
2593 continue;
2594 }
2595
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2596 FBB = TBB;
2597 TBB = I->getOperand(0).getMBB();
2598 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2599 continue;
2600 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2601
2602 // Handle subsequent conditional branches. Only handle the case where all
2603 // conditional branches branch to the same destination and their condition
2604 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2605 assert(Cond.size() == 1);
2606 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2607
2608 // Only handle the case where all conditional branches branch to the same
2609 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2610 if (TBB != I->getOperand(0).getMBB())
2611 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2612
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2613 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2614 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2615 if (OldBranchCode == BranchCode)
2616 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2617
2618 // If they differ, see if they fit one of the known patterns. Theoretically,
2619 // we could handle more patterns here, but we shouldn't expect to see them
2620 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2621 if ((OldBranchCode == X86::COND_NP &&
2622 BranchCode == X86::COND_E) ||
2623 (OldBranchCode == X86::COND_E &&
2624 BranchCode == X86::COND_NP))
2625 BranchCode = X86::COND_NP_OR_E;
2626 else if ((OldBranchCode == X86::COND_P &&
2627 BranchCode == X86::COND_NE) ||
2628 (OldBranchCode == X86::COND_NE &&
2629 BranchCode == X86::COND_P))
2630 BranchCode = X86::COND_NE_OR_P;
2631 else
2632 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2633
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2634 // Update the MachineOperand.
2635 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]2636 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2637
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2638 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2639}
2640
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2641unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2642 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2643 unsigned Count = 0;
2644
2645 while (I != MBB.begin()) {
2646 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2647 if (I->isDebugValue())
2648 continue;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2649 if (I->getOpcode() != X86::JMP_4 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2650 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2651 break;
2652 // Remove the branch.
2653 I->eraseFromParent();
2654 I = MBB.end();
2655 ++Count;
2656 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2657
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2658 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2659}
2660
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2661unsigned
2662X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2663 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2664 const SmallVectorImpl<MachineOperand> &Cond,
2665 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2666 // Shouldn't be a fall through.
2667 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]2668 assert((Cond.size() == 1 || Cond.size() == 0) &&
2669 "X86 branch conditions have one component!");
2670
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2671 if (Cond.empty()) {
2672 // Unconditional branch?
2673 assert(!FBB && "Unconditional branch with multiple successors!");
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2674 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2675 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2676 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2677
2678 // Conditional branch.
2679 unsigned Count = 0;
2680 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2681 switch (CC) {
2682 case X86::COND_NP_OR_E:
2683 // Synthesize NP_OR_E with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2684 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2685 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2686 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2687 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2688 break;
2689 case X86::COND_NE_OR_P:
2690 // Synthesize NE_OR_P with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2691 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2692 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2693 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2694 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2695 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2696 default: {
2697 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2698 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2699 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2700 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2701 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2702 if (FBB) {
2703 // Two-way Conditional branch. Insert the second branch.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2704 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2705 ++Count;
2706 }
2707 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2708}
2709
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2710bool X86InstrInfo::
2711canInsertSelect(const MachineBasicBlock &MBB,
2712 const SmallVectorImpl<MachineOperand> &Cond,
2713 unsigned TrueReg, unsigned FalseReg,
2714 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2715 // Not all subtargets have cmov instructions.
2716 if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2717 return false;
2718 if (Cond.size() != 1)
2719 return false;
2720 // We cannot do the composite conditions, at least not in SSA form.
2721 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2722 return false;
2723
2724 // Check register classes.
2725 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2726 const TargetRegisterClass *RC =
2727 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2728 if (!RC)
2729 return false;
2730
2731 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2732 if (X86::GR16RegClass.hasSubClassEq(RC) ||
2733 X86::GR32RegClass.hasSubClassEq(RC) ||
2734 X86::GR64RegClass.hasSubClassEq(RC)) {
2735 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2736 // Bridge. Probably Ivy Bridge as well.
2737 CondCycles = 2;
2738 TrueCycles = 2;
2739 FalseCycles = 2;
2740 return true;
2741 }
2742
2743 // Can't do vectors.
2744 return false;
2745}
2746
2747void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2748 MachineBasicBlock::iterator I, DebugLoc DL,
2749 unsigned DstReg,
2750 const SmallVectorImpl<MachineOperand> &Cond,
2751 unsigned TrueReg, unsigned FalseReg) const {
2752 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2753 assert(Cond.size() == 1 && "Invalid Cond array");
2754 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]2755 MRI.getRegClass(DstReg)->getSize(),
2756 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]2757 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2758}
2759
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]2760/// isHReg - Test if the given register is a physical h register.
2761static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2762 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]2763}
2764
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2765// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2766static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2767 bool HasAVX) {
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2768 // SrcReg(VR128) -> DestReg(GR64)
2769 // SrcReg(VR64) -> DestReg(GR64)
2770 // SrcReg(GR64) -> DestReg(VR128)
2771 // SrcReg(GR64) -> DestReg(VR64)
2772
2773 if (X86::GR64RegClass.contains(DestReg)) {
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2774 if (X86::VR128RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2775 // Copy from a VR128 register to a GR64 register.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2776 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2777 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2778 // Copy from a VR64 register to a GR64 register.
2779 return X86::MOVSDto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2780 } else if (X86::GR64RegClass.contains(SrcReg)) {
2781 // Copy from a GR64 register to a VR128 register.
2782 if (X86::VR128RegClass.contains(DestReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2783 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2784 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2785 if (X86::VR64RegClass.contains(DestReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2786 return X86::MOV64toSDrr;
2787 }
2788
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]2789 // SrcReg(FR32) -> DestReg(GR32)
2790 // SrcReg(GR32) -> DestReg(FR32)
2791
2792 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2793 // Copy from a FR32 register to a GR32 register.
2794 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]2795
2796 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2797 // Copy from a GR32 register to a FR32 register.
2798 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]2799
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2800 return 0;
2801}
2802
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2803void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2804 MachineBasicBlock::iterator MI, DebugLoc DL,
2805 unsigned DestReg, unsigned SrcReg,
2806 bool KillSrc) const {
2807 // First deal with the normal symmetric copies.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2808 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2809 unsigned Opc;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2810 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2811 Opc = X86::MOV64rr;
2812 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2813 Opc = X86::MOV32rr;
2814 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2815 Opc = X86::MOV16rr;
2816 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2817 // Copying to or from a physical H register on x86-64 requires a NOREX
2818 // move. Otherwise use a normal move.
2819 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]2820 TM.getSubtarget<X86Subtarget>().is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2821 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]2822 // Both operands must be encodable without an REX prefix.
2823 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2824 "8-bit H register can not be copied outside GR8_NOREX");
2825 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2826 Opc = X86::MOV8rr;
2827 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2828 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2829 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2830 Opc = X86::VMOVAPSYrr;
Jakob Stoklund Olesenec58a432010-07-08 22:30:35 +0000[diff] [blame]2831 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2832 Opc = X86::MMX_MOVQ64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2833 else
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2834 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2835
2836 if (Opc) {
2837 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2838 .addReg(SrcReg, getKillRegState(KillSrc));
2839 return;
2840 }
2841
2842 // Moving EFLAGS to / from another register requires a push and a pop.
2843 if (SrcReg == X86::EFLAGS) {
2844 if (X86::GR64RegClass.contains(DestReg)) {
2845 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2846 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2847 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2848 }
2849 if (X86::GR32RegClass.contains(DestReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2850 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2851 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2852 return;
2853 }
2854 }
2855 if (DestReg == X86::EFLAGS) {
2856 if (X86::GR64RegClass.contains(SrcReg)) {
2857 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2858 .addReg(SrcReg, getKillRegState(KillSrc));
2859 BuildMI(MBB, MI, DL, get(X86::POPF64));
2860 return;
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]2861 }
2862 if (X86::GR32RegClass.contains(SrcReg)) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2863 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2864 .addReg(SrcReg, getKillRegState(KillSrc));
2865 BuildMI(MBB, MI, DL, get(X86::POPF32));
2866 return;
2867 }
2868 }
2869
2870 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2871 << " to " << RI.getName(DestReg) << '\n');
2872 llvm_unreachable("Cannot emit physreg copy instruction");
2873}
2874
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2875static unsigned getLoadStoreRegOpcode(unsigned Reg,
2876 const TargetRegisterClass *RC,
2877 bool isStackAligned,
2878 const TargetMachine &TM,
2879 bool load) {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2880 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2881 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]2882 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2883 llvm_unreachable("Unknown spill size");
2884 case 1:
2885 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2886 if (TM.getSubtarget<X86Subtarget>().is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2887 // Copying to or from a physical H register on x86-64 requires a NOREX
2888 // move. Otherwise use a normal move.
2889 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2890 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2891 return load ? X86::MOV8rm : X86::MOV8mr;
2892 case 2:
2893 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2894 return load ? X86::MOV16rm : X86::MOV16mr;
2895 case 4:
2896 if (X86::GR32RegClass.hasSubClassEq(RC))
2897 return load ? X86::MOV32rm : X86::MOV32mr;
2898 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2899 return load ?
2900 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2901 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2902 if (X86::RFP32RegClass.hasSubClassEq(RC))
2903 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2904 llvm_unreachable("Unknown 4-byte regclass");
2905 case 8:
2906 if (X86::GR64RegClass.hasSubClassEq(RC))
2907 return load ? X86::MOV64rm : X86::MOV64mr;
2908 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2909 return load ?
2910 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2911 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2912 if (X86::VR64RegClass.hasSubClassEq(RC))
2913 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2914 if (X86::RFP64RegClass.hasSubClassEq(RC))
2915 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2916 llvm_unreachable("Unknown 8-byte regclass");
2917 case 10:
2918 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2919 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2920 case 16: {
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2921 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2922 // If stack is realigned we can use aligned stores.
2923 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2924 return load ?
2925 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2926 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2927 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2928 return load ?
2929 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2930 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2931 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2932 case 32:
2933 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2934 // If stack is realigned we can use aligned stores.
2935 if (isStackAligned)
2936 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2937 else
2938 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2939 }
2940}
2941
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2942static unsigned getStoreRegOpcode(unsigned SrcReg,
2943 const TargetRegisterClass *RC,
2944 bool isStackAligned,
2945 TargetMachine &TM) {
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2946 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2947}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2948
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2949
2950static unsigned getLoadRegOpcode(unsigned DestReg,
2951 const TargetRegisterClass *RC,
2952 bool isStackAligned,
2953 const TargetMachine &TM) {
2954 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2955}
2956
2957void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2958 MachineBasicBlock::iterator MI,
2959 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]2960 const TargetRegisterClass *RC,
2961 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]2962 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]2963 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2964 "Stack slot too small for store");
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2965 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2966 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]2967 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2968 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]2969 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2970 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2971 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2972}
2973
2974void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2975 bool isKill,
2976 SmallVectorImpl<MachineOperand> &Addr,
2977 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2978 MachineInstr::mmo_iterator MMOBegin,
2979 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2980 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2981 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2982 bool isAligned = MMOBegin != MMOEnd &&
2983 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2984 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]2985 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]2986 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2987 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2988 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2989 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2990 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2991 NewMIs.push_back(MIB);
2992}
2993
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2994
2995void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]2996 MachineBasicBlock::iterator MI,
2997 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]2998 const TargetRegisterClass *RC,
2999 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]3000 const MachineFunction &MF = *MBB.getParent();
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3001 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3002 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]3003 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3004 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]3005 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3006 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3007}
3008
3009void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3010 SmallVectorImpl<MachineOperand> &Addr,
3011 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3012 MachineInstr::mmo_iterator MMOBegin,
3013 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3014 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3015 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3016 bool isAligned = MMOBegin != MMOEnd &&
3017 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3018 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]3019 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]3020 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3021 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3022 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3023 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]3024 NewMIs.push_back(MIB);
3025}
3026
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3027bool X86InstrInfo::
3028analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3029 int &CmpMask, int &CmpValue) const {
3030 switch (MI->getOpcode()) {
3031 default: break;
3032 case X86::CMP64ri32:
3033 case X86::CMP64ri8:
3034 case X86::CMP32ri:
3035 case X86::CMP32ri8:
3036 case X86::CMP16ri:
3037 case X86::CMP16ri8:
3038 case X86::CMP8ri:
3039 SrcReg = MI->getOperand(0).getReg();
3040 SrcReg2 = 0;
3041 CmpMask = ~0;
3042 CmpValue = MI->getOperand(1).getImm();
3043 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3044 // A SUB can be used to perform comparison.
3045 case X86::SUB64rm:
3046 case X86::SUB32rm:
3047 case X86::SUB16rm:
3048 case X86::SUB8rm:
3049 SrcReg = MI->getOperand(1).getReg();
3050 SrcReg2 = 0;
3051 CmpMask = ~0;
3052 CmpValue = 0;
3053 return true;
3054 case X86::SUB64rr:
3055 case X86::SUB32rr:
3056 case X86::SUB16rr:
3057 case X86::SUB8rr:
3058 SrcReg = MI->getOperand(1).getReg();
3059 SrcReg2 = MI->getOperand(2).getReg();
3060 CmpMask = ~0;
3061 CmpValue = 0;
3062 return true;
3063 case X86::SUB64ri32:
3064 case X86::SUB64ri8:
3065 case X86::SUB32ri:
3066 case X86::SUB32ri8:
3067 case X86::SUB16ri:
3068 case X86::SUB16ri8:
3069 case X86::SUB8ri:
3070 SrcReg = MI->getOperand(1).getReg();
3071 SrcReg2 = 0;
3072 CmpMask = ~0;
3073 CmpValue = MI->getOperand(2).getImm();
3074 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3075 case X86::CMP64rr:
3076 case X86::CMP32rr:
3077 case X86::CMP16rr:
3078 case X86::CMP8rr:
3079 SrcReg = MI->getOperand(0).getReg();
3080 SrcReg2 = MI->getOperand(1).getReg();
3081 CmpMask = ~0;
3082 CmpValue = 0;
3083 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3084 case X86::TEST8rr:
3085 case X86::TEST16rr:
3086 case X86::TEST32rr:
3087 case X86::TEST64rr:
3088 SrcReg = MI->getOperand(0).getReg();
3089 if (MI->getOperand(1).getReg() != SrcReg) return false;
3090 // Compare against zero.
3091 SrcReg2 = 0;
3092 CmpMask = ~0;
3093 CmpValue = 0;
3094 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3095 }
3096 return false;
3097}
3098
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3099/// isRedundantFlagInstr - check whether the first instruction, whose only
3100/// purpose is to update flags, can be made redundant.
3101/// CMPrr can be made redundant by SUBrr if the operands are the same.
3102/// This function can be extended later on.
3103/// SrcReg, SrcRegs: register operands for FlagI.
3104/// ImmValue: immediate for FlagI if it takes an immediate.
3105inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3106 unsigned SrcReg2, int ImmValue,
3107 MachineInstr *OI) {
3108 if (((FlagI->getOpcode() == X86::CMP64rr &&
3109 OI->getOpcode() == X86::SUB64rr) ||
3110 (FlagI->getOpcode() == X86::CMP32rr &&
3111 OI->getOpcode() == X86::SUB32rr)||
3112 (FlagI->getOpcode() == X86::CMP16rr &&
3113 OI->getOpcode() == X86::SUB16rr)||
3114 (FlagI->getOpcode() == X86::CMP8rr &&
3115 OI->getOpcode() == X86::SUB8rr)) &&
3116 ((OI->getOperand(1).getReg() == SrcReg &&
3117 OI->getOperand(2).getReg() == SrcReg2) ||
3118 (OI->getOperand(1).getReg() == SrcReg2 &&
3119 OI->getOperand(2).getReg() == SrcReg)))
3120 return true;
3121
3122 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3123 OI->getOpcode() == X86::SUB64ri32) ||
3124 (FlagI->getOpcode() == X86::CMP64ri8 &&
3125 OI->getOpcode() == X86::SUB64ri8) ||
3126 (FlagI->getOpcode() == X86::CMP32ri &&
3127 OI->getOpcode() == X86::SUB32ri) ||
3128 (FlagI->getOpcode() == X86::CMP32ri8 &&
3129 OI->getOpcode() == X86::SUB32ri8) ||
3130 (FlagI->getOpcode() == X86::CMP16ri &&
3131 OI->getOpcode() == X86::SUB16ri) ||
3132 (FlagI->getOpcode() == X86::CMP16ri8 &&
3133 OI->getOpcode() == X86::SUB16ri8) ||
3134 (FlagI->getOpcode() == X86::CMP8ri &&
3135 OI->getOpcode() == X86::SUB8ri)) &&
3136 OI->getOperand(1).getReg() == SrcReg &&
3137 OI->getOperand(2).getImm() == ImmValue)
3138 return true;
3139 return false;
3140}
3141
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3142/// isDefConvertible - check whether the definition can be converted
3143/// to remove a comparison against zero.
3144inline static bool isDefConvertible(MachineInstr *MI) {
3145 switch (MI->getOpcode()) {
3146 default: return false;
3147 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3148 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
3149 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
3150 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
3151 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3152 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
3153 case X86::DEC64m: case X86::DEC32m: case X86::DEC16m: case X86::DEC8m:
3154 case X86::DEC64_32r: case X86::DEC64_16r:
3155 case X86::DEC64_32m: case X86::DEC64_16m:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3156 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3157 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
3158 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
3159 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
3160 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3161 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
3162 case X86::INC64m: case X86::INC32m: case X86::INC16m: case X86::INC8m:
3163 case X86::INC64_32r: case X86::INC64_16r:
3164 case X86::INC64_32m: case X86::INC64_16m:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3165 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3166 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
3167 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
3168 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
3169 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
3170 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3171 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
3172 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
3173 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
3174 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
3175 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
3176 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
3177 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
3178 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
3179 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
3180 return true;
3181 }
3182}
3183
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3184/// optimizeCompareInstr - Check if there exists an earlier instruction that
3185/// operates on the same source operands and sets flags in the same way as
3186/// Compare; remove Compare if possible.
3187bool X86InstrInfo::
3188optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3189 int CmpMask, int CmpValue,
3190 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3191 // Check whether we can replace SUB with CMP.
3192 unsigned NewOpcode = 0;
3193 switch (CmpInstr->getOpcode()) {
3194 default: break;
3195 case X86::SUB64ri32:
3196 case X86::SUB64ri8:
3197 case X86::SUB32ri:
3198 case X86::SUB32ri8:
3199 case X86::SUB16ri:
3200 case X86::SUB16ri8:
3201 case X86::SUB8ri:
3202 case X86::SUB64rm:
3203 case X86::SUB32rm:
3204 case X86::SUB16rm:
3205 case X86::SUB8rm:
3206 case X86::SUB64rr:
3207 case X86::SUB32rr:
3208 case X86::SUB16rr:
3209 case X86::SUB8rr: {
3210 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3211 return false;
3212 // There is no use of the destination register, we can replace SUB with CMP.
3213 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]3214 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]3215 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3216 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3217 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3218 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3219 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3220 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3221 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3222 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3223 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3224 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
3225 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
3226 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
3227 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
3228 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
3229 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
3230 }
3231 CmpInstr->setDesc(get(NewOpcode));
3232 CmpInstr->RemoveOperand(0);
3233 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3234 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3235 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3236 return false;
3237 }
3238 }
3239
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3240 // Get the unique definition of SrcReg.
3241 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3242 if (!MI) return false;
3243
3244 // CmpInstr is the first instruction of the BB.
3245 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3246
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3247 // If we are comparing against zero, check whether we can use MI to update
3248 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3249 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3250 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3251 !isDefConvertible(MI)))
3252 return false;
3253
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3254 // We are searching for an earlier instruction that can make CmpInstr
3255 // redundant and that instruction will be saved in Sub.
3256 MachineInstr *Sub = NULL;
3257 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3258
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3259 // We iterate backward, starting from the instruction before CmpInstr and
3260 // stop when reaching the definition of a source register or done with the BB.
3261 // RI points to the instruction before CmpInstr.
3262 // If the definition is in this basic block, RE points to the definition;
3263 // otherwise, RE is the rend of the basic block.
3264 MachineBasicBlock::reverse_iterator
3265 RI = MachineBasicBlock::reverse_iterator(I),
3266 RE = CmpInstr->getParent() == MI->getParent() ?
3267 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3268 CmpInstr->getParent()->rend();
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3269 MachineInstr *Movr0Inst = 0;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3270 for (; RI != RE; ++RI) {
3271 MachineInstr *Instr = &*RI;
3272 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3273 if (!IsCmpZero &&
3274 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3275 Sub = Instr;
3276 break;
3277 }
3278
3279 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3280 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3281 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3282
3283 // MOV32r0 etc. are implemented with xor which clobbers condition code.
3284 // They are safe to move up, if the definition to EFLAGS is dead and
3285 // earlier instructions do not read or write EFLAGS.
3286 if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 ||
3287 Instr->getOpcode() == X86::MOV16r0 ||
3288 Instr->getOpcode() == X86::MOV32r0 ||
3289 Instr->getOpcode() == X86::MOV64r0) &&
3290 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3291 Movr0Inst = Instr;
3292 continue;
3293 }
3294
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3295 // We can't remove CmpInstr.
3296 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3297 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3298 }
3299
3300 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3301 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3302 return false;
3303
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3304 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3305 Sub->getOperand(2).getReg() == SrcReg);
3306
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3307 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3308 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3309 // If we are done with the basic block, we need to check whether EFLAGS is
3310 // live-out.
3311 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3312 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3313 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3314 for (++I; I != E; ++I) {
3315 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3316 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3317 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3318 // We should check the usage if this instruction uses and updates EFLAGS.
3319 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3320 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3321 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3322 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3323 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3324 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3325 continue;
3326
3327 // EFLAGS is used by this instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3328 X86::CondCode OldCC;
3329 bool OpcIsSET = false;
3330 if (IsCmpZero || IsSwapped) {
3331 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3332 if (Instr.isBranch())
3333 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3334 else {
3335 OldCC = getCondFromSETOpc(Instr.getOpcode());
3336 if (OldCC != X86::COND_INVALID)
3337 OpcIsSET = true;
3338 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3339 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3340 }
3341 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3342 }
3343 if (IsCmpZero) {
3344 switch (OldCC) {
3345 default: break;
3346 case X86::COND_A: case X86::COND_AE:
3347 case X86::COND_B: case X86::COND_BE:
3348 case X86::COND_G: case X86::COND_GE:
3349 case X86::COND_L: case X86::COND_LE:
3350 case X86::COND_O: case X86::COND_NO:
3351 // CF and OF are used, we can't perform this optimization.
3352 return false;
3353 }
3354 } else if (IsSwapped) {
3355 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3356 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3357 // We swap the condition code and synthesize the new opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3358 X86::CondCode NewCC = getSwappedCondition(OldCC);
3359 if (NewCC == X86::COND_INVALID) return false;
3360
3361 // Synthesize the new opcode.
3362 bool HasMemoryOperand = Instr.hasOneMemOperand();
3363 unsigned NewOpc;
3364 if (Instr.isBranch())
3365 NewOpc = GetCondBranchFromCond(NewCC);
3366 else if(OpcIsSET)
3367 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3368 else {
3369 unsigned DstReg = Instr.getOperand(0).getReg();
3370 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3371 HasMemoryOperand);
3372 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3373
3374 // Push the MachineInstr to OpsToUpdate.
3375 // If it is safe to remove CmpInstr, the condition code of these
3376 // instructions will be modified.
3377 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3378 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]3379 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3380 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3381 IsSafe = true;
3382 break;
3383 }
3384 }
3385
3386 // If EFLAGS is not killed nor re-defined, we should check whether it is
3387 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3388 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]3389 MachineBasicBlock *MBB = CmpInstr->getParent();
3390 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3391 SE = MBB->succ_end(); SI != SE; ++SI)
3392 if ((*SI)->isLiveIn(X86::EFLAGS))
3393 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3394 }
3395
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3396 // The instruction to be updated is either Sub or MI.
3397 Sub = IsCmpZero ? MI : Sub;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]3398 // Move Movr0Inst to the place right before Sub.
3399 if (Movr0Inst) {
3400 Sub->getParent()->remove(Movr0Inst);
3401 Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst);
3402 }
3403
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3404 // Make sure Sub instruction defines EFLAGS and mark the def live.
3405 unsigned LastOperand = Sub->getNumOperands() - 1;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3406 assert(Sub->getNumOperands() >= 2 &&
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3407 Sub->getOperand(LastOperand).isReg() &&
3408 Sub->getOperand(LastOperand).getReg() == X86::EFLAGS &&
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]3409 "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND");
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]3410 Sub->getOperand(LastOperand).setIsDef(true);
3411 Sub->getOperand(LastOperand).setIsDead(false);
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]3412 CmpInstr->eraseFromParent();
3413
3414 // Modify the condition code of instructions in OpsToUpdate.
3415 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3416 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3417 return true;
3418}
3419
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]3420/// optimizeLoadInstr - Try to remove the load by folding it to a register
3421/// operand at the use. We fold the load instructions if load defines a virtual
3422/// register, the virtual register is used once in the same BB, and the
3423/// instructions in-between do not load or store, and have no side effects.
3424MachineInstr* X86InstrInfo::
3425optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3426 unsigned &FoldAsLoadDefReg,
3427 MachineInstr *&DefMI) const {
3428 if (FoldAsLoadDefReg == 0)
3429 return 0;
3430 // To be conservative, if there exists another load, clear the load candidate.
3431 if (MI->mayLoad()) {
3432 FoldAsLoadDefReg = 0;
3433 return 0;
3434 }
3435
3436 // Check whether we can move DefMI here.
3437 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3438 assert(DefMI);
3439 bool SawStore = false;
3440 if (!DefMI->isSafeToMove(this, 0, SawStore))
3441 return 0;
3442
3443 // We try to commute MI if possible.
3444 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3445 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3446 // Collect information about virtual register operands of MI.
3447 unsigned SrcOperandId = 0;
3448 bool FoundSrcOperand = false;
3449 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3450 MachineOperand &MO = MI->getOperand(i);
3451 if (!MO.isReg())
3452 continue;
3453 unsigned Reg = MO.getReg();
3454 if (Reg != FoldAsLoadDefReg)
3455 continue;
3456 // Do not fold if we have a subreg use or a def or multiple uses.
3457 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3458 return 0;
3459
3460 SrcOperandId = i;
3461 FoundSrcOperand = true;
3462 }
3463 if (!FoundSrcOperand) return 0;
3464
3465 // Check whether we can fold the def into SrcOperandId.
3466 SmallVector<unsigned, 8> Ops;
3467 Ops.push_back(SrcOperandId);
3468 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3469 if (FoldMI) {
3470 FoldAsLoadDefReg = 0;
3471 return FoldMI;
3472 }
3473
3474 if (Idx == 1) {
3475 // MI was changed but it didn't help, commute it back!
3476 commuteInstruction(MI, false);
3477 return 0;
3478 }
3479
3480 // Check whether we can commute MI and enable folding.
3481 if (MI->isCommutable()) {
3482 MachineInstr *NewMI = commuteInstruction(MI, false);
3483 // Unable to commute.
3484 if (!NewMI) return 0;
3485 if (NewMI != MI) {
3486 // New instruction. It doesn't need to be kept.
3487 NewMI->eraseFromParent();
3488 return 0;
3489 }
3490 }
3491 }
3492 return 0;
3493}
3494
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3495/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3496/// instruction with two undef reads of the register being defined. This is
3497/// used for mapping:
3498/// %xmm4 = V_SET0
3499/// to:
3500/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3501///
3502static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
3503 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3504 unsigned Reg = MI->getOperand(0).getReg();
3505 MI->setDesc(Desc);
3506
3507 // MachineInstr::addOperand() will insert explicit operands before any
3508 // implicit operands.
3509 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
3510 .addReg(Reg, RegState::Undef);
3511 // But we don't trust that.
3512 assert(MI->getOperand(1).getReg() == Reg &&
3513 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
3514 return true;
3515}
3516
3517bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3518 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3519 switch (MI->getOpcode()) {
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]3520 case X86::SETB_C8r:
3521 return Expand2AddrUndef(MI, get(X86::SBB8rr));
3522 case X86::SETB_C16r:
3523 return Expand2AddrUndef(MI, get(X86::SBB16rr));
3524 case X86::SETB_C32r:
3525 return Expand2AddrUndef(MI, get(X86::SBB32rr));
3526 case X86::SETB_C64r:
3527 return Expand2AddrUndef(MI, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3528 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3529 case X86::FsFLD0SS:
3530 case X86::FsFLD0SD:
Jakob Stoklund Olesen024130892011-11-07 19:15:58 +0000[diff] [blame]3531 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]3532 case X86::AVX_SET0:
3533 assert(HasAVX && "AVX not supported");
3534 return Expand2AddrUndef(MI, get(X86::VXORPSYrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]3535 case X86::V_SETALLONES:
3536 return Expand2AddrUndef(MI, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3537 case X86::AVX2_SETALLONES:
3538 return Expand2AddrUndef(MI, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]3539 case X86::TEST8ri_NOREX:
3540 MI->setDesc(get(X86::TEST8ri));
3541 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3542 }
3543 return false;
3544}
3545
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]3546MachineInstr*
3547X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
Evan Cheng250e9172010-04-29 01:13:30 +0000[diff] [blame]3548 int FrameIx, uint64_t Offset,
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]3549 const MDNode *MDPtr,
3550 DebugLoc DL) const {
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]3551 X86AddressMode AM;
3552 AM.BaseType = X86AddressMode::FrameIndexBase;
3553 AM.Base.FrameIndex = FrameIx;
3554 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
3555 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
3556 return &*MIB;
3557}
3558
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]3559static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]3560 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]3561 MachineInstr *MI,
3562 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3563 // Create the base instruction with the memory operand as the first part.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]3564 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3565 MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3566 MachineInstrBuilder MIB(NewMI);
3567 unsigned NumAddrOps = MOs.size();
3568 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3569 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3570 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]3571 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3572
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3573 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]3574 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3575 for (unsigned i = 0; i != NumOps; ++i) {
3576 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3577 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3578 }
3579 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3580 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3581 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3582 }
3583 return MIB;
3584}
3585
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]3586static MachineInstr *FuseInst(MachineFunction &MF,
3587 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]3588 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3589 MachineInstr *MI, const TargetInstrInfo &TII) {
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]3590 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3591 MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3592 MachineInstrBuilder MIB(NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3593
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3594 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3595 MachineOperand &MO = MI->getOperand(i);
3596 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]3597 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3598 unsigned NumAddrOps = MOs.size();
3599 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3600 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3601 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]3602 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3603 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3604 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3605 }
3606 }
3607 return MIB;
3608}
3609
3610static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]3611 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3612 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]3613 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3614 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3615
3616 unsigned NumAddrOps = MOs.size();
3617 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3618 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3619 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]3620 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3621 return MIB.addImm(0);
3622}
3623
3624MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3625X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3626 MachineInstr *MI, unsigned i,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3627 const SmallVectorImpl<MachineOperand> &MOs,
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3628 unsigned Size, unsigned Align) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3629 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3630 bool isTwoAddrFold = false;
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]3631 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3632 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3633 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3634
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]3635 // FIXME: AsmPrinter doesn't know how to handle
3636 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3637 if (MI->getOpcode() == X86::ADD32ri &&
3638 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3639 return NULL;
3640
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3641 MachineInstr *NewMI = NULL;
3642 // Folding a memory location into the two-address part of a two-address
3643 // instruction is different than folding it other places. It requires
3644 // replacing the *two* registers with the memory location.
3645 if (isTwoAddr && NumOps >= 2 && i < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]3646 MI->getOperand(0).isReg() &&
3647 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3648 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3649 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3650 isTwoAddrFold = true;
3651 } else if (i == 0) { // If operand 0
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]3652 unsigned Opc = 0;
3653 switch (MI->getOpcode()) {
3654 default: break;
3655 case X86::MOV64r0: Opc = X86::MOV64mi32; break;
3656 case X86::MOV32r0: Opc = X86::MOV32mi; break;
3657 case X86::MOV16r0: Opc = X86::MOV16mi; break;
3658 case X86::MOV8r0: Opc = X86::MOV8mi; break;
3659 }
3660 if (Opc)
3661 NewMI = MakeM0Inst(*this, Opc, MOs, MI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3662 if (NewMI)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3663 return NewMI;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3664
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3665 OpcodeTablePtr = &RegOp2MemOpTable0;
3666 } else if (i == 1) {
3667 OpcodeTablePtr = &RegOp2MemOpTable1;
3668 } else if (i == 2) {
3669 OpcodeTablePtr = &RegOp2MemOpTable2;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]3670 } else if (i == 3) {
3671 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3672 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3673
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3674 // If table selected...
3675 if (OpcodeTablePtr) {
3676 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3677 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3678 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3679 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3680 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3681 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3682 if (Align < MinAlign)
3683 return NULL;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3684 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3685 if (Size) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3686 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3687 if (Size < RCSize) {
3688 // Check if it's safe to fold the load. If the size of the object is
3689 // narrower than the load width, then it's not.
3690 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
3691 return NULL;
3692 // If this is a 64-bit load, but the spill slot is 32, then we can do
3693 // a 32-bit load which is implicitly zero-extended. This likely is due
3694 // to liveintervalanalysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3695 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
3696 return NULL;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3697 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3698 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3699 }
3700 }
3701
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3702 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3703 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3704 else
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3705 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3706
3707 if (NarrowToMOV32rm) {
3708 // If this is the special case where we use a MOV32rm to load a 32-bit
3709 // value and zero-extend the top bits. Change the destination register
3710 // to a 32-bit one.
3711 unsigned DstReg = NewMI->getOperand(0).getReg();
3712 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
3713 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]3714 X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3715 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]3716 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3717 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3718 return NewMI;
3719 }
3720 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3721
3722 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]3723 if (PrintFailedFusing && !MI->isCopy())
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]3724 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3725 return NULL;
3726}
3727
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3728/// hasPartialRegUpdate - Return true for all instructions that only update
3729/// the first 32 or 64-bits of the destination register and leave the rest
3730/// unmodified. This can be used to avoid folding loads if the instructions
3731/// only update part of the destination register, and the non-updated part is
3732/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
3733/// instructions breaks the partial register dependency and it can improve
3734/// performance. e.g.:
3735///
3736/// movss (%rdi), %xmm0
3737/// cvtss2sd %xmm0, %xmm0
3738///
3739/// Instead of
3740/// cvtss2sd (%rdi), %xmm0
3741///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]3742/// FIXME: This should be turned into a TSFlags.
3743///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3744static bool hasPartialRegUpdate(unsigned Opcode) {
3745 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]3746 case X86::CVTSI2SSrr:
3747 case X86::CVTSI2SS64rr:
3748 case X86::CVTSI2SDrr:
3749 case X86::CVTSI2SD64rr:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3750 case X86::CVTSD2SSrr:
3751 case X86::Int_CVTSD2SSrr:
3752 case X86::CVTSS2SDrr:
3753 case X86::Int_CVTSS2SDrr:
3754 case X86::RCPSSr:
3755 case X86::RCPSSr_Int:
3756 case X86::ROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3757 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3758 case X86::ROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3759 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3760 case X86::RSQRTSSr:
3761 case X86::RSQRTSSr_Int:
3762 case X86::SQRTSSr:
3763 case X86::SQRTSSr_Int:
3764 // AVX encoded versions
3765 case X86::VCVTSD2SSrr:
3766 case X86::Int_VCVTSD2SSrr:
3767 case X86::VCVTSS2SDrr:
3768 case X86::Int_VCVTSS2SDrr:
3769 case X86::VRCPSSr:
3770 case X86::VROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3771 case X86::VROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3772 case X86::VROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3773 case X86::VROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3774 case X86::VRSQRTSSr:
3775 case X86::VSQRTSSr:
3776 return true;
3777 }
3778
3779 return false;
3780}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3781
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]3782/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3783/// instructions we would like before a partial register update.
3784unsigned X86InstrInfo::
3785getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3786 const TargetRegisterInfo *TRI) const {
3787 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3788 return 0;
3789
3790 // If MI is marked as reading Reg, the partial register update is wanted.
3791 const MachineOperand &MO = MI->getOperand(0);
3792 unsigned Reg = MO.getReg();
3793 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3794 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3795 return 0;
3796 } else {
3797 if (MI->readsRegister(Reg, TRI))
3798 return 0;
3799 }
3800
3801 // If any of the preceding 16 instructions are reading Reg, insert a
3802 // dependency breaking instruction. The magic number is based on a few
3803 // Nehalem experiments.
3804 return 16;
3805}
3806
3807void X86InstrInfo::
3808breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3809 const TargetRegisterInfo *TRI) const {
3810 unsigned Reg = MI->getOperand(OpNum).getReg();
3811 if (X86::VR128RegClass.contains(Reg)) {
3812 // These instructions are all floating point domain, so xorps is the best
3813 // choice.
3814 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3815 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3816 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3817 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3818 } else if (X86::VR256RegClass.contains(Reg)) {
3819 // Use vxorps to clear the full ymm register.
3820 // It wants to read and write the xmm sub-register.
3821 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3822 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3823 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3824 .addReg(Reg, RegState::ImplicitDefine);
3825 } else
3826 return;
3827 MI->addRegisterKilled(Reg, TRI, true);
3828}
3829
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3830MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3831 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3832 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3833 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3834 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3835 if (NoFusing) return NULL;
3836
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3837 // Unless optimizing for size, don't fold to avoid partial
3838 // register update stalls
Bill Wendlingc9b22d72012-10-09 07:45:08 +0000[diff] [blame]3839 if (!MF.getFunction()->getFnAttributes().
3840 hasAttribute(Attributes::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3841 hasPartialRegUpdate(MI->getOpcode()))
3842 return 0;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]3843
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3844 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3845 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3846 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3847 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3848 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3849 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3850 switch (MI->getOpcode()) {
3851 default: return NULL;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3852 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]3853 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3854 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3855 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3856 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3857 // Check if it's safe to fold the load. If the size of the object is
3858 // narrower than the load width, then it's not.
3859 if (Size < RCSize)
3860 return NULL;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3861 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3862 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3863 MI->getOperand(1).ChangeToImmediate(0);
3864 } else if (Ops.size() != 1)
3865 return NULL;
3866
3867 SmallVector<MachineOperand,4> MOs;
3868 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3869 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3870}
3871
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3872MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3873 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3874 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3875 MachineInstr *LoadMI) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3876 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3877 if (NoFusing) return NULL;
3878
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3879 // Unless optimizing for size, don't fold to avoid partial
3880 // register update stalls
Bill Wendlingc9b22d72012-10-09 07:45:08 +0000[diff] [blame]3881 if (!MF.getFunction()->getFnAttributes().
3882 hasAttribute(Attributes::OptimizeForSize) &&
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3883 hasPartialRegUpdate(MI->getOpcode()))
3884 return 0;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]3885
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]3886 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3887 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]3888 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]3889 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3890 else
3891 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]3892 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]3893 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3894 Alignment = 32;
3895 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3896 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3897 case X86::V_SETALLONES:
3898 Alignment = 16;
3899 break;
3900 case X86::FsFLD0SD:
3901 Alignment = 8;
3902 break;
3903 case X86::FsFLD0SS:
3904 Alignment = 4;
3905 break;
3906 default:
Eli Friedman87ef3872011-06-10 01:13:01 +0000[diff] [blame]3907 return 0;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3908 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3909 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3910 unsigned NewOpc = 0;
3911 switch (MI->getOpcode()) {
3912 default: return NULL;
3913 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3914 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3915 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3916 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3917 }
3918 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3919 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3920 MI->getOperand(1).ChangeToImmediate(0);
3921 } else if (Ops.size() != 1)
3922 return NULL;
3923
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]3924 // Make sure the subregisters match.
3925 // Otherwise we risk changing the size of the load.
3926 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3927 return NULL;
3928
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3929 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3930 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3931 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3932 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]3933 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]3934 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3935 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3936 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3937 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3938 // Create a constant-pool entry and operands to load from it.
3939
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]3940 // Medium and large mode can't fold loads this way.
3941 if (TM.getCodeModel() != CodeModel::Small &&
3942 TM.getCodeModel() != CodeModel::Kernel)
3943 return NULL;
3944
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3945 // x86-32 PIC requires a PIC base register for constant pools.
3946 unsigned PICBase = 0;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3947 if (TM.getRelocationModel() == Reloc::PIC_) {
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]3948 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3949 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3950 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3951 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]3952 // This doesn't work for several reasons.
3953 // 1. GlobalBaseReg may have been spilled.
3954 // 2. It may not be live at MI.
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3955 return NULL;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3956 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3957
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3958 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3959 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]3960 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3961 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3962 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3963 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3964 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3965 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]3966 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]3967 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3968 else
3969 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3970
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]3971 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3972 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3973 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3974 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3975
3976 // Create operands to load from the constant pool entry.
3977 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3978 MOs.push_back(MachineOperand::CreateImm(1));
3979 MOs.push_back(MachineOperand::CreateReg(0, false));
3980 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]3981 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3982 break;
3983 }
3984 default: {
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]3985 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
3986 LoadMI->getOpcode() == X86::VMOVSSrm) &&
3987 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
3988 > 4)
3989 // These instructions only load 32 bits, we can't fold them if the
3990 // destination register is wider than 32 bits (4 bytes).
3991 return NULL;
3992 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
3993 LoadMI->getOpcode() == X86::VMOVSDrm) &&
3994 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
3995 > 8)
3996 // These instructions only load 64 bits, we can't fold them if the
3997 // destination register is wider than 64 bits (8 bytes).
3998 return NULL;
3999
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4000 // Folding a normal load. Just copy the load's address operands.
4001 unsigned NumOps = LoadMI->getDesc().getNumOperands();
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4002 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4003 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]4004 break;
4005 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]4006 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4007 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4008}
4009
4010
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]4011bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4012 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4013 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4014 if (NoFusing) return 0;
4015
4016 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4017 switch (MI->getOpcode()) {
4018 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4019 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4020 case X86::TEST16rr:
4021 case X86::TEST32rr:
4022 case X86::TEST64rr:
4023 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4024 case X86::ADD32ri:
4025 // FIXME: AsmPrinter doesn't know how to handle
4026 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4027 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4028 return false;
4029 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4030 }
4031 }
4032
4033 if (Ops.size() != 1)
4034 return false;
4035
4036 unsigned OpNum = Ops[0];
4037 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4038 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4039 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4040 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4041
4042 // Folding a memory location into the two-address part of a two-address
4043 // instruction is different than folding it other places. It requires
4044 // replacing the *two* registers with the memory location.
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4045 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4046 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4047 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4048 } else if (OpNum == 0) { // If operand 0
4049 switch (Opc) {
Chris Lattner79c136d2009-07-14 20:19:57 +0000[diff] [blame]4050 case X86::MOV8r0:
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]4051 case X86::MOV16r0:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4052 case X86::MOV32r0:
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4053 case X86::MOV64r0: return true;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4054 default: break;
4055 }
4056 OpcodeTablePtr = &RegOp2MemOpTable0;
4057 } else if (OpNum == 1) {
4058 OpcodeTablePtr = &RegOp2MemOpTable1;
4059 } else if (OpNum == 2) {
4060 OpcodeTablePtr = &RegOp2MemOpTable2;
Craig Topper7573c8f2012-08-31 22:12:16 +0000[diff] [blame]4061 } else if (OpNum == 3) {
4062 OpcodeTablePtr = &RegOp2MemOpTable3;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4063 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4064
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]4065 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4066 return true;
Jakob Stoklund Olesen9de596e2012-11-28 02:35:17 +0000[diff] [blame]4067 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4068}
4069
4070bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4071 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4072 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4073 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4074 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4075 if (I == MemOp2RegOpTable.end())
4076 return false;
4077 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4078 unsigned Index = I->second.second & TB_INDEX_MASK;
4079 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4080 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4081 if (UnfoldLoad && !FoldedLoad)
4082 return false;
4083 UnfoldLoad &= FoldedLoad;
4084 if (UnfoldStore && !FoldedStore)
4085 return false;
4086 UnfoldStore &= FoldedStore;
4087
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4088 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4089 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4090 if (!MI->hasOneMemOperand() &&
4091 RC == &X86::VR128RegClass &&
4092 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4093 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4094 // conservatively assume the address is unaligned. That's bad for
4095 // performance.
4096 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4097 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4098 SmallVector<MachineOperand,2> BeforeOps;
4099 SmallVector<MachineOperand,2> AfterOps;
4100 SmallVector<MachineOperand,4> ImpOps;
4101 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4102 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4103 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4104 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4105 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4106 ImpOps.push_back(Op);
4107 else if (i < Index)
4108 BeforeOps.push_back(Op);
4109 else if (i > Index)
4110 AfterOps.push_back(Op);
4111 }
4112
4113 // Emit the load instruction.
4114 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4115 std::pair<MachineInstr::mmo_iterator,
4116 MachineInstr::mmo_iterator> MMOs =
4117 MF.extractLoadMemRefs(MI->memoperands_begin(),
4118 MI->memoperands_end());
4119 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4120 if (UnfoldStore) {
4121 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4122 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4123 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4124 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4125 MO.setIsKill(false);
4126 }
4127 }
4128 }
4129
4130 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4131 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4132 MachineInstrBuilder MIB(DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4133
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4134 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4135 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4136 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4137 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4138 if (FoldedLoad)
4139 MIB.addReg(Reg);
4140 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4141 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4142 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4143 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4144 MIB.addReg(MO.getReg(),
4145 getDefRegState(MO.isDef()) |
4146 RegState::Implicit |
4147 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]4148 getDeadRegState(MO.isDead()) |
4149 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4150 }
4151 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4152 switch (DataMI->getOpcode()) {
4153 default: break;
4154 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4155 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4156 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4157 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4158 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4159 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4160 case X86::CMP8ri: {
4161 MachineOperand &MO0 = DataMI->getOperand(0);
4162 MachineOperand &MO1 = DataMI->getOperand(1);
4163 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4164 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4165 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4166 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4167 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4168 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4169 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4170 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]4171 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4172 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
4173 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
4174 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]4175 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4176 MO1.ChangeToRegister(MO0.getReg(), false);
4177 }
4178 }
4179 }
4180 NewMIs.push_back(DataMI);
4181
4182 // Emit the store instruction.
4183 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4184 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4185 std::pair<MachineInstr::mmo_iterator,
4186 MachineInstr::mmo_iterator> MMOs =
4187 MF.extractStoreMemRefs(MI->memoperands_begin(),
4188 MI->memoperands_end());
4189 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4190 }
4191
4192 return true;
4193}
4194
4195bool
4196X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4197 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]4198 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4199 return false;
4200
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4201 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4202 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4203 if (I == MemOp2RegOpTable.end())
4204 return false;
4205 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4206 unsigned Index = I->second.second & TB_INDEX_MASK;
4207 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4208 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4209 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4210 MachineFunction &MF = DAG.getMachineFunction();
4211 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4212 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4213 std::vector<SDValue> AddrOps;
4214 std::vector<SDValue> BeforeOps;
4215 std::vector<SDValue> AfterOps;
Dale Johannesen9f3f72f2009-02-06 01:31:28 +0000[diff] [blame]4216 DebugLoc dl = N->getDebugLoc();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4217 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]4218 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4219 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]4220 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4221 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4222 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4223 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]4224 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4225 AfterOps.push_back(Op);
4226 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4227 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4228 AddrOps.push_back(Chain);
4229
4230 // Emit the load instruction.
4231 SDNode *Load = 0;
4232 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4233 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4234 std::pair<MachineInstr::mmo_iterator,
4235 MachineInstr::mmo_iterator> MMOs =
4236 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4237 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4238 if (!(*MMOs.first) &&
4239 RC == &X86::VR128RegClass &&
4240 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4241 // Do not introduce a slow unaligned load.
4242 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4243 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4244 bool isAligned = (*MMOs.first) &&
4245 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]4246 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4247 VT, MVT::Other, &AddrOps[0], AddrOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4248 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4249
4250 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4251 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4252 }
4253
4254 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4255 std::vector<EVT> VTs;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4256 const TargetRegisterClass *DstRC = 0;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4257 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]4258 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4259 VTs.push_back(*DstRC->vt_begin());
4260 }
4261 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]4262 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4263 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4264 VTs.push_back(VT);
4265 }
4266 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4267 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4268 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]4269 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
4270 BeforeOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4271 NewNodes.push_back(NewNode);
4272
4273 // Emit the store instruction.
4274 if (FoldedStore) {
4275 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]4276 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4277 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]4278 std::pair<MachineInstr::mmo_iterator,
4279 MachineInstr::mmo_iterator> MMOs =
4280 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4281 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]4282 if (!(*MMOs.first) &&
4283 RC == &X86::VR128RegClass &&
4284 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4285 // Do not introduce a slow unaligned store.
4286 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4287 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4288 bool isAligned = (*MMOs.first) &&
4289 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]4290 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4291 isAligned, TM),
4292 dl, MVT::Other,
4293 &AddrOps[0], AddrOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4294 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4295
4296 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4297 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4298 }
4299
4300 return true;
4301}
4302
4303unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4304 bool UnfoldLoad, bool UnfoldStore,
4305 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4306 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4307 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4308 if (I == MemOp2RegOpTable.end())
4309 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4310 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4311 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4312 if (UnfoldLoad && !FoldedLoad)
4313 return 0;
4314 if (UnfoldStore && !FoldedStore)
4315 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]4316 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4317 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4318 return I->second.first;
4319}
4320
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4321bool
4322X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4323 int64_t &Offset1, int64_t &Offset2) const {
4324 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4325 return false;
4326 unsigned Opc1 = Load1->getMachineOpcode();
4327 unsigned Opc2 = Load2->getMachineOpcode();
4328 switch (Opc1) {
4329 default: return false;
4330 case X86::MOV8rm:
4331 case X86::MOV16rm:
4332 case X86::MOV32rm:
4333 case X86::MOV64rm:
4334 case X86::LD_Fp32m:
4335 case X86::LD_Fp64m:
4336 case X86::LD_Fp80m:
4337 case X86::MOVSSrm:
4338 case X86::MOVSDrm:
4339 case X86::MMX_MOVD64rm:
4340 case X86::MMX_MOVQ64rm:
4341 case X86::FsMOVAPSrm:
4342 case X86::FsMOVAPDrm:
4343 case X86::MOVAPSrm:
4344 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4345 case X86::MOVAPDrm:
4346 case X86::MOVDQArm:
4347 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]4348 // AVX load instructions
4349 case X86::VMOVSSrm:
4350 case X86::VMOVSDrm:
4351 case X86::FsVMOVAPSrm:
4352 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4353 case X86::VMOVAPSrm:
4354 case X86::VMOVUPSrm:
4355 case X86::VMOVAPDrm:
4356 case X86::VMOVDQArm:
4357 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4358 case X86::VMOVAPSYrm:
4359 case X86::VMOVUPSYrm:
4360 case X86::VMOVAPDYrm:
4361 case X86::VMOVDQAYrm:
4362 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4363 break;
4364 }
4365 switch (Opc2) {
4366 default: return false;
4367 case X86::MOV8rm:
4368 case X86::MOV16rm:
4369 case X86::MOV32rm:
4370 case X86::MOV64rm:
4371 case X86::LD_Fp32m:
4372 case X86::LD_Fp64m:
4373 case X86::LD_Fp80m:
4374 case X86::MOVSSrm:
4375 case X86::MOVSDrm:
4376 case X86::MMX_MOVD64rm:
4377 case X86::MMX_MOVQ64rm:
4378 case X86::FsMOVAPSrm:
4379 case X86::FsMOVAPDrm:
4380 case X86::MOVAPSrm:
4381 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4382 case X86::MOVAPDrm:
4383 case X86::MOVDQArm:
4384 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]4385 // AVX load instructions
4386 case X86::VMOVSSrm:
4387 case X86::VMOVSDrm:
4388 case X86::FsVMOVAPSrm:
4389 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4390 case X86::VMOVAPSrm:
4391 case X86::VMOVUPSrm:
4392 case X86::VMOVAPDrm:
4393 case X86::VMOVDQArm:
4394 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4395 case X86::VMOVAPSYrm:
4396 case X86::VMOVUPSYrm:
4397 case X86::VMOVAPDYrm:
4398 case X86::VMOVDQAYrm:
4399 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4400 break;
4401 }
4402
4403 // Check if chain operands and base addresses match.
4404 if (Load1->getOperand(0) != Load2->getOperand(0) ||
4405 Load1->getOperand(5) != Load2->getOperand(5))
4406 return false;
4407 // Segment operands should match as well.
4408 if (Load1->getOperand(4) != Load2->getOperand(4))
4409 return false;
4410 // Scale should be 1, Index should be Reg0.
4411 if (Load1->getOperand(1) == Load2->getOperand(1) &&
4412 Load1->getOperand(2) == Load2->getOperand(2)) {
4413 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4414 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4415
4416 // Now let's examine the displacements.
4417 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4418 isa<ConstantSDNode>(Load2->getOperand(3))) {
4419 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4420 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4421 return true;
4422 }
4423 }
4424 return false;
4425}
4426
4427bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4428 int64_t Offset1, int64_t Offset2,
4429 unsigned NumLoads) const {
4430 assert(Offset2 > Offset1);
4431 if ((Offset2 - Offset1) / 8 > 64)
4432 return false;
4433
4434 unsigned Opc1 = Load1->getMachineOpcode();
4435 unsigned Opc2 = Load2->getMachineOpcode();
4436 if (Opc1 != Opc2)
4437 return false; // FIXME: overly conservative?
4438
4439 switch (Opc1) {
4440 default: break;
4441 case X86::LD_Fp32m:
4442 case X86::LD_Fp64m:
4443 case X86::LD_Fp80m:
4444 case X86::MMX_MOVD64rm:
4445 case X86::MMX_MOVQ64rm:
4446 return false;
4447 }
4448
4449 EVT VT = Load1->getValueType(0);
4450 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4451 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4452 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4453 // have 16 of them to play with.
4454 if (TM.getSubtargetImpl()->is64Bit()) {
4455 if (NumLoads >= 3)
4456 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4457 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4458 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4459 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4460 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4461 case MVT::i8:
4462 case MVT::i16:
4463 case MVT::i32:
4464 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]4465 case MVT::f32:
4466 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4467 if (NumLoads)
4468 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]4469 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]4470 }
4471
4472 return true;
4473}
4474
4475
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4476bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]4477ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4478 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]4479 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4480 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
4481 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]4482 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]4483 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4484}
4485
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]4486bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]4487isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
4488 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]4489 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]4490 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
4491 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]4492}
4493
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]4494/// getGlobalBaseReg - Return a virtual register initialized with the
4495/// the global base register value. Output instructions required to
4496/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]4497///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4498/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
4499///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]4500unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
4501 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
4502 "X86-64 PIC uses RIP relative addressing");
4503
4504 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
4505 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4506 if (GlobalBaseReg != 0)
4507 return GlobalBaseReg;
4508
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4509 // Create the register. The code to initialize it is inserted
4510 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]4511 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]4512 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]4513 X86FI->setGlobalBaseReg(GlobalBaseReg);
4514 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]4515}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]4516
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4517// These are the replaceable SSE instructions. Some of these have Int variants
4518// that we don't include here. We don't want to replace instructions selected
4519// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]4520static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]4521 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]4522 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
4523 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
4524 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
4525 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
4526 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
4527 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
4528 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
4529 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
4530 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
4531 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
4532 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
4533 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
4534 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
4535 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4536 // AVX 128-bit support
4537 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
4538 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
4539 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
4540 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
4541 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
4542 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
4543 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
4544 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
4545 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
4546 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
4547 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
4548 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]4549 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
4550 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4551 // AVX 256-bit support
4552 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
4553 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
4554 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
4555 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
4556 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]4557 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
4558};
4559
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]4560static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]4561 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]4562 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
4563 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
4564 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
4565 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
4566 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
4567 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
4568 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]4569 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
4570 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
4571 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
4572 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
4573 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
4574 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
4575 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4576};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]4577
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4578// FIXME: Some shuffle and unpack instructions have equivalents in different
4579// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]4580
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]4581static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]4582 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4583 if (ReplaceableInstrs[i][domain-1] == opcode)
4584 return ReplaceableInstrs[i];
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]4585 return 0;
4586}
4587
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]4588static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]4589 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
4590 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
4591 return ReplaceableInstrsAVX2[i];
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4592 return 0;
4593}
4594
4595std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]4596X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4597 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]4598 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]4599 uint16_t validDomains = 0;
4600 if (domain && lookup(MI->getOpcode(), domain))
4601 validDomains = 0xe;
4602 else if (domain && lookupAVX2(MI->getOpcode(), domain))
4603 validDomains = hasAVX2 ? 0xe : 0x6;
4604 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4605}
4606
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]4607void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4608 assert(Domain>0 && Domain<4 && "Invalid execution domain");
4609 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
4610 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]4611 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]4612 if (!table) { // try the other table
4613 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
4614 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]4615 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]4616 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]4617 assert(table && "Cannot change domain");
4618 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]4619}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]4620
4621/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
4622void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
4623 NopInst.setOpcode(X86::NOOP);
4624}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4625
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]4626bool X86InstrInfo::isHighLatencyDef(int opc) const {
4627 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]4628 default: return false;
4629 case X86::DIVSDrm:
4630 case X86::DIVSDrm_Int:
4631 case X86::DIVSDrr:
4632 case X86::DIVSDrr_Int:
4633 case X86::DIVSSrm:
4634 case X86::DIVSSrm_Int:
4635 case X86::DIVSSrr:
4636 case X86::DIVSSrr_Int:
4637 case X86::SQRTPDm:
4638 case X86::SQRTPDm_Int:
4639 case X86::SQRTPDr:
4640 case X86::SQRTPDr_Int:
4641 case X86::SQRTPSm:
4642 case X86::SQRTPSm_Int:
4643 case X86::SQRTPSr:
4644 case X86::SQRTPSr_Int:
4645 case X86::SQRTSDm:
4646 case X86::SQRTSDm_Int:
4647 case X86::SQRTSDr:
4648 case X86::SQRTSDr_Int:
4649 case X86::SQRTSSm:
4650 case X86::SQRTSSm_Int:
4651 case X86::SQRTSSr:
4652 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]4653 // AVX instructions with high latency
4654 case X86::VDIVSDrm:
4655 case X86::VDIVSDrm_Int:
4656 case X86::VDIVSDrr:
4657 case X86::VDIVSDrr_Int:
4658 case X86::VDIVSSrm:
4659 case X86::VDIVSSrm_Int:
4660 case X86::VDIVSSrr:
4661 case X86::VDIVSSrr_Int:
4662 case X86::VSQRTPDm:
4663 case X86::VSQRTPDm_Int:
4664 case X86::VSQRTPDr:
4665 case X86::VSQRTPDr_Int:
4666 case X86::VSQRTPSm:
4667 case X86::VSQRTPSm_Int:
4668 case X86::VSQRTPSr:
4669 case X86::VSQRTPSr_Int:
4670 case X86::VSQRTSDm:
4671 case X86::VSQRTSDm_Int:
4672 case X86::VSQRTSDr:
4673 case X86::VSQRTSSm:
4674 case X86::VSQRTSSm_Int:
4675 case X86::VSQRTSSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]4676 return true;
4677 }
4678}
4679
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]4680bool X86InstrInfo::
4681hasHighOperandLatency(const InstrItineraryData *ItinData,
4682 const MachineRegisterInfo *MRI,
4683 const MachineInstr *DefMI, unsigned DefIdx,
4684 const MachineInstr *UseMI, unsigned UseIdx) const {
4685 return isHighLatencyDef(DefMI->getOpcode());
4686}
4687
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4688namespace {
4689 /// CGBR - Create Global Base Reg pass. This initializes the PIC
4690 /// global base register for x86-32.
4691 struct CGBR : public MachineFunctionPass {
4692 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]4693 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4694
4695 virtual bool runOnMachineFunction(MachineFunction &MF) {
4696 const X86TargetMachine *TM =
4697 static_cast<const X86TargetMachine *>(&MF.getTarget());
4698
4699 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
4700 "X86-64 PIC uses RIP relative addressing");
4701
4702 // Only emit a global base reg in PIC mode.
4703 if (TM->getRelocationModel() != Reloc::PIC_)
4704 return false;
4705
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]4706 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
4707 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4708
4709 // If we didn't need a GlobalBaseReg, don't insert code.
4710 if (GlobalBaseReg == 0)
4711 return false;
4712
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4713 // Insert the set of GlobalBaseReg into the first MBB of the function
4714 MachineBasicBlock &FirstMBB = MF.front();
4715 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
4716 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
4717 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4718 const X86InstrInfo *TII = TM->getInstrInfo();
4719
4720 unsigned PC;
4721 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]4722 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4723 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]4724 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4725
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4726 // Operand of MovePCtoStack is completely ignored by asm printer. It's
4727 // only used in JIT code emission as displacement to pc.
4728 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4729
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4730 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
4731 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
4732 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4733 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
4734 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4735 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
4736 X86II::MO_GOT_ABSOLUTE_ADDRESS);
4737 }
4738
4739 return true;
4740 }
4741
4742 virtual const char *getPassName() const {
4743 return "X86 PIC Global Base Reg Initialization";
4744 }
4745
4746 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4747 AU.setPreservesCFG();
4748 MachineFunctionPass::getAnalysisUsage(AU);
4749 }
4750 };
4751}
4752
4753char CGBR::ID = 0;
4754FunctionPass*
4755llvm::createGlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]4756
4757namespace {
4758 struct LDTLSCleanup : public MachineFunctionPass {
4759 static char ID;
4760 LDTLSCleanup() : MachineFunctionPass(ID) {}
4761
4762 virtual bool runOnMachineFunction(MachineFunction &MF) {
4763 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
4764 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
4765 // No point folding accesses if there isn't at least two.
4766 return false;
4767 }
4768
4769 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
4770 return VisitNode(DT->getRootNode(), 0);
4771 }
4772
4773 // Visit the dominator subtree rooted at Node in pre-order.
4774 // If TLSBaseAddrReg is non-null, then use that to replace any
4775 // TLS_base_addr instructions. Otherwise, create the register
4776 // when the first such instruction is seen, and then use it
4777 // as we encounter more instructions.
4778 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
4779 MachineBasicBlock *BB = Node->getBlock();
4780 bool Changed = false;
4781
4782 // Traverse the current block.
4783 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
4784 ++I) {
4785 switch (I->getOpcode()) {
4786 case X86::TLS_base_addr32:
4787 case X86::TLS_base_addr64:
4788 if (TLSBaseAddrReg)
4789 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
4790 else
4791 I = SetRegister(I, &TLSBaseAddrReg);
4792 Changed = true;
4793 break;
4794 default:
4795 break;
4796 }
4797 }
4798
4799 // Visit the children of this block in the dominator tree.
4800 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
4801 I != E; ++I) {
4802 Changed |= VisitNode(*I, TLSBaseAddrReg);
4803 }
4804
4805 return Changed;
4806 }
4807
4808 // Replace the TLS_base_addr instruction I with a copy from
4809 // TLSBaseAddrReg, returning the new instruction.
4810 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
4811 unsigned TLSBaseAddrReg) {
4812 MachineFunction *MF = I->getParent()->getParent();
4813 const X86TargetMachine *TM =
4814 static_cast<const X86TargetMachine *>(&MF->getTarget());
4815 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4816 const X86InstrInfo *TII = TM->getInstrInfo();
4817
4818 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
4819 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
4820 TII->get(TargetOpcode::COPY),
4821 is64Bit ? X86::RAX : X86::EAX)
4822 .addReg(TLSBaseAddrReg);
4823
4824 // Erase the TLS_base_addr instruction.
4825 I->eraseFromParent();
4826
4827 return Copy;
4828 }
4829
4830 // Create a virtal register in *TLSBaseAddrReg, and populate it by
4831 // inserting a copy instruction after I. Returns the new instruction.
4832 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
4833 MachineFunction *MF = I->getParent()->getParent();
4834 const X86TargetMachine *TM =
4835 static_cast<const X86TargetMachine *>(&MF->getTarget());
4836 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4837 const X86InstrInfo *TII = TM->getInstrInfo();
4838
4839 // Create a virtual register for the TLS base address.
4840 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4841 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
4842 ? &X86::GR64RegClass
4843 : &X86::GR32RegClass);
4844
4845 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
4846 MachineInstr *Next = I->getNextNode();
4847 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
4848 TII->get(TargetOpcode::COPY),
4849 *TLSBaseAddrReg)
4850 .addReg(is64Bit ? X86::RAX : X86::EAX);
4851
4852 return Copy;
4853 }
4854
4855 virtual const char *getPassName() const {
4856 return "Local Dynamic TLS Access Clean-up";
4857 }
4858
4859 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4860 AU.setPreservesCFG();
4861 AU.addRequired<MachineDominatorTree>();
4862 MachineFunctionPass::getAnalysisUsage(AU);
4863 }
4864 };
4865}
4866
4867char LDTLSCleanup::ID = 0;
4868FunctionPass*
4869llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }