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gerrit-public.fairphone.software / toolchain / llvm-project / c6ac4cefcca36e131b42cb4ff75223dcafc21dfa / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: b8c29ac8957ec92b39031439131f5604c0602add [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]20#include "llvm/DerivedTypes.h"
Owen Anderson53a52212009-07-13 04:09:18 +0000[diff] [blame]21#include "llvm/LLVMContext.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]22#include "llvm/ADT/STLExtras.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]27#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]28#include "llvm/CodeGen/LiveVariables.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]29#include "llvm/MC/MCAsmInfo.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]30#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]31#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]32#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]35#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]36#include <limits>
37
Evan Cheng703a0fb2011-07-01 17:57:27 +0000[diff] [blame]38#define GET_INSTRINFO_CTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]39#include "X86GenInstrInfo.inc"
40
Brian Gaeke960707c2003-11-11 22:41:34 +0000[diff] [blame]41using namespace llvm;
42
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]43static cl::opt<bool>
44NoFusing("disable-spill-fusing",
45 cl::desc("Disable fusing of spill code into instructions"));
46static cl::opt<bool>
47PrintFailedFusing("print-failed-fuse-candidates",
48 cl::desc("Print instructions that the allocator wants to"
49 " fuse, but the X86 backend currently can't"),
50 cl::Hidden);
51static cl::opt<bool>
52ReMatPICStubLoad("remat-pic-stub-load",
53 cl::desc("Re-materialize load from stub in PIC mode"),
54 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]55
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]56enum {
57 // Select which memory operand is being unfolded.
58 // (stored in bits 0 - 7)
59 TB_INDEX_0 = 0,
60 TB_INDEX_1 = 1,
61 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]62 TB_INDEX_3 = 3,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]63 TB_INDEX_MASK = 0xff,
64
65 // Minimum alignment required for load/store.
66 // Used for RegOp->MemOp conversion.
67 // (stored in bits 8 - 15)
68 TB_ALIGN_SHIFT = 8,
69 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
70 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
71 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
72 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
73
74 // Do not insert the reverse map (MemOp -> RegOp) into the table.
75 // This may be needed because there is a many -> one mapping.
76 TB_NO_REVERSE = 1 << 16,
77
78 // Do not insert the forward map (RegOp -> MemOp) into the table.
79 // This is needed for Native Client, which prohibits branch
80 // instructions from using a memory operand.
81 TB_NO_FORWARD = 1 << 17,
82
83 TB_FOLDED_LOAD = 1 << 18,
84 TB_FOLDED_STORE = 1 << 19
85};
86
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]87struct X86OpTblEntry {
88 uint16_t RegOp;
89 uint16_t MemOp;
90 uint32_t Flags;
91};
92
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]93X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
Evan Cheng703a0fb2011-07-01 17:57:27 +0000[diff] [blame]94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
95 ? X86::ADJCALLSTACKDOWN64
96 : X86::ADJCALLSTACKDOWN32),
97 (tm.getSubtarget<X86Subtarget>().is64Bit()
98 ? X86::ADJCALLSTACKUP64
99 : X86::ADJCALLSTACKUP32)),
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]100 TM(tm), RI(tm, *this) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]101
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]102 static const X86OpTblEntry OpTbl2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]103 { X86::ADC32ri, X86::ADC32mi, 0 },
104 { X86::ADC32ri8, X86::ADC32mi8, 0 },
105 { X86::ADC32rr, X86::ADC32mr, 0 },
106 { X86::ADC64ri32, X86::ADC64mi32, 0 },
107 { X86::ADC64ri8, X86::ADC64mi8, 0 },
108 { X86::ADC64rr, X86::ADC64mr, 0 },
109 { X86::ADD16ri, X86::ADD16mi, 0 },
110 { X86::ADD16ri8, X86::ADD16mi8, 0 },
111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
113 { X86::ADD16rr, X86::ADD16mr, 0 },
114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
115 { X86::ADD32ri, X86::ADD32mi, 0 },
116 { X86::ADD32ri8, X86::ADD32mi8, 0 },
117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
119 { X86::ADD32rr, X86::ADD32mr, 0 },
120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
121 { X86::ADD64ri32, X86::ADD64mi32, 0 },
122 { X86::ADD64ri8, X86::ADD64mi8, 0 },
123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
125 { X86::ADD64rr, X86::ADD64mr, 0 },
126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
127 { X86::ADD8ri, X86::ADD8mi, 0 },
128 { X86::ADD8rr, X86::ADD8mr, 0 },
129 { X86::AND16ri, X86::AND16mi, 0 },
130 { X86::AND16ri8, X86::AND16mi8, 0 },
131 { X86::AND16rr, X86::AND16mr, 0 },
132 { X86::AND32ri, X86::AND32mi, 0 },
133 { X86::AND32ri8, X86::AND32mi8, 0 },
134 { X86::AND32rr, X86::AND32mr, 0 },
135 { X86::AND64ri32, X86::AND64mi32, 0 },
136 { X86::AND64ri8, X86::AND64mi8, 0 },
137 { X86::AND64rr, X86::AND64mr, 0 },
138 { X86::AND8ri, X86::AND8mi, 0 },
139 { X86::AND8rr, X86::AND8mr, 0 },
140 { X86::DEC16r, X86::DEC16m, 0 },
141 { X86::DEC32r, X86::DEC32m, 0 },
142 { X86::DEC64_16r, X86::DEC64_16m, 0 },
143 { X86::DEC64_32r, X86::DEC64_32m, 0 },
144 { X86::DEC64r, X86::DEC64m, 0 },
145 { X86::DEC8r, X86::DEC8m, 0 },
146 { X86::INC16r, X86::INC16m, 0 },
147 { X86::INC32r, X86::INC32m, 0 },
148 { X86::INC64_16r, X86::INC64_16m, 0 },
149 { X86::INC64_32r, X86::INC64_32m, 0 },
150 { X86::INC64r, X86::INC64m, 0 },
151 { X86::INC8r, X86::INC8m, 0 },
152 { X86::NEG16r, X86::NEG16m, 0 },
153 { X86::NEG32r, X86::NEG32m, 0 },
154 { X86::NEG64r, X86::NEG64m, 0 },
155 { X86::NEG8r, X86::NEG8m, 0 },
156 { X86::NOT16r, X86::NOT16m, 0 },
157 { X86::NOT32r, X86::NOT32m, 0 },
158 { X86::NOT64r, X86::NOT64m, 0 },
159 { X86::NOT8r, X86::NOT8m, 0 },
160 { X86::OR16ri, X86::OR16mi, 0 },
161 { X86::OR16ri8, X86::OR16mi8, 0 },
162 { X86::OR16rr, X86::OR16mr, 0 },
163 { X86::OR32ri, X86::OR32mi, 0 },
164 { X86::OR32ri8, X86::OR32mi8, 0 },
165 { X86::OR32rr, X86::OR32mr, 0 },
166 { X86::OR64ri32, X86::OR64mi32, 0 },
167 { X86::OR64ri8, X86::OR64mi8, 0 },
168 { X86::OR64rr, X86::OR64mr, 0 },
169 { X86::OR8ri, X86::OR8mi, 0 },
170 { X86::OR8rr, X86::OR8mr, 0 },
171 { X86::ROL16r1, X86::ROL16m1, 0 },
172 { X86::ROL16rCL, X86::ROL16mCL, 0 },
173 { X86::ROL16ri, X86::ROL16mi, 0 },
174 { X86::ROL32r1, X86::ROL32m1, 0 },
175 { X86::ROL32rCL, X86::ROL32mCL, 0 },
176 { X86::ROL32ri, X86::ROL32mi, 0 },
177 { X86::ROL64r1, X86::ROL64m1, 0 },
178 { X86::ROL64rCL, X86::ROL64mCL, 0 },
179 { X86::ROL64ri, X86::ROL64mi, 0 },
180 { X86::ROL8r1, X86::ROL8m1, 0 },
181 { X86::ROL8rCL, X86::ROL8mCL, 0 },
182 { X86::ROL8ri, X86::ROL8mi, 0 },
183 { X86::ROR16r1, X86::ROR16m1, 0 },
184 { X86::ROR16rCL, X86::ROR16mCL, 0 },
185 { X86::ROR16ri, X86::ROR16mi, 0 },
186 { X86::ROR32r1, X86::ROR32m1, 0 },
187 { X86::ROR32rCL, X86::ROR32mCL, 0 },
188 { X86::ROR32ri, X86::ROR32mi, 0 },
189 { X86::ROR64r1, X86::ROR64m1, 0 },
190 { X86::ROR64rCL, X86::ROR64mCL, 0 },
191 { X86::ROR64ri, X86::ROR64mi, 0 },
192 { X86::ROR8r1, X86::ROR8m1, 0 },
193 { X86::ROR8rCL, X86::ROR8mCL, 0 },
194 { X86::ROR8ri, X86::ROR8mi, 0 },
195 { X86::SAR16r1, X86::SAR16m1, 0 },
196 { X86::SAR16rCL, X86::SAR16mCL, 0 },
197 { X86::SAR16ri, X86::SAR16mi, 0 },
198 { X86::SAR32r1, X86::SAR32m1, 0 },
199 { X86::SAR32rCL, X86::SAR32mCL, 0 },
200 { X86::SAR32ri, X86::SAR32mi, 0 },
201 { X86::SAR64r1, X86::SAR64m1, 0 },
202 { X86::SAR64rCL, X86::SAR64mCL, 0 },
203 { X86::SAR64ri, X86::SAR64mi, 0 },
204 { X86::SAR8r1, X86::SAR8m1, 0 },
205 { X86::SAR8rCL, X86::SAR8mCL, 0 },
206 { X86::SAR8ri, X86::SAR8mi, 0 },
207 { X86::SBB32ri, X86::SBB32mi, 0 },
208 { X86::SBB32ri8, X86::SBB32mi8, 0 },
209 { X86::SBB32rr, X86::SBB32mr, 0 },
210 { X86::SBB64ri32, X86::SBB64mi32, 0 },
211 { X86::SBB64ri8, X86::SBB64mi8, 0 },
212 { X86::SBB64rr, X86::SBB64mr, 0 },
213 { X86::SHL16rCL, X86::SHL16mCL, 0 },
214 { X86::SHL16ri, X86::SHL16mi, 0 },
215 { X86::SHL32rCL, X86::SHL32mCL, 0 },
216 { X86::SHL32ri, X86::SHL32mi, 0 },
217 { X86::SHL64rCL, X86::SHL64mCL, 0 },
218 { X86::SHL64ri, X86::SHL64mi, 0 },
219 { X86::SHL8rCL, X86::SHL8mCL, 0 },
220 { X86::SHL8ri, X86::SHL8mi, 0 },
221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
227 { X86::SHR16r1, X86::SHR16m1, 0 },
228 { X86::SHR16rCL, X86::SHR16mCL, 0 },
229 { X86::SHR16ri, X86::SHR16mi, 0 },
230 { X86::SHR32r1, X86::SHR32m1, 0 },
231 { X86::SHR32rCL, X86::SHR32mCL, 0 },
232 { X86::SHR32ri, X86::SHR32mi, 0 },
233 { X86::SHR64r1, X86::SHR64m1, 0 },
234 { X86::SHR64rCL, X86::SHR64mCL, 0 },
235 { X86::SHR64ri, X86::SHR64mi, 0 },
236 { X86::SHR8r1, X86::SHR8m1, 0 },
237 { X86::SHR8rCL, X86::SHR8mCL, 0 },
238 { X86::SHR8ri, X86::SHR8mi, 0 },
239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
245 { X86::SUB16ri, X86::SUB16mi, 0 },
246 { X86::SUB16ri8, X86::SUB16mi8, 0 },
247 { X86::SUB16rr, X86::SUB16mr, 0 },
248 { X86::SUB32ri, X86::SUB32mi, 0 },
249 { X86::SUB32ri8, X86::SUB32mi8, 0 },
250 { X86::SUB32rr, X86::SUB32mr, 0 },
251 { X86::SUB64ri32, X86::SUB64mi32, 0 },
252 { X86::SUB64ri8, X86::SUB64mi8, 0 },
253 { X86::SUB64rr, X86::SUB64mr, 0 },
254 { X86::SUB8ri, X86::SUB8mi, 0 },
255 { X86::SUB8rr, X86::SUB8mr, 0 },
256 { X86::XOR16ri, X86::XOR16mi, 0 },
257 { X86::XOR16ri8, X86::XOR16mi8, 0 },
258 { X86::XOR16rr, X86::XOR16mr, 0 },
259 { X86::XOR32ri, X86::XOR32mi, 0 },
260 { X86::XOR32ri8, X86::XOR32mi8, 0 },
261 { X86::XOR32rr, X86::XOR32mr, 0 },
262 { X86::XOR64ri32, X86::XOR64mi32, 0 },
263 { X86::XOR64ri8, X86::XOR64mi8, 0 },
264 { X86::XOR64rr, X86::XOR64mr, 0 },
265 { X86::XOR8ri, X86::XOR8mi, 0 },
266 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]267 };
268
269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]270 unsigned RegOp = OpTbl2Addr[i].RegOp;
271 unsigned MemOp = OpTbl2Addr[i].MemOp;
272 unsigned Flags = OpTbl2Addr[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274 RegOp, MemOp,
275 // Index 0, folded load and store, no alignment requirement.
276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]277 }
278
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]279 static const X86OpTblEntry OpTbl0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
357 // AVX 128-bit versions of foldable instructions
358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
371 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]378 };
379
380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]381 unsigned RegOp = OpTbl0[i].RegOp;
382 unsigned MemOp = OpTbl0[i].MemOp;
383 unsigned Flags = OpTbl0[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385 RegOp, MemOp, TB_INDEX_0 | Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]386 }
387
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]388 static const X86OpTblEntry OpTbl1[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]389 { X86::CMP16rr, X86::CMP16rm, 0 },
390 { X86::CMP32rr, X86::CMP32rm, 0 },
391 { X86::CMP64rr, X86::CMP64rm, 0 },
392 { X86::CMP8rr, X86::CMP8rm, 0 },
393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]405 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
407 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
413 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
414 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
415 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
416 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
417 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
418 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
419 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
420 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
421 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
422 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
423 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
424 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
425 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
426 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
427 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
428 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
429 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
430 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
431 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
432 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
433 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
434 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]435 { X86::MOV16rr, X86::MOV16rm, 0 },
436 { X86::MOV32rr, X86::MOV32rm, 0 },
437 { X86::MOV64rr, X86::MOV64rm, 0 },
438 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
439 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
440 { X86::MOV8rr, X86::MOV8rm, 0 },
441 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
442 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]443 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
444 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
445 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
446 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]447 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
448 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
449 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
450 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
451 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
452 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
453 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
454 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
455 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
456 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]457 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
458 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
459 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
460 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
461 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
462 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
463 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
464 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
465 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
466 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]467 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
468 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
469 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]470 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
471 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
472 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
473 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
474 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
475 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
476 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
477 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
478 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
479 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
480 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
481 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
482 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
483 { X86::SQRTSDr, X86::SQRTSDm, 0 },
484 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
485 { X86::SQRTSSr, X86::SQRTSSm, 0 },
486 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
487 { X86::TEST16rr, X86::TEST16rm, 0 },
488 { X86::TEST32rr, X86::TEST32rm, 0 },
489 { X86::TEST64rr, X86::TEST64rm, 0 },
490 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]491 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]492 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
493 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]494 // AVX 128-bit versions of foldable instructions
495 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
496 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
497 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
498 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
499 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
500 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
501 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
502 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
503 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
504 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
505 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
506 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
507 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
508 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
509 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
510 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
511 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
512 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
513 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
514 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
515 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
516 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
517 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
518 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
519 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
520 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
521 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]522 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
523 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
524 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]525 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]526 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]527 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
528 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
529 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
530 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
531 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
532 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
533 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
534 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
535 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
536 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
537 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]538 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]539 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
540 // AVX 256-bit foldable instructions
541 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
542 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]543 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]544 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]545 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]546 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 },
547 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]548 // AVX2 foldable instructions
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]549 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 },
550 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 },
551 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 },
552 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 },
553 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 },
554 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 },
555 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 },
556 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 },
557 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 },
558 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 },
559 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 },
560 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 },
561 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 },
562 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]563 };
564
565 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]566 unsigned RegOp = OpTbl1[i].RegOp;
567 unsigned MemOp = OpTbl1[i].MemOp;
568 unsigned Flags = OpTbl1[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]569 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
570 RegOp, MemOp,
571 // Index 1, folded load
572 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]573 }
574
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]575 static const X86OpTblEntry OpTbl2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]576 { X86::ADC32rr, X86::ADC32rm, 0 },
577 { X86::ADC64rr, X86::ADC64rm, 0 },
578 { X86::ADD16rr, X86::ADD16rm, 0 },
579 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
580 { X86::ADD32rr, X86::ADD32rm, 0 },
581 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
582 { X86::ADD64rr, X86::ADD64rm, 0 },
583 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
584 { X86::ADD8rr, X86::ADD8rm, 0 },
585 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
586 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
587 { X86::ADDSDrr, X86::ADDSDrm, 0 },
588 { X86::ADDSSrr, X86::ADDSSrm, 0 },
589 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
590 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
591 { X86::AND16rr, X86::AND16rm, 0 },
592 { X86::AND32rr, X86::AND32rm, 0 },
593 { X86::AND64rr, X86::AND64rm, 0 },
594 { X86::AND8rr, X86::AND8rm, 0 },
595 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
596 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
597 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
598 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]599 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
600 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
601 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
602 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]603 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
604 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
605 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
606 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
607 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
608 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
609 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
610 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
611 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
612 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
613 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
614 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
615 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
616 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
617 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
618 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
619 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
620 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
621 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
622 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
623 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
624 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
625 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
626 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
627 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
628 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
629 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
630 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
631 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
632 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
633 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
634 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
635 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
636 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
637 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
638 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
639 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
640 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
641 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
642 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
643 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
644 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
645 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
646 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
647 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
648 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
649 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
650 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
651 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
652 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
653 { X86::CMPSDrr, X86::CMPSDrm, 0 },
654 { X86::CMPSSrr, X86::CMPSSrm, 0 },
655 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
656 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
657 { X86::DIVSDrr, X86::DIVSDrm, 0 },
658 { X86::DIVSSrr, X86::DIVSSrm, 0 },
659 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
660 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
661 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
662 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
663 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
664 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
665 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
666 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
667 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
668 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
669 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
670 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
671 { X86::IMUL16rr, X86::IMUL16rm, 0 },
672 { X86::IMUL32rr, X86::IMUL32rm, 0 },
673 { X86::IMUL64rr, X86::IMUL64rm, 0 },
674 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
675 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
676 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
677 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
678 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
679 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
680 { X86::MAXSDrr, X86::MAXSDrm, 0 },
681 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
682 { X86::MAXSSrr, X86::MAXSSrm, 0 },
683 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
684 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
685 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
686 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
687 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
688 { X86::MINSDrr, X86::MINSDrm, 0 },
689 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
690 { X86::MINSSrr, X86::MINSSrm, 0 },
691 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]692 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]693 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
694 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
695 { X86::MULSDrr, X86::MULSDrm, 0 },
696 { X86::MULSSrr, X86::MULSSrm, 0 },
697 { X86::OR16rr, X86::OR16rm, 0 },
698 { X86::OR32rr, X86::OR32rm, 0 },
699 { X86::OR64rr, X86::OR64rm, 0 },
700 { X86::OR8rr, X86::OR8rm, 0 },
701 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
702 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
703 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
704 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]705 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]706 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
707 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
708 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
709 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
710 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
711 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]712 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
713 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]714 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]715 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]716 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
717 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
718 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
719 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]720 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]721 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
722 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]723 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]724 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
725 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
726 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]727 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]728 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]729 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
730 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]731 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]732 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]733 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]734 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]735 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]736 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]737 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
738 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
739 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
740 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
741 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
742 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]743 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]744 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
745 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
746 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
747 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
748 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
749 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
750 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]751 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
752 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
753 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
754 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]755 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
756 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
757 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
758 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
759 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
760 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
761 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
762 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
763 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
764 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
765 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
766 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
767 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
768 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
769 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
770 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
771 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
772 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
773 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
774 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
775 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
776 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
777 { X86::SBB32rr, X86::SBB32rm, 0 },
778 { X86::SBB64rr, X86::SBB64rm, 0 },
779 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
780 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
781 { X86::SUB16rr, X86::SUB16rm, 0 },
782 { X86::SUB32rr, X86::SUB32rm, 0 },
783 { X86::SUB64rr, X86::SUB64rm, 0 },
784 { X86::SUB8rr, X86::SUB8rm, 0 },
785 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
786 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
787 { X86::SUBSDrr, X86::SUBSDrm, 0 },
788 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]789 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]790 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
791 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
792 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
793 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
794 { X86::XOR16rr, X86::XOR16rm, 0 },
795 { X86::XOR32rr, X86::XOR32rm, 0 },
796 { X86::XOR64rr, X86::XOR64rm, 0 },
797 { X86::XOR8rr, X86::XOR8rm, 0 },
798 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]799 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
800 // AVX 128-bit versions of foldable instructions
801 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
802 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
803 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
804 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
805 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
806 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
807 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
808 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
809 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
810 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
811 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
812 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
813 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
814 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
815 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
816 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
817 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
818 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
819 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
820 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
821 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
822 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
823 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
824 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
825 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
826 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
827 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
828 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
829 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
830 { X86::VADDSDrr, X86::VADDSDrm, 0 },
831 { X86::VADDSSrr, X86::VADDSSrm, 0 },
832 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
833 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
834 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
835 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
836 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
837 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]838 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 },
839 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 },
840 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 },
841 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]842 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
843 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
844 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
845 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
846 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
847 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
848 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
849 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
850 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
851 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
852 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
853 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
854 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
855 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
856 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
857 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
858 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
859 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
860 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
861 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
862 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
863 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
864 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
865 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
866 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
867 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
868 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
869 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
870 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
871 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
872 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
873 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
874 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
875 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
876 { X86::VMINSDrr, X86::VMINSDrm, 0 },
877 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
878 { X86::VMINSSrr, X86::VMINSSrm, 0 },
879 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]880 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]881 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
882 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
883 { X86::VMULSDrr, X86::VMULSDrm, 0 },
884 { X86::VMULSSrr, X86::VMULSSrm, 0 },
885 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
886 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
887 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
888 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]889 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]890 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
891 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
892 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
893 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
894 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
895 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]896 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
897 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]898 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]899 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]900 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
901 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]902 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
903 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]904 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]905 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
906 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]907 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]908 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
909 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
910 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]911 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]912 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]913 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]914 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]915 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 },
916 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]917 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]918 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]919 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 },
920 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]921 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]922 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]923 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
924 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
925 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
926 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
927 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
928 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]929 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]930 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
931 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
932 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
933 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
934 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
935 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
936 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]937 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 },
938 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 },
939 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 },
940 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]941 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
942 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
943 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
944 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
945 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
946 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
947 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
948 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
949 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
950 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
951 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
952 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
953 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
954 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
955 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
956 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
957 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
958 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
959 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
960 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
961 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
962 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
963 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
964 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
965 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
966 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
967 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
968 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
969 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
970 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
971 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
972 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
973 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]974 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]975 // AVX 256-bit foldable instructions
976 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 },
977 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 },
978 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 },
979 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 },
980 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 },
981 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 },
982 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 },
983 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 },
984 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 },
985 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 },
986 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 },
987 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 },
988 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 },
989 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 },
990 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 },
991 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 },
992 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 },
993 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 },
994 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 },
995 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 },
996 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 },
997 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 },
998 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 },
999 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 },
1000 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 },
1001 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 },
1002 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 },
1003 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 },
1004 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 },
1005 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 },
1006 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 },
1007 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 },
1008 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 },
1009 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 },
1010 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 },
1011 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 },
1012 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 },
1013 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 },
1014 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 },
1015 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 },
1016 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 },
1017 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 },
1018 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 },
1019 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 },
1020 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 },
1021 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1022 // AVX2 foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1023 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 },
1024 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 },
1025 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 },
1026 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 },
1027 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 },
1028 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 },
1029 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 },
1030 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 },
1031 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 },
1032 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 },
1033 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 },
1034 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 },
1035 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 },
1036 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 },
1037 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 },
1038 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 },
1039 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 },
1040 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 },
1041 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 },
1042 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 },
1043 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 },
1044 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 },
1045 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 },
1046 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 },
1047 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 },
1048 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 },
1049 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 },
1050 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 },
1051 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 },
1052 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]1053 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 },
Elena Demikhovsky779a72b2012-04-15 11:18:59 +0000[diff] [blame]1054 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]1055 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 },
Elena Demikhovsky779a72b2012-04-15 11:18:59 +0000[diff] [blame]1056 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1057 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1058 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1059 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 },
1060 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1061 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1062 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1063 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 },
1064 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 },
1065 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 },
1066 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 },
1067 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 },
1068 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 },
1069 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 },
1070 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 },
1071 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 },
1072 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 },
1073 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 },
1074 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 },
1075 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 },
1076 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
1077 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
1078 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1079 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 },
1080 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 },
1081 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 },
1082 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1083 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
1084 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
1085 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
1086 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1087 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1088 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1089 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1090 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1091 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1092 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1093 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1094 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1095 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1096 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1097 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1098 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1099 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1100 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 },
1101 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 },
1102 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 },
1103 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 },
1104 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 },
1105 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 },
1106 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 },
1107 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1108 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1109 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 },
1110 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 },
1111 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 },
1112 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 },
1113 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 },
1114 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1115 // FIXME: add AVX 256-bit foldable instructions
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1116 };
1117
1118 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]1119 unsigned RegOp = OpTbl2[i].RegOp;
1120 unsigned MemOp = OpTbl2[i].MemOp;
1121 unsigned Flags = OpTbl2[i].Flags;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1122 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1123 RegOp, MemOp,
1124 // Index 2, folded load
1125 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1126 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1127
1128 static const X86OpTblEntry OpTbl3[] = {
1129 // FMA foldable instructions
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1130 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 },
1131 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 },
1132 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 },
1133 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 },
1134 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 },
1135 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 },
1136 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, 0 },
1137 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1138
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1139 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 },
1140 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 },
1141 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 },
1142 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 },
1143 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 },
1144 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 },
1145 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 },
1146 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 },
1147 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 },
1148 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
1149 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
1150 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
1151 { X86::VFMADDPSr132r_Int, X86::VFMADDPSr132m_Int, TB_ALIGN_16 },
1152 { X86::VFMADDPDr132r_Int, X86::VFMADDPDr132m_Int, TB_ALIGN_16 },
1153 { X86::VFMADDPSr132rY_Int, X86::VFMADDPSr132mY_Int, TB_ALIGN_32 },
1154 { X86::VFMADDPDr132rY_Int, X86::VFMADDPDr132mY_Int, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1155
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1156 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
1157 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
1158 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 },
1159 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 },
1160 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 },
1161 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 },
1162 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, 0 },
1163 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1164
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1165 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 },
1166 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 },
1167 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 },
1168 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 },
1169 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 },
1170 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 },
1171 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 },
1172 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 },
1173 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 },
1174 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
1175 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
1176 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
1177 { X86::VFNMADDPSr132r_Int, X86::VFNMADDPSr132m_Int, TB_ALIGN_16 },
1178 { X86::VFNMADDPDr132r_Int, X86::VFNMADDPDr132m_Int, TB_ALIGN_16 },
1179 { X86::VFNMADDPSr132rY_Int, X86::VFNMADDPSr132mY_Int, TB_ALIGN_32 },
1180 { X86::VFNMADDPDr132rY_Int, X86::VFNMADDPDr132mY_Int, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1181
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1182 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
1183 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
1184 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 },
1185 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 },
1186 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 },
1187 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 },
1188 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, 0 },
1189 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, 0 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1190
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1191 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 },
1192 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 },
1193 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 },
1194 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 },
1195 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 },
1196 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 },
1197 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 },
1198 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 },
1199 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 },
1200 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
1201 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
1202 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
1203 { X86::VFMSUBPSr132r_Int, X86::VFMSUBPSr132m_Int, TB_ALIGN_16 },
1204 { X86::VFMSUBPDr132r_Int, X86::VFMSUBPDr132m_Int, TB_ALIGN_16 },
1205 { X86::VFMSUBPSr132rY_Int, X86::VFMSUBPSr132mY_Int, TB_ALIGN_32 },
1206 { X86::VFMSUBPDr132rY_Int, X86::VFMSUBPDr132mY_Int, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1207
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1208 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 },
1209 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 },
1210 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 },
1211 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 },
1212 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 },
1213 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 },
1214 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, 0 },
1215 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, 0 },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1216
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1217 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 },
1218 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 },
1219 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 },
1220 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 },
1221 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 },
1222 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 },
1223 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 },
1224 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 },
1225 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 },
1226 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 },
1227 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 },
1228 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 },
1229 { X86::VFNMSUBPSr132r_Int, X86::VFNMSUBPSr132m_Int, TB_ALIGN_16 },
1230 { X86::VFNMSUBPDr132r_Int, X86::VFNMSUBPDr132m_Int, TB_ALIGN_16 },
1231 { X86::VFNMSUBPSr132rY_Int, X86::VFNMSUBPSr132mY_Int, TB_ALIGN_32 },
1232 { X86::VFNMSUBPDr132rY_Int, X86::VFNMSUBPDr132mY_Int, TB_ALIGN_32 },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1233
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1234 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 },
1235 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 },
1236 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 },
1237 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 },
1238 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 },
1239 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 },
1240 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 },
1241 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 },
1242 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 },
1243 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 },
1244 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 },
1245 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 },
1246 { X86::VFMADDSUBPSr132r_Int, X86::VFMADDSUBPSr132m_Int, TB_ALIGN_16 },
1247 { X86::VFMADDSUBPDr132r_Int, X86::VFMADDSUBPDr132m_Int, TB_ALIGN_16 },
1248 { X86::VFMADDSUBPSr132rY_Int, X86::VFMADDSUBPSr132mY_Int, TB_ALIGN_32 },
1249 { X86::VFMADDSUBPDr132rY_Int, X86::VFMADDSUBPDr132mY_Int, TB_ALIGN_32 },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1250
Craig Topperc6ac4ce2012-06-04 07:46:16 +0000[diff] [blame^]1251 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 },
1252 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 },
1253 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 },
1254 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 },
1255 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 },
1256 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 },
1257 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 },
1258 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 },
1259 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 },
1260 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 },
1261 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 },
1262 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 },
1263 { X86::VFMSUBADDPSr132r_Int, X86::VFMSUBADDPSr132m_Int, TB_ALIGN_16 },
1264 { X86::VFMSUBADDPDr132r_Int, X86::VFMSUBADDPDr132m_Int, TB_ALIGN_16 },
1265 { X86::VFMSUBADDPSr132rY_Int, X86::VFMSUBADDPSr132mY_Int, TB_ALIGN_32 },
1266 { X86::VFMSUBADDPDr132rY_Int, X86::VFMSUBADDPDr132mY_Int, TB_ALIGN_32 },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1267 };
1268
1269 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1270 unsigned RegOp = OpTbl3[i].RegOp;
1271 unsigned MemOp = OpTbl3[i].MemOp;
1272 unsigned Flags = OpTbl3[i].Flags;
1273 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1274 RegOp, MemOp,
1275 // Index 3, folded load
1276 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1277 }
1278
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1279}
1280
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1281void
1282X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1283 MemOp2RegOpTableType &M2RTable,
1284 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1285 if ((Flags & TB_NO_FORWARD) == 0) {
1286 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1287 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1288 }
1289 if ((Flags & TB_NO_REVERSE) == 0) {
1290 assert(!M2RTable.count(MemOp) &&
1291 "Duplicated entries in unfolding maps?");
1292 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1293 }
1294}
1295
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1296bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1297X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1298 unsigned &SrcReg, unsigned &DstReg,
1299 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1300 switch (MI.getOpcode()) {
1301 default: break;
1302 case X86::MOVSX16rr8:
1303 case X86::MOVZX16rr8:
1304 case X86::MOVSX32rr8:
1305 case X86::MOVZX32rr8:
1306 case X86::MOVSX64rr8:
1307 case X86::MOVZX64rr8:
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]1308 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1309 // It's not always legal to reference the low 8-bit of the larger
1310 // register in 32-bit mode.
1311 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1312 case X86::MOVSX32rr16:
1313 case X86::MOVZX32rr16:
1314 case X86::MOVSX64rr16:
1315 case X86::MOVZX64rr16:
1316 case X86::MOVSX64rr32:
1317 case X86::MOVZX64rr32: {
1318 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1319 // Be conservative.
1320 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1321 SrcReg = MI.getOperand(1).getReg();
1322 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1323 switch (MI.getOpcode()) {
1324 default:
1325 llvm_unreachable(0);
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1326 case X86::MOVSX16rr8:
1327 case X86::MOVZX16rr8:
1328 case X86::MOVSX32rr8:
1329 case X86::MOVZX32rr8:
1330 case X86::MOVSX64rr8:
1331 case X86::MOVZX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1332 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1333 break;
1334 case X86::MOVSX32rr16:
1335 case X86::MOVZX32rr16:
1336 case X86::MOVSX64rr16:
1337 case X86::MOVZX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1338 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1339 break;
1340 case X86::MOVSX64rr32:
1341 case X86::MOVZX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]1342 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1343 break;
1344 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1345 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1346 }
1347 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]1348 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]1349}
1350
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1351/// isFrameOperand - Return true and the FrameIndex if the specified
1352/// operand and follow operands form a reference to the stack frame.
1353bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1354 int &FrameIndex) const {
1355 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1356 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1357 MI->getOperand(Op+1).getImm() == 1 &&
1358 MI->getOperand(Op+2).getReg() == 0 &&
1359 MI->getOperand(Op+3).getImm() == 0) {
1360 FrameIndex = MI->getOperand(Op).getIndex();
1361 return true;
1362 }
1363 return false;
1364}
1365
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1366static bool isFrameLoadOpcode(int Opcode) {
1367 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]1368 default:
1369 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1370 case X86::MOV8rm:
1371 case X86::MOV16rm:
1372 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]1373 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]1374 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1375 case X86::MOVSSrm:
1376 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]1377 case X86::MOVAPSrm:
1378 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1379 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1380 case X86::VMOVSSrm:
1381 case X86::VMOVSDrm:
1382 case X86::VMOVAPSrm:
1383 case X86::VMOVAPDrm:
1384 case X86::VMOVDQArm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1385 case X86::VMOVAPSYrm:
1386 case X86::VMOVAPDYrm:
1387 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]1388 case X86::MMX_MOVD64rm:
1389 case X86::MMX_MOVQ64rm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1390 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1391 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1392}
1393
1394static bool isFrameStoreOpcode(int Opcode) {
1395 switch (Opcode) {
1396 default: break;
1397 case X86::MOV8mr:
1398 case X86::MOV16mr:
1399 case X86::MOV32mr:
1400 case X86::MOV64mr:
1401 case X86::ST_FpP64m:
1402 case X86::MOVSSmr:
1403 case X86::MOVSDmr:
1404 case X86::MOVAPSmr:
1405 case X86::MOVAPDmr:
1406 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1407 case X86::VMOVSSmr:
1408 case X86::VMOVSDmr:
1409 case X86::VMOVAPSmr:
1410 case X86::VMOVAPDmr:
1411 case X86::VMOVDQAmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1412 case X86::VMOVAPSYmr:
1413 case X86::VMOVAPDYmr:
1414 case X86::VMOVDQAYmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1415 case X86::MMX_MOVD64mr:
1416 case X86::MMX_MOVQ64mr:
1417 case X86::MMX_MOVNTQmr:
1418 return true;
1419 }
1420 return false;
1421}
1422
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1423unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1424 int &FrameIndex) const {
1425 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1426 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1427 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1428 return 0;
1429}
1430
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1431unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1432 int &FrameIndex) const {
1433 if (isFrameLoadOpcode(MI->getOpcode())) {
1434 unsigned Reg;
1435 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1436 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1437 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1438 const MachineMemOperand *Dummy;
1439 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1440 }
1441 return 0;
1442}
1443
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]1444unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1445 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1446 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]1447 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1448 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]1449 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]1450 return 0;
1451}
1452
1453unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1454 int &FrameIndex) const {
1455 if (isFrameStoreOpcode(MI->getOpcode())) {
1456 unsigned Reg;
1457 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1458 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]1459 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]1460 const MachineMemOperand *Dummy;
1461 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]1462 }
1463 return 0;
1464}
1465
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1466/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1467/// X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1468static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1469 bool isPICBase = false;
1470 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1471 E = MRI.def_end(); I != E; ++I) {
1472 MachineInstr *DefMI = I.getOperand().getParent();
1473 if (DefMI->getOpcode() != X86::MOVPC32r)
1474 return false;
1475 assert(!isPICBase && "More than one PIC base?");
1476 isPICBase = true;
1477 }
1478 return isPICBase;
1479}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]1480
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]1481bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1482X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1483 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1484 switch (MI->getOpcode()) {
1485 default: break;
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1486 case X86::MOV8rm:
1487 case X86::MOV16rm:
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1488 case X86::MOV32rm:
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1489 case X86::MOV64rm:
1490 case X86::LD_Fp64m:
1491 case X86::MOVSSrm:
1492 case X86::MOVSDrm:
1493 case X86::MOVAPSrm:
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]1494 case X86::MOVUPSrm:
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1495 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]1496 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1497 case X86::VMOVSSrm:
1498 case X86::VMOVSDrm:
1499 case X86::VMOVAPSrm:
1500 case X86::VMOVUPSrm:
1501 case X86::VMOVAPDrm:
1502 case X86::VMOVDQArm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]1503 case X86::VMOVAPSYrm:
1504 case X86::VMOVUPSYrm:
1505 case X86::VMOVAPDYrm:
1506 case X86::VMOVDQAYrm:
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1507 case X86::MMX_MOVD64rm:
Evan Cheng5392cc92009-11-17 09:51:18 +0000[diff] [blame]1508 case X86::MMX_MOVQ64rm:
Bruno Cardoso Lopesaad5e502011-09-03 00:46:45 +0000[diff] [blame]1509 case X86::FsVMOVAPSrm:
1510 case X86::FsVMOVAPDrm:
Evan Cheng5392cc92009-11-17 09:51:18 +0000[diff] [blame]1511 case X86::FsMOVAPSrm:
1512 case X86::FsMOVAPDrm: {
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1513 // Loads from constant pools are trivially rematerializable.
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1514 if (MI->getOperand(1).isReg() &&
1515 MI->getOperand(2).isImm() &&
1516 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]1517 MI->isInvariantLoad(AA)) {
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1518 unsigned BaseReg = MI->getOperand(1).getReg();
Chris Lattnerfea81da2009-06-27 04:16:01 +0000[diff] [blame]1519 if (BaseReg == 0 || BaseReg == X86::RIP)
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1520 return true;
1521 // Allow re-materialization of PIC load.
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1522 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
Evan Chengb86595f2008-04-01 23:26:12 +0000[diff] [blame]1523 return false;
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1524 const MachineFunction &MF = *MI->getParent()->getParent();
1525 const MachineRegisterInfo &MRI = MF.getRegInfo();
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1526 bool isPICBase = false;
1527 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1528 E = MRI.def_end(); I != E; ++I) {
1529 MachineInstr *DefMI = I.getOperand().getParent();
1530 if (DefMI->getOpcode() != X86::MOVPC32r)
1531 return false;
1532 assert(!isPICBase && "More than one PIC base?");
1533 isPICBase = true;
1534 }
1535 return isPICBase;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1536 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1537 return false;
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]1538 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1539
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1540 case X86::LEA32r:
1541 case X86::LEA64r: {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1542 if (MI->getOperand(2).isImm() &&
1543 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1544 !MI->getOperand(4).isReg()) {
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1545 // lea fi#, lea GV, etc. are all rematerializable.
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1546 if (!MI->getOperand(1).isReg())
Dan Gohman7e922aa2008-09-26 21:30:20 +0000[diff] [blame]1547 return true;
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1548 unsigned BaseReg = MI->getOperand(1).getReg();
1549 if (BaseReg == 0)
1550 return true;
1551 // Allow re-materialization of lea PICBase + x.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1552 const MachineFunction &MF = *MI->getParent()->getParent();
1553 const MachineRegisterInfo &MRI = MF.getRegInfo();
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]1554 return regIsPICBase(BaseReg, MRI);
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1555 }
1556 return false;
1557 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1558 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]1559
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]1560 // All other instructions marked M_REMATERIALIZABLE are always trivially
1561 // rematerializable.
1562 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]1563}
1564
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1565/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1566/// would clobber the EFLAGS condition register. Note the result may be
1567/// conservative. If it cannot definitely determine the safety after visiting
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1568/// a few instructions in each direction it assumes it's not safe.
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1569static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1570 MachineBasicBlock::iterator I) {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1571 MachineBasicBlock::iterator E = MBB.end();
1572
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1573 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1574 // safety after visiting 4 instructions in each direction, we will assume
1575 // it's not safe.
1576 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1577 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1578 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1579 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1580 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1581 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1582 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1583 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1584 continue;
1585 if (MO.getReg() == X86::EFLAGS) {
1586 if (MO.isUse())
1587 return false;
1588 SeenDef = true;
1589 }
1590 }
1591
1592 if (SeenDef)
1593 // This instruction defines EFLAGS, no need to look any further.
1594 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1595 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1596 // Skip over DBG_VALUE.
1597 while (Iter != E && Iter->isDebugValue())
1598 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1599 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1600
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]1601 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1602 // live in.
1603 if (Iter == E) {
1604 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1605 SE = MBB.succ_end(); SI != SE; ++SI)
1606 if ((*SI)->isLiveIn(X86::EFLAGS))
1607 return false;
1608 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1609 }
1610
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1611 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1612 Iter = I;
1613 for (unsigned i = 0; i < 4; ++i) {
1614 // If we make it to the beginning of the block, it's safe to clobber
1615 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1616 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1617 return !MBB.isLiveIn(X86::EFLAGS);
1618
1619 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]1620 // Skip over DBG_VALUE.
1621 while (Iter != B && Iter->isDebugValue())
1622 --Iter;
1623
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1624 bool SawKill = false;
1625 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1626 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]1627 // A register mask may clobber EFLAGS, but we should still look for a
1628 // live EFLAGS def.
1629 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1630 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]1631 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1632 if (MO.isDef()) return MO.isDead();
1633 if (MO.isKill()) SawKill = true;
1634 }
1635 }
1636
1637 if (SawKill)
1638 // This instruction kills EFLAGS and doesn't redefine it, so
1639 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]1640 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1641 }
1642
1643 // Conservative answer.
1644 return false;
1645}
1646
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1647void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1648 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1649 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]1650 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1651 const TargetRegisterInfo &TRI) const {
Dan Gohman90c600d2010-05-07 01:28:10 +0000[diff] [blame]1652 DebugLoc DL = Orig->getDebugLoc();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1653
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1654 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1655 // Re-materialize them as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1656 bool Clone = true;
1657 unsigned Opc = Orig->getOpcode();
1658 switch (Opc) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1659 default: break;
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1660 case X86::MOV8r0:
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]1661 case X86::MOV16r0:
1662 case X86::MOV32r0:
1663 case X86::MOV64r0: {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1664 if (!isSafeToClobberEFLAGS(MBB, I)) {
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1665 switch (Opc) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1666 default: break;
1667 case X86::MOV8r0: Opc = X86::MOV8ri; break;
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]1668 case X86::MOV16r0: Opc = X86::MOV16ri; break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1669 case X86::MOV32r0: Opc = X86::MOV32ri; break;
Dan Gohman952f6f92010-02-26 16:49:27 +0000[diff] [blame]1670 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1671 }
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1672 Clone = false;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1673 }
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1674 break;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]1675 }
1676 }
1677
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1678 if (Clone) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1679 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1680 MBB.insert(I, MI);
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1681 } else {
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1682 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1683 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]1684
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]1685 MachineInstr *NewMI = prior(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]1686 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]1687}
1688
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1689/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1690/// is not marked dead.
1691static bool hasLiveCondCodeDef(MachineInstr *MI) {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1692 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1693 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]1694 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]1695 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1696 return true;
1697 }
1698 }
1699 return false;
1700}
1701
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1702/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1703/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1704/// to a 32-bit superregister and then truncating back down to a 16-bit
1705/// subregister.
1706MachineInstr *
1707X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1708 MachineFunction::iterator &MFI,
1709 MachineBasicBlock::iterator &MBBI,
1710 LiveVariables *LV) const {
1711 MachineInstr *MI = MBBI;
1712 unsigned Dest = MI->getOperand(0).getReg();
1713 unsigned Src = MI->getOperand(1).getReg();
1714 bool isDead = MI->getOperand(0).isDead();
1715 bool isKill = MI->getOperand(1).isKill();
1716
1717 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1718 ? X86::LEA64_32r : X86::LEA32r;
1719 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1720 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1721 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1722
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1723 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1724 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1725 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]1726 // movw (%rbp,%rcx,2), %dx
1727 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1728 // But testing has shown this *does* help performance in 64-bit mode (at
1729 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1730 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1731 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]1732 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1733 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1734 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1735
1736 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1737 get(Opc), leaOutReg);
1738 switch (MIOpc) {
1739 default:
1740 llvm_unreachable(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1741 case X86::SHL16ri: {
1742 unsigned ShAmt = MI->getOperand(2).getImm();
1743 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1744 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1745 break;
1746 }
1747 case X86::INC16r:
1748 case X86::INC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1749 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1750 break;
1751 case X86::DEC16r:
1752 case X86::DEC64_16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1753 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1754 break;
1755 case X86::ADD16ri:
1756 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]1757 case X86::ADD16ri_DB:
1758 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1759 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1760 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]1761 case X86::ADD16rr:
1762 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1763 unsigned Src2 = MI->getOperand(2).getReg();
1764 bool isKill2 = MI->getOperand(2).isKill();
1765 unsigned leaInReg2 = 0;
1766 MachineInstr *InsMI2 = 0;
1767 if (Src == Src2) {
1768 // ADD16rr %reg1028<kill>, %reg1028
1769 // just a single insert_subreg.
1770 addRegReg(MIB, leaInReg, true, leaInReg, false);
1771 } else {
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1772 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1773 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1774 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]1775 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1776 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]1777 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]1778 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1779 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1780 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1781 }
1782 if (LV && isKill2 && InsMI2)
1783 LV->replaceKillInstruction(Src2, MI, InsMI2);
1784 break;
1785 }
1786 }
1787
1788 MachineInstr *NewMI = MIB;
1789 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]1790 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1791 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]1792 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1793
1794 if (LV) {
1795 // Update live variables
1796 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1797 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1798 if (isKill)
1799 LV->replaceKillInstruction(Src, MI, InsMI);
1800 if (isDead)
1801 LV->replaceKillInstruction(Dest, MI, ExtMI);
1802 }
1803
1804 return ExtMI;
1805}
1806
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1807/// convertToThreeAddress - This method must be implemented by targets that
1808/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1809/// may be able to convert a two-address instruction into a true
1810/// three-address instruction on demand. This allows the X86 target (for
1811/// example) to convert ADD and SHL instructions into LEA instructions if they
1812/// would require register copies due to two-addressness.
1813///
1814/// This method returns a null pointer if the transformation cannot be
1815/// performed, otherwise it returns the new instruction.
1816///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1817MachineInstr *
1818X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1819 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]1820 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1821 MachineInstr *MI = MBBI;
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]1822 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1823 // All instructions input are two-addr instructions. Get the known operands.
1824 unsigned Dest = MI->getOperand(0).getReg();
1825 unsigned Src = MI->getOperand(1).getReg();
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1826 bool isDead = MI->getOperand(0).isDead();
1827 bool isKill = MI->getOperand(1).isKill();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1828
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]1829 MachineInstr *NewMI = NULL;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1830 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1831 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1832 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1833 bool DisableLEA16 = true;
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1834 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]1835
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1836 unsigned MIOpc = MI->getOpcode();
1837 switch (MIOpc) {
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1838 case X86::SHUFPSrri: {
1839 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1840 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]1841
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]1842 unsigned B = MI->getOperand(1).getReg();
1843 unsigned C = MI->getOperand(2).getReg();
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1844 if (B != C) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1845 unsigned A = MI->getOperand(0).getReg();
1846 unsigned M = MI->getOperand(3).getImm();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1847 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1848 .addReg(A, RegState::Define | getDeadRegState(isDead))
1849 .addReg(B, getKillRegState(isKill)).addImm(M);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1850 break;
1851 }
Craig Toppere52d86a2012-01-13 09:21:41 +0000[diff] [blame]1852 case X86::SHUFPDrri: {
1853 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1854 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1855
1856 unsigned B = MI->getOperand(1).getReg();
1857 unsigned C = MI->getOperand(2).getReg();
1858 if (B != C) return 0;
1859 unsigned A = MI->getOperand(0).getReg();
1860 unsigned M = MI->getOperand(3).getImm();
1861
1862 // Convert to PSHUFD mask.
1863 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1864
1865 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1866 .addReg(A, RegState::Define | getDeadRegState(isDead))
1867 .addReg(B, getKillRegState(isKill)).addImm(M);
1868 break;
1869 }
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1870 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1871 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1872 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1873 // the flags produced by a shift yet, so this is safe.
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1874 unsigned ShAmt = MI->getOperand(2).getImm();
1875 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1876
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1877 // LEA can't handle RSP.
1878 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1879 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1880 return 0;
1881
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1882 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1883 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1884 .addReg(0).addImm(1 << ShAmt)
1885 .addReg(Src, getKillRegState(isKill))
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1886 .addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]1887 break;
1888 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1889 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1890 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1891 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1892 // the flags produced by a shift yet, so this is safe.
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1893 unsigned ShAmt = MI->getOperand(2).getImm();
1894 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1895
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1896 // LEA can't handle ESP.
1897 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1898 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1899 return 0;
1900
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1901 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1902 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1903 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1904 .addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1905 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1906 break;
1907 }
1908 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]1909 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
Evan Cheng189df732007-09-06 00:14:41 +0000[diff] [blame]1910 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1911 // the flags produced by a shift yet, so this is safe.
Evan Cheng189df732007-09-06 00:14:41 +0000[diff] [blame]1912 unsigned ShAmt = MI->getOperand(2).getImm();
1913 if (ShAmt == 0 || ShAmt >= 4) return 0;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1914
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1915 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1916 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1917 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1918 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1919 .addReg(0).addImm(1 << ShAmt)
1920 .addReg(Src, getKillRegState(isKill))
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1921 .addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]1922 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1923 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1924 default: {
1925 // The following opcodes also sets the condition code register(s). Only
1926 // convert them to equivalent lea if the condition code register def's
1927 // are dead!
1928 if (hasLiveCondCodeDef(MI))
1929 return 0;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]1930
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1931 switch (MIOpc) {
1932 default: return 0;
1933 case X86::INC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]1934 case X86::INC32r:
1935 case X86::INC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1936 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]1937 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1938 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]1939 const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
1940 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1941 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1942
1943 // LEA can't handle RSP.
1944 if (TargetRegisterInfo::isVirtualRegister(Src) &&
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]1945 !MF.getRegInfo().constrainRegClass(Src, RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1946 return 0;
1947
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1948 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1949 .addReg(Dest, RegState::Define |
1950 getDeadRegState(isDead)),
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]1951 Src, isKill, 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1952 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]1953 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1954 case X86::INC16r:
1955 case X86::INC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1956 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1957 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1958 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1959 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1960 .addReg(Dest, RegState::Define |
1961 getDeadRegState(isDead)),
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1962 Src, isKill, 1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1963 break;
1964 case X86::DEC64r:
Dan Gohmanbeac19e2009-01-06 23:34:46 +0000[diff] [blame]1965 case X86::DEC32r:
1966 case X86::DEC64_32r: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1967 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Evan Cheng82bc90a2007-10-09 07:14:53 +0000[diff] [blame]1968 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1969 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]1970 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
1971 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1972 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1973 // LEA can't handle RSP.
1974 if (TargetRegisterInfo::isVirtualRegister(Src) &&
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]1975 !MF.getRegInfo().constrainRegClass(Src, RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]1976 return 0;
1977
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]1978 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1979 .addReg(Dest, RegState::Define |
1980 getDeadRegState(isDead)),
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]1981 Src, isKill, -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1982 break;
1983 }
1984 case X86::DEC16r:
1985 case X86::DEC64_16r:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]1986 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]1987 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1988 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]1989 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]1990 .addReg(Dest, RegState::Define |
1991 getDeadRegState(isDead)),
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]1992 Src, isKill, -1);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1993 break;
1994 case X86::ADD64rr:
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]1995 case X86::ADD64rr_DB:
1996 case X86::ADD32rr:
1997 case X86::ADD32rr_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]1998 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]1999 unsigned Opc;
Craig Topper760b1342012-02-22 05:59:10 +0000[diff] [blame]2000 const TargetRegisterClass *RC;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2001 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
2002 Opc = X86::LEA64r;
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]2003 RC = &X86::GR64_NOSPRegClass;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2004 } else {
2005 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]2006 RC = &X86::GR32_NOSPRegClass;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2007 }
2008
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2009
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2010 unsigned Src2 = MI->getOperand(2).getReg();
2011 bool isKill2 = MI->getOperand(2).isKill();
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2012
2013 // LEA can't handle RSP.
2014 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2015 !MF.getRegInfo().constrainRegClass(Src2, RC))
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2016 return 0;
2017
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2018 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2019 .addReg(Dest, RegState::Define |
2020 getDeadRegState(isDead)),
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2021 Src, isKill, Src2, isKill2);
2022 if (LV && isKill2)
2023 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2024 break;
2025 }
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2026 case X86::ADD16rr:
2027 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2028 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2029 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2030 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2031 unsigned Src2 = MI->getOperand(2).getReg();
2032 bool isKill2 = MI->getOperand(2).isKill();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2033 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2034 .addReg(Dest, RegState::Define |
2035 getDeadRegState(isDead)),
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2036 Src, isKill, Src2, isKill2);
2037 if (LV && isKill2)
2038 LV->replaceKillInstruction(Src2, MI, NewMI);
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2039 break;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2040 }
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2041 case X86::ADD64ri32:
2042 case X86::ADD64ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2043 case X86::ADD64ri32_DB:
2044 case X86::ADD64ri8_DB:
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2045 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2046 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2047 .addReg(Dest, RegState::Define |
2048 getDeadRegState(isDead)),
2049 Src, isKill, MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2050 break;
2051 case X86::ADD32ri:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2052 case X86::ADD32ri8:
2053 case X86::ADD32ri_DB:
2054 case X86::ADD32ri8_DB: {
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2055 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2056 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2057 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2058 .addReg(Dest, RegState::Define |
2059 getDeadRegState(isDead)),
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]2060 Src, isKill, MI->getOperand(2).getImm());
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2061 break;
2062 }
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2063 case X86::ADD16ri:
2064 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2065 case X86::ADD16ri_DB:
2066 case X86::ADD16ri8_DB:
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2067 if (DisableLEA16)
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2068 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2069 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2070 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2071 .addReg(Dest, RegState::Define |
2072 getDeadRegState(isDead)),
2073 Src, isKill, MI->getOperand(2).getImm());
2074 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2075 }
2076 }
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2077 }
2078
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2079 if (!NewMI) return 0;
2080
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2081 if (LV) { // Update live variables
2082 if (isKill)
2083 LV->replaceKillInstruction(Src, MI, NewMI);
2084 if (isDead)
2085 LV->replaceKillInstruction(Dest, MI, NewMI);
2086 }
2087
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2088 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2089 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2090}
2091
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2092/// commuteInstruction - We have a few instructions that must be hacked on to
2093/// commute them.
2094///
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2095MachineInstr *
2096X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2097 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2098 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2099 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2100 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2101 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2102 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2103 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2104 unsigned Opc;
2105 unsigned Size;
2106 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2107 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2108 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2109 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2110 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2111 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2112 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2113 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2114 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2115 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2116 if (NewMI) {
2117 MachineFunction &MF = *MI->getParent()->getParent();
2118 MI = MF.CloneMachineInstr(MI);
2119 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2120 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2121 MI->setDesc(get(Opc));
2122 MI->getOperand(3).setImm(Size-Amt);
2123 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2124 }
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2125 case X86::CMOVB16rr:
2126 case X86::CMOVB32rr:
2127 case X86::CMOVB64rr:
2128 case X86::CMOVAE16rr:
2129 case X86::CMOVAE32rr:
2130 case X86::CMOVAE64rr:
2131 case X86::CMOVE16rr:
2132 case X86::CMOVE32rr:
2133 case X86::CMOVE64rr:
2134 case X86::CMOVNE16rr:
2135 case X86::CMOVNE32rr:
2136 case X86::CMOVNE64rr:
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2137 case X86::CMOVBE16rr:
2138 case X86::CMOVBE32rr:
2139 case X86::CMOVBE64rr:
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2140 case X86::CMOVA16rr:
2141 case X86::CMOVA32rr:
2142 case X86::CMOVA64rr:
2143 case X86::CMOVL16rr:
2144 case X86::CMOVL32rr:
2145 case X86::CMOVL64rr:
2146 case X86::CMOVGE16rr:
2147 case X86::CMOVGE32rr:
2148 case X86::CMOVGE64rr:
2149 case X86::CMOVLE16rr:
2150 case X86::CMOVLE32rr:
2151 case X86::CMOVLE64rr:
2152 case X86::CMOVG16rr:
2153 case X86::CMOVG32rr:
2154 case X86::CMOVG64rr:
2155 case X86::CMOVS16rr:
2156 case X86::CMOVS32rr:
2157 case X86::CMOVS64rr:
2158 case X86::CMOVNS16rr:
2159 case X86::CMOVNS32rr:
2160 case X86::CMOVNS64rr:
2161 case X86::CMOVP16rr:
2162 case X86::CMOVP32rr:
2163 case X86::CMOVP64rr:
2164 case X86::CMOVNP16rr:
2165 case X86::CMOVNP32rr:
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2166 case X86::CMOVNP64rr:
2167 case X86::CMOVO16rr:
2168 case X86::CMOVO32rr:
2169 case X86::CMOVO64rr:
2170 case X86::CMOVNO16rr:
2171 case X86::CMOVNO32rr:
2172 case X86::CMOVNO64rr: {
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2173 unsigned Opc = 0;
2174 switch (MI->getOpcode()) {
2175 default: break;
2176 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2177 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2178 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2179 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2180 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2181 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2182 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2183 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2184 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2185 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2186 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2187 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]2188 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2189 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2190 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2191 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2192 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2193 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2194 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2195 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2196 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2197 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2198 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2199 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2200 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2201 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2202 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2203 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2204 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2205 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2206 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2207 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2208 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2209 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2210 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2211 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2212 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2213 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2214 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2215 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2216 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2217 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2218 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2219 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]2220 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]2221 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2222 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2223 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2224 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2225 if (NewMI) {
2226 MachineFunction &MF = *MI->getParent()->getParent();
2227 MI = MF.CloneMachineInstr(MI);
2228 NewMI = false;
2229 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]2230 MI->setDesc(get(Opc));
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]2231 // Fallthrough intended.
2232 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2233 default:
Evan Cheng03553bb2008-06-16 07:33:11 +0000[diff] [blame]2234 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2235 }
2236}
2237
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2238static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2239 switch (BrOpc) {
2240 default: return X86::COND_INVALID;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2241 case X86::JE_4: return X86::COND_E;
2242 case X86::JNE_4: return X86::COND_NE;
2243 case X86::JL_4: return X86::COND_L;
2244 case X86::JLE_4: return X86::COND_LE;
2245 case X86::JG_4: return X86::COND_G;
2246 case X86::JGE_4: return X86::COND_GE;
2247 case X86::JB_4: return X86::COND_B;
2248 case X86::JBE_4: return X86::COND_BE;
2249 case X86::JA_4: return X86::COND_A;
2250 case X86::JAE_4: return X86::COND_AE;
2251 case X86::JS_4: return X86::COND_S;
2252 case X86::JNS_4: return X86::COND_NS;
2253 case X86::JP_4: return X86::COND_P;
2254 case X86::JNP_4: return X86::COND_NP;
2255 case X86::JO_4: return X86::COND_O;
2256 case X86::JNO_4: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2257 }
2258}
2259
2260unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2261 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2262 default: llvm_unreachable("Illegal condition code!");
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2263 case X86::COND_E: return X86::JE_4;
2264 case X86::COND_NE: return X86::JNE_4;
2265 case X86::COND_L: return X86::JL_4;
2266 case X86::COND_LE: return X86::JLE_4;
2267 case X86::COND_G: return X86::JG_4;
2268 case X86::COND_GE: return X86::JGE_4;
2269 case X86::COND_B: return X86::JB_4;
2270 case X86::COND_BE: return X86::JBE_4;
2271 case X86::COND_A: return X86::JA_4;
2272 case X86::COND_AE: return X86::JAE_4;
2273 case X86::COND_S: return X86::JS_4;
2274 case X86::COND_NS: return X86::JNS_4;
2275 case X86::COND_P: return X86::JP_4;
2276 case X86::COND_NP: return X86::JNP_4;
2277 case X86::COND_O: return X86::JO_4;
2278 case X86::COND_NO: return X86::JNO_4;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2279 }
2280}
2281
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2282/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2283/// e.g. turning COND_E to COND_NE.
2284X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2285 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2286 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2287 case X86::COND_E: return X86::COND_NE;
2288 case X86::COND_NE: return X86::COND_E;
2289 case X86::COND_L: return X86::COND_GE;
2290 case X86::COND_LE: return X86::COND_G;
2291 case X86::COND_G: return X86::COND_LE;
2292 case X86::COND_GE: return X86::COND_L;
2293 case X86::COND_B: return X86::COND_AE;
2294 case X86::COND_BE: return X86::COND_A;
2295 case X86::COND_A: return X86::COND_BE;
2296 case X86::COND_AE: return X86::COND_B;
2297 case X86::COND_S: return X86::COND_NS;
2298 case X86::COND_NS: return X86::COND_S;
2299 case X86::COND_P: return X86::COND_NP;
2300 case X86::COND_NP: return X86::COND_P;
2301 case X86::COND_O: return X86::COND_NO;
2302 case X86::COND_NO: return X86::COND_O;
2303 }
2304}
2305
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2306bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2307 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2308
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2309 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2310 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2311 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2312 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]2313 return true;
2314 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]2315}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]2316
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2317bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2318 MachineBasicBlock *&TBB,
2319 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2320 SmallVectorImpl<MachineOperand> &Cond,
2321 bool AllowModify) const {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2322 // Start from the bottom of the block and work up, examining the
2323 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2324 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2325 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2326 while (I != MBB.begin()) {
2327 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2328 if (I->isDebugValue())
2329 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2330
2331 // Working from the bottom, when we see a non-terminator instruction, we're
2332 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]2333 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2334 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2335
2336 // A terminator that isn't a branch can't easily be handled by this
2337 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]2338 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2339 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2340
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2341 // Handle unconditional branches.
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2342 if (I->getOpcode() == X86::JMP_4) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2343 UnCondBrIter = I;
2344
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2345 if (!AllowModify) {
2346 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]2347 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]2348 }
2349
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2350 // If the block has any instructions after a JMP, delete them.
Chris Lattnera48f44d2009-12-03 00:50:42 +0000[diff] [blame]2351 while (llvm::next(I) != MBB.end())
2352 llvm::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2353
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2354 Cond.clear();
2355 FBB = 0;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2356
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2357 // Delete the JMP if it's equivalent to a fall-through.
2358 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2359 TBB = 0;
2360 I->eraseFromParent();
2361 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2362 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2363 continue;
2364 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2365
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2366 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2367 TBB = I->getOperand(0).getMBB();
2368 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2369 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2370
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2371 // Handle conditional branches.
2372 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2373 if (BranchCode == X86::COND_INVALID)
2374 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2375
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2376 // Working from the bottom, handle the first conditional branch.
2377 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2378 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2379 if (AllowModify && UnCondBrIter != MBB.end() &&
2380 MBB.isLayoutSuccessor(TargetBB)) {
2381 // If we can modify the code and it ends in something like:
2382 //
2383 // jCC L1
2384 // jmp L2
2385 // L1:
2386 // ...
2387 // L2:
2388 //
2389 // Then we can change this to:
2390 //
2391 // jnCC L2
2392 // L1:
2393 // ...
2394 // L2:
2395 //
2396 // Which is a bit more efficient.
2397 // We conditionally jump to the fall-through block.
2398 BranchCode = GetOppositeBranchCondition(BranchCode);
2399 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2400 MachineBasicBlock::iterator OldInst = I;
2401
2402 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2403 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2404 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2405 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]2406
2407 OldInst->eraseFromParent();
2408 UnCondBrIter->eraseFromParent();
2409
2410 // Restart the analysis.
2411 UnCondBrIter = MBB.end();
2412 I = MBB.end();
2413 continue;
2414 }
2415
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2416 FBB = TBB;
2417 TBB = I->getOperand(0).getMBB();
2418 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2419 continue;
2420 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2421
2422 // Handle subsequent conditional branches. Only handle the case where all
2423 // conditional branches branch to the same destination and their condition
2424 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2425 assert(Cond.size() == 1);
2426 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2427
2428 // Only handle the case where all conditional branches branch to the same
2429 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2430 if (TBB != I->getOperand(0).getMBB())
2431 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2432
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2433 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2434 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2435 if (OldBranchCode == BranchCode)
2436 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2437
2438 // If they differ, see if they fit one of the known patterns. Theoretically,
2439 // we could handle more patterns here, but we shouldn't expect to see them
2440 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2441 if ((OldBranchCode == X86::COND_NP &&
2442 BranchCode == X86::COND_E) ||
2443 (OldBranchCode == X86::COND_E &&
2444 BranchCode == X86::COND_NP))
2445 BranchCode = X86::COND_NP_OR_E;
2446 else if ((OldBranchCode == X86::COND_P &&
2447 BranchCode == X86::COND_NE) ||
2448 (OldBranchCode == X86::COND_NE &&
2449 BranchCode == X86::COND_P))
2450 BranchCode = X86::COND_NE_OR_P;
2451 else
2452 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]2453
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2454 // Update the MachineOperand.
2455 Cond[0].setImm(BranchCode);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]2456 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2457
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2458 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2459}
2460
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2461unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2462 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2463 unsigned Count = 0;
2464
2465 while (I != MBB.begin()) {
2466 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]2467 if (I->isDebugValue())
2468 continue;
Chris Lattner2b0a7a22010-02-11 19:25:55 +0000[diff] [blame]2469 if (I->getOpcode() != X86::JMP_4 &&
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2470 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2471 break;
2472 // Remove the branch.
2473 I->eraseFromParent();
2474 I = MBB.end();
2475 ++Count;
2476 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2477
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2478 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2479}
2480
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2481unsigned
2482X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2483 MachineBasicBlock *FBB,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2484 const SmallVectorImpl<MachineOperand> &Cond,
2485 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2486 // Shouldn't be a fall through.
2487 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]2488 assert((Cond.size() == 1 || Cond.size() == 0) &&
2489 "X86 branch conditions have one component!");
2490
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2491 if (Cond.empty()) {
2492 // Unconditional branch?
2493 assert(!FBB && "Unconditional branch with multiple successors!");
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2494 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]2495 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2496 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2497
2498 // Conditional branch.
2499 unsigned Count = 0;
2500 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2501 switch (CC) {
2502 case X86::COND_NP_OR_E:
2503 // Synthesize NP_OR_E with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2504 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2505 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2506 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2507 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2508 break;
2509 case X86::COND_NE_OR_P:
2510 // Synthesize NE_OR_P with two branches.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2511 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2512 ++Count;
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2513 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2514 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2515 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2516 default: {
2517 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2518 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2519 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2520 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]2521 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2522 if (FBB) {
2523 // Two-way Conditional branch. Insert the second branch.
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]2524 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]2525 ++Count;
2526 }
2527 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]2528}
2529
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]2530/// isHReg - Test if the given register is a physical h register.
2531static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2532 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]2533}
2534
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2535// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2536static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2537 bool HasAVX) {
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2538 // SrcReg(VR128) -> DestReg(GR64)
2539 // SrcReg(VR64) -> DestReg(GR64)
2540 // SrcReg(GR64) -> DestReg(VR128)
2541 // SrcReg(GR64) -> DestReg(VR64)
2542
2543 if (X86::GR64RegClass.contains(DestReg)) {
2544 if (X86::VR128RegClass.contains(SrcReg)) {
2545 // Copy from a VR128 register to a GR64 register.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2546 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2547 } else if (X86::VR64RegClass.contains(SrcReg)) {
2548 // Copy from a VR64 register to a GR64 register.
2549 return X86::MOVSDto64rr;
2550 }
2551 } else if (X86::GR64RegClass.contains(SrcReg)) {
2552 // Copy from a GR64 register to a VR128 register.
2553 if (X86::VR128RegClass.contains(DestReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2554 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2555 // Copy from a GR64 register to a VR64 register.
2556 else if (X86::VR64RegClass.contains(DestReg))
2557 return X86::MOV64toSDrr;
2558 }
2559
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]2560 // SrcReg(FR32) -> DestReg(GR32)
2561 // SrcReg(GR32) -> DestReg(FR32)
2562
2563 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2564 // Copy from a FR32 register to a GR32 register.
2565 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2566
2567 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2568 // Copy from a GR32 register to a FR32 register.
2569 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2570
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2571 return 0;
2572}
2573
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2574void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2575 MachineBasicBlock::iterator MI, DebugLoc DL,
2576 unsigned DestReg, unsigned SrcReg,
2577 bool KillSrc) const {
2578 // First deal with the normal symmetric copies.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2579 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2580 unsigned Opc = 0;
2581 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2582 Opc = X86::MOV64rr;
2583 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2584 Opc = X86::MOV32rr;
2585 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2586 Opc = X86::MOV16rr;
2587 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2588 // Copying to or from a physical H register on x86-64 requires a NOREX
2589 // move. Otherwise use a normal move.
2590 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]2591 TM.getSubtarget<X86Subtarget>().is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2592 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]2593 // Both operands must be encodable without an REX prefix.
2594 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2595 "8-bit H register can not be copied outside GR8_NOREX");
2596 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2597 Opc = X86::MOV8rr;
2598 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2599 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2600 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2601 Opc = X86::VMOVAPSYrr;
Jakob Stoklund Olesenec58a432010-07-08 22:30:35 +0000[diff] [blame]2602 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2603 Opc = X86::MMX_MOVQ64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]2604 else
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2605 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]2606
2607 if (Opc) {
2608 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2609 .addReg(SrcReg, getKillRegState(KillSrc));
2610 return;
2611 }
2612
2613 // Moving EFLAGS to / from another register requires a push and a pop.
2614 if (SrcReg == X86::EFLAGS) {
2615 if (X86::GR64RegClass.contains(DestReg)) {
2616 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2617 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2618 return;
2619 } else if (X86::GR32RegClass.contains(DestReg)) {
2620 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2621 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2622 return;
2623 }
2624 }
2625 if (DestReg == X86::EFLAGS) {
2626 if (X86::GR64RegClass.contains(SrcReg)) {
2627 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2628 .addReg(SrcReg, getKillRegState(KillSrc));
2629 BuildMI(MBB, MI, DL, get(X86::POPF64));
2630 return;
2631 } else if (X86::GR32RegClass.contains(SrcReg)) {
2632 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2633 .addReg(SrcReg, getKillRegState(KillSrc));
2634 BuildMI(MBB, MI, DL, get(X86::POPF32));
2635 return;
2636 }
2637 }
2638
2639 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2640 << " to " << RI.getName(DestReg) << '\n');
2641 llvm_unreachable("Cannot emit physreg copy instruction");
2642}
2643
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2644static unsigned getLoadStoreRegOpcode(unsigned Reg,
2645 const TargetRegisterClass *RC,
2646 bool isStackAligned,
2647 const TargetMachine &TM,
2648 bool load) {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2649 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2650 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]2651 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2652 llvm_unreachable("Unknown spill size");
2653 case 1:
2654 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2655 if (TM.getSubtarget<X86Subtarget>().is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2656 // Copying to or from a physical H register on x86-64 requires a NOREX
2657 // move. Otherwise use a normal move.
2658 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2659 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2660 return load ? X86::MOV8rm : X86::MOV8mr;
2661 case 2:
2662 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2663 return load ? X86::MOV16rm : X86::MOV16mr;
2664 case 4:
2665 if (X86::GR32RegClass.hasSubClassEq(RC))
2666 return load ? X86::MOV32rm : X86::MOV32mr;
2667 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2668 return load ?
2669 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2670 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2671 if (X86::RFP32RegClass.hasSubClassEq(RC))
2672 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2673 llvm_unreachable("Unknown 4-byte regclass");
2674 case 8:
2675 if (X86::GR64RegClass.hasSubClassEq(RC))
2676 return load ? X86::MOV64rm : X86::MOV64mr;
2677 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2678 return load ?
2679 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2680 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2681 if (X86::VR64RegClass.hasSubClassEq(RC))
2682 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2683 if (X86::RFP64RegClass.hasSubClassEq(RC))
2684 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2685 llvm_unreachable("Unknown 8-byte regclass");
2686 case 10:
2687 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2688 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2689 case 16: {
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]2690 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2691 // If stack is realigned we can use aligned stores.
2692 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2693 return load ?
2694 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2695 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2696 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]2697 return load ?
2698 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2699 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2700 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2701 case 32:
2702 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2703 // If stack is realigned we can use aligned stores.
2704 if (isStackAligned)
2705 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2706 else
2707 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2708 }
2709}
2710
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2711static unsigned getStoreRegOpcode(unsigned SrcReg,
2712 const TargetRegisterClass *RC,
2713 bool isStackAligned,
2714 TargetMachine &TM) {
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2715 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2716}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2717
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]2718
2719static unsigned getLoadRegOpcode(unsigned DestReg,
2720 const TargetRegisterClass *RC,
2721 bool isStackAligned,
2722 const TargetMachine &TM) {
2723 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2724}
2725
2726void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2727 MachineBasicBlock::iterator MI,
2728 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]2729 const TargetRegisterClass *RC,
2730 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]2731 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]2732 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2733 "Stack slot too small for store");
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2734 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2735 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]2736 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2737 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]2738 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2739 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2740 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2741}
2742
2743void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2744 bool isKill,
2745 SmallVectorImpl<MachineOperand> &Addr,
2746 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2747 MachineInstr::mmo_iterator MMOBegin,
2748 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2749 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2750 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2751 bool isAligned = MMOBegin != MMOEnd &&
2752 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2753 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]2754 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]2755 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2756 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2757 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]2758 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2759 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2760 NewMIs.push_back(MIB);
2761}
2762
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2763
2764void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]2765 MachineBasicBlock::iterator MI,
2766 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]2767 const TargetRegisterClass *RC,
2768 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]2769 const MachineFunction &MF = *MBB.getParent();
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2770 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2771 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
Evan Chengee9b90a2011-06-23 01:53:43 +0000[diff] [blame]2772 RI.canRealignStack(MF);
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2773 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]2774 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2775 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2776}
2777
2778void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2779 SmallVectorImpl<MachineOperand> &Addr,
2780 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2781 MachineInstr::mmo_iterator MMOBegin,
2782 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2783 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2784 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2785 bool isAligned = MMOBegin != MMOEnd &&
2786 (*MMOBegin)->getAlignment() >= Alignment;
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]2787 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]2788 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]2789 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2790 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2791 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]2792 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]2793 NewMIs.push_back(MIB);
2794}
2795
Manman Ren9bccb642012-05-31 17:20:29 +0000[diff] [blame]2796bool X86InstrInfo::
2797OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const {
2798 // If destination is a memory operand, do not perform this optimization.
2799 if ((SubInstr->getOpcode() != X86::SUB64rr) &&
2800 (SubInstr->getOpcode() != X86::SUB32rr) &&
2801 (SubInstr->getOpcode() != X86::SUB16rr) &&
2802 (SubInstr->getOpcode() != X86::SUB8rr) &&
2803 (SubInstr->getOpcode() != X86::SUB64ri32) &&
2804 (SubInstr->getOpcode() != X86::SUB64ri8) &&
2805 (SubInstr->getOpcode() != X86::SUB32ri) &&
2806 (SubInstr->getOpcode() != X86::SUB32ri8) &&
2807 (SubInstr->getOpcode() != X86::SUB16ri) &&
2808 (SubInstr->getOpcode() != X86::SUB16ri8) &&
2809 (SubInstr->getOpcode() != X86::SUB8ri))
2810 return false;
2811 unsigned DestReg = SubInstr->getOperand(0).getReg();
2812 if (MRI->use_begin(DestReg) != MRI->use_end())
2813 return false;
2814
2815 // There is no use of the destination register, we can replace SUB with CMP.
2816 switch (SubInstr->getOpcode()) {
2817 default: break;
2818 case X86::SUB64rr: SubInstr->setDesc(get(X86::CMP64rr)); break;
2819 case X86::SUB32rr: SubInstr->setDesc(get(X86::CMP32rr)); break;
2820 case X86::SUB16rr: SubInstr->setDesc(get(X86::CMP16rr)); break;
2821 case X86::SUB8rr: SubInstr->setDesc(get(X86::CMP8rr)); break;
2822 case X86::SUB64ri32: SubInstr->setDesc(get(X86::CMP64ri32)); break;
2823 case X86::SUB64ri8: SubInstr->setDesc(get(X86::CMP64ri8)); break;
2824 case X86::SUB32ri: SubInstr->setDesc(get(X86::CMP32ri)); break;
2825 case X86::SUB32ri8: SubInstr->setDesc(get(X86::CMP32ri8)); break;
2826 case X86::SUB16ri: SubInstr->setDesc(get(X86::CMP16ri)); break;
2827 case X86::SUB16ri8: SubInstr->setDesc(get(X86::CMP16ri8)); break;
2828 case X86::SUB8ri: SubInstr->setDesc(get(X86::CMP8ri)); break;
2829 }
2830 SubInstr->RemoveOperand(0);
2831 return true;
2832}
2833
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]2834/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2835/// instruction with two undef reads of the register being defined. This is
2836/// used for mapping:
2837/// %xmm4 = V_SET0
2838/// to:
2839/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2840///
2841static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2842 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2843 unsigned Reg = MI->getOperand(0).getReg();
2844 MI->setDesc(Desc);
2845
2846 // MachineInstr::addOperand() will insert explicit operands before any
2847 // implicit operands.
2848 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2849 .addReg(Reg, RegState::Undef);
2850 // But we don't trust that.
2851 assert(MI->getOperand(1).getReg() == Reg &&
2852 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2853 return true;
2854}
2855
2856bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2857 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2858 switch (MI->getOpcode()) {
2859 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]2860 case X86::FsFLD0SS:
2861 case X86::FsFLD0SD:
Jakob Stoklund Olesen024130892011-11-07 19:15:58 +0000[diff] [blame]2862 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]2863 case X86::TEST8ri_NOREX:
2864 MI->setDesc(get(X86::TEST8ri));
2865 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]2866 }
2867 return false;
2868}
2869
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]2870MachineInstr*
2871X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
Evan Cheng250e9172010-04-29 01:13:30 +0000[diff] [blame]2872 int FrameIx, uint64_t Offset,
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]2873 const MDNode *MDPtr,
2874 DebugLoc DL) const {
Evan Chenged69b382010-04-26 07:38:55 +0000[diff] [blame]2875 X86AddressMode AM;
2876 AM.BaseType = X86AddressMode::FrameIndexBase;
2877 AM.Base.FrameIndex = FrameIx;
2878 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2879 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2880 return &*MIB;
2881}
2882
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2883static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]2884 const SmallVectorImpl<MachineOperand> &MOs,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]2885 MachineInstr *MI,
2886 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2887 // Create the base instruction with the memory operand as the first part.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]2888 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2889 MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2890 MachineInstrBuilder MIB(NewMI);
2891 unsigned NumAddrOps = MOs.size();
2892 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2893 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2894 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]2895 addOffset(MIB, 0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2896
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2897 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]2898 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2899 for (unsigned i = 0; i != NumOps; ++i) {
2900 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2901 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2902 }
2903 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2904 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2905 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2906 }
2907 return MIB;
2908}
2909
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2910static MachineInstr *FuseInst(MachineFunction &MF,
2911 unsigned Opcode, unsigned OpNo,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]2912 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2913 MachineInstr *MI, const TargetInstrInfo &TII) {
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]2914 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2915 MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2916 MachineInstrBuilder MIB(NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2917
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2918 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2919 MachineOperand &MO = MI->getOperand(i);
2920 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2921 assert(MO.isReg() && "Expected to fold into reg operand!");
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2922 unsigned NumAddrOps = MOs.size();
2923 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2924 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2925 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]2926 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2927 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2928 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2929 }
2930 }
2931 return MIB;
2932}
2933
2934static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Dan Gohman906152a2009-01-05 17:59:02 +0000[diff] [blame]2935 const SmallVectorImpl<MachineOperand> &MOs,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2936 MachineInstr *MI) {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2937 MachineFunction &MF = *MI->getParent()->getParent();
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2938 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2939
2940 unsigned NumAddrOps = MOs.size();
2941 for (unsigned i = 0; i != NumAddrOps; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]2942 MIB.addOperand(MOs[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2943 if (NumAddrOps < 4) // FrameIndex only
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]2944 addOffset(MIB, 0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2945 return MIB.addImm(0);
2946}
2947
2948MachineInstr*
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]2949X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2950 MachineInstr *MI, unsigned i,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]2951 const SmallVectorImpl<MachineOperand> &MOs,
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]2952 unsigned Size, unsigned Align) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]2953 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2954 bool isTwoAddrFold = false;
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]2955 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2956 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]2957 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2958
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]2959 // FIXME: AsmPrinter doesn't know how to handle
2960 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2961 if (MI->getOpcode() == X86::ADD32ri &&
2962 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2963 return NULL;
2964
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2965 MachineInstr *NewMI = NULL;
2966 // Folding a memory location into the two-address part of a two-address
2967 // instruction is different than folding it other places. It requires
2968 // replacing the *two* registers with the memory location.
2969 if (isTwoAddr && NumOps >= 2 && i < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2970 MI->getOperand(0).isReg() &&
2971 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2972 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2973 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2974 isTwoAddrFold = true;
2975 } else if (i == 0) { // If operand 0
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]2976 if (MI->getOpcode() == X86::MOV64r0)
2977 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2978 else if (MI->getOpcode() == X86::MOV32r0)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2979 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]2980 else if (MI->getOpcode() == X86::MOV16r0)
2981 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2982 else if (MI->getOpcode() == X86::MOV8r0)
2983 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2984 if (NewMI)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2985 return NewMI;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2986
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2987 OpcodeTablePtr = &RegOp2MemOpTable0;
2988 } else if (i == 1) {
2989 OpcodeTablePtr = &RegOp2MemOpTable1;
2990 } else if (i == 2) {
2991 OpcodeTablePtr = &RegOp2MemOpTable2;
2992 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2993
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2994 // If table selected...
2995 if (OpcodeTablePtr) {
2996 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]2997 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2998 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]2999 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3000 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3001 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3002 if (Align < MinAlign)
3003 return NULL;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3004 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3005 if (Size) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3006 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3007 if (Size < RCSize) {
3008 // Check if it's safe to fold the load. If the size of the object is
3009 // narrower than the load width, then it's not.
3010 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
3011 return NULL;
3012 // If this is a 64-bit load, but the spill slot is 32, then we can do
3013 // a 32-bit load which is implicitly zero-extended. This likely is due
3014 // to liveintervalanalysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3015 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
3016 return NULL;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3017 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3018 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3019 }
3020 }
3021
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3022 if (isTwoAddrFold)
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3023 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3024 else
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3025 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3026
3027 if (NarrowToMOV32rm) {
3028 // If this is the special case where we use a MOV32rm to load a 32-bit
3029 // value and zero-extend the top bits. Change the destination register
3030 // to a 32-bit one.
3031 unsigned DstReg = NewMI->getOperand(0).getReg();
3032 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
3033 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]3034 X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3035 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]3036 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]3037 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3038 return NewMI;
3039 }
3040 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3041
3042 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]3043 if (PrintFailedFusing && !MI->isCopy())
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]3044 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3045 return NULL;
3046}
3047
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3048/// hasPartialRegUpdate - Return true for all instructions that only update
3049/// the first 32 or 64-bits of the destination register and leave the rest
3050/// unmodified. This can be used to avoid folding loads if the instructions
3051/// only update part of the destination register, and the non-updated part is
3052/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
3053/// instructions breaks the partial register dependency and it can improve
3054/// performance. e.g.:
3055///
3056/// movss (%rdi), %xmm0
3057/// cvtss2sd %xmm0, %xmm0
3058///
3059/// Instead of
3060/// cvtss2sd (%rdi), %xmm0
3061///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]3062/// FIXME: This should be turned into a TSFlags.
3063///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3064static bool hasPartialRegUpdate(unsigned Opcode) {
3065 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]3066 case X86::CVTSI2SSrr:
3067 case X86::CVTSI2SS64rr:
3068 case X86::CVTSI2SDrr:
3069 case X86::CVTSI2SD64rr:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3070 case X86::CVTSD2SSrr:
3071 case X86::Int_CVTSD2SSrr:
3072 case X86::CVTSS2SDrr:
3073 case X86::Int_CVTSS2SDrr:
3074 case X86::RCPSSr:
3075 case X86::RCPSSr_Int:
3076 case X86::ROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3077 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3078 case X86::ROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3079 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3080 case X86::RSQRTSSr:
3081 case X86::RSQRTSSr_Int:
3082 case X86::SQRTSSr:
3083 case X86::SQRTSSr_Int:
3084 // AVX encoded versions
3085 case X86::VCVTSD2SSrr:
3086 case X86::Int_VCVTSD2SSrr:
3087 case X86::VCVTSS2SDrr:
3088 case X86::Int_VCVTSS2SDrr:
3089 case X86::VRCPSSr:
3090 case X86::VROUNDSDr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3091 case X86::VROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3092 case X86::VROUNDSSr:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]3093 case X86::VROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3094 case X86::VRSQRTSSr:
3095 case X86::VSQRTSSr:
3096 return true;
3097 }
3098
3099 return false;
3100}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3101
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]3102/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3103/// instructions we would like before a partial register update.
3104unsigned X86InstrInfo::
3105getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3106 const TargetRegisterInfo *TRI) const {
3107 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3108 return 0;
3109
3110 // If MI is marked as reading Reg, the partial register update is wanted.
3111 const MachineOperand &MO = MI->getOperand(0);
3112 unsigned Reg = MO.getReg();
3113 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3114 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3115 return 0;
3116 } else {
3117 if (MI->readsRegister(Reg, TRI))
3118 return 0;
3119 }
3120
3121 // If any of the preceding 16 instructions are reading Reg, insert a
3122 // dependency breaking instruction. The magic number is based on a few
3123 // Nehalem experiments.
3124 return 16;
3125}
3126
3127void X86InstrInfo::
3128breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3129 const TargetRegisterInfo *TRI) const {
3130 unsigned Reg = MI->getOperand(OpNum).getReg();
3131 if (X86::VR128RegClass.contains(Reg)) {
3132 // These instructions are all floating point domain, so xorps is the best
3133 // choice.
3134 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3135 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3136 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3137 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3138 } else if (X86::VR256RegClass.contains(Reg)) {
3139 // Use vxorps to clear the full ymm register.
3140 // It wants to read and write the xmm sub-register.
3141 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3142 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3143 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3144 .addReg(Reg, RegState::ImplicitDefine);
3145 } else
3146 return;
3147 MI->addRegisterKilled(Reg, TRI, true);
3148}
3149
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3150MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3151 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3152 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3153 int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3154 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3155 if (NoFusing) return NULL;
3156
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3157 // Unless optimizing for size, don't fold to avoid partial
3158 // register update stalls
3159 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3160 hasPartialRegUpdate(MI->getOpcode()))
3161 return 0;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]3162
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3163 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3164 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3165 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3166 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3167 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3168 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3169 switch (MI->getOpcode()) {
3170 default: return NULL;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3171 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]3172 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3173 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3174 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3175 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3176 // Check if it's safe to fold the load. If the size of the object is
3177 // narrower than the load width, then it's not.
3178 if (Size < RCSize)
3179 return NULL;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3180 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3181 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3182 MI->getOperand(1).ChangeToImmediate(0);
3183 } else if (Ops.size() != 1)
3184 return NULL;
3185
3186 SmallVector<MachineOperand,4> MOs;
3187 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3188 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3189}
3190
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3191MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3192 MachineInstr *MI,
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]3193 const SmallVectorImpl<unsigned> &Ops,
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]3194 MachineInstr *LoadMI) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3195 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3196 if (NoFusing) return NULL;
3197
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]3198 // Unless optimizing for size, don't fold to avoid partial
3199 // register update stalls
3200 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3201 hasPartialRegUpdate(MI->getOpcode()))
3202 return 0;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]3203
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]3204 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]3205 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]3206 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]3207 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3208 else
3209 switch (LoadMI->getOpcode()) {
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3210 case X86::AVX_SET0PSY:
3211 case X86::AVX_SET0PDY:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]3212 case X86::AVX2_SETALLONES:
Craig Toppercb7e13d2012-01-13 08:12:35 +0000[diff] [blame]3213 case X86::AVX2_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3214 Alignment = 32;
3215 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3216 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3217 case X86::V_SETALLONES:
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3218 case X86::AVX_SETALLONES:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3219 Alignment = 16;
3220 break;
3221 case X86::FsFLD0SD:
3222 Alignment = 8;
3223 break;
3224 case X86::FsFLD0SS:
3225 Alignment = 4;
3226 break;
3227 default:
Eli Friedman87ef3872011-06-10 01:13:01 +0000[diff] [blame]3228 return 0;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3229 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3230 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3231 unsigned NewOpc = 0;
3232 switch (MI->getOpcode()) {
3233 default: return NULL;
3234 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3235 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3236 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3237 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3238 }
3239 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3240 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3241 MI->getOperand(1).ChangeToImmediate(0);
3242 } else if (Ops.size() != 1)
3243 return NULL;
3244
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]3245 // Make sure the subregisters match.
3246 // Otherwise we risk changing the size of the load.
3247 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3248 return NULL;
3249
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3250 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3251 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3252 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3253 case X86::V_SETALLONES:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3254 case X86::AVX_SET0PSY:
3255 case X86::AVX_SET0PDY:
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3256 case X86::AVX_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]3257 case X86::AVX2_SETALLONES:
Craig Toppercb7e13d2012-01-13 08:12:35 +0000[diff] [blame]3258 case X86::AVX2_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3259 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3260 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]3261 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3262 // Create a constant-pool entry and operands to load from it.
3263
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]3264 // Medium and large mode can't fold loads this way.
3265 if (TM.getCodeModel() != CodeModel::Small &&
3266 TM.getCodeModel() != CodeModel::Kernel)
3267 return NULL;
3268
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3269 // x86-32 PIC requires a PIC base register for constant pools.
3270 unsigned PICBase = 0;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3271 if (TM.getRelocationModel() == Reloc::PIC_) {
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]3272 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3273 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3274 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3275 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]3276 // This doesn't work for several reasons.
3277 // 1. GlobalBaseReg may have been spilled.
3278 // 2. It may not be live at MI.
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3279 return NULL;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]3280 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3281
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3282 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3283 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]3284 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3285 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3286 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3287 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]3288 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3289 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3290 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3291 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
Craig Toppercb7e13d2012-01-13 08:12:35 +0000[diff] [blame]3292 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]3293 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3294 else
3295 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3296
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]3297 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3298 Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]3299 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3300 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3301 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3302
3303 // Create operands to load from the constant pool entry.
3304 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3305 MOs.push_back(MachineOperand::CreateImm(1));
3306 MOs.push_back(MachineOperand::CreateReg(0, false));
3307 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]3308 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3309 break;
3310 }
3311 default: {
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3312 // Folding a normal load. Just copy the load's address operands.
3313 unsigned NumOps = LoadMI->getDesc().getNumOperands();
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3314 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3315 MOs.push_back(LoadMI->getOperand(i));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]3316 break;
3317 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]3318 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]3319 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3320}
3321
3322
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]3323bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3324 const SmallVectorImpl<unsigned> &Ops) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3325 // Check switch flag
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3326 if (NoFusing) return 0;
3327
3328 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3329 switch (MI->getOpcode()) {
3330 default: return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3331 case X86::TEST8rr:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3332 case X86::TEST16rr:
3333 case X86::TEST32rr:
3334 case X86::TEST64rr:
3335 return true;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]3336 case X86::ADD32ri:
3337 // FIXME: AsmPrinter doesn't know how to handle
3338 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3339 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3340 return false;
3341 break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3342 }
3343 }
3344
3345 if (Ops.size() != 1)
3346 return false;
3347
3348 unsigned OpNum = Ops[0];
3349 unsigned Opc = MI->getOpcode();
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]3350 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3351 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3352 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3353
3354 // Folding a memory location into the two-address part of a two-address
3355 // instruction is different than folding it other places. It requires
3356 // replacing the *two* registers with the memory location.
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3357 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3358 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3359 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3360 } else if (OpNum == 0) { // If operand 0
3361 switch (Opc) {
Chris Lattner79c136d2009-07-14 20:19:57 +0000[diff] [blame]3362 case X86::MOV8r0:
Dan Gohmanc1195802010-01-12 04:42:54 +0000[diff] [blame]3363 case X86::MOV16r0:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3364 case X86::MOV32r0:
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3365 case X86::MOV64r0: return true;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3366 default: break;
3367 }
3368 OpcodeTablePtr = &RegOp2MemOpTable0;
3369 } else if (OpNum == 1) {
3370 OpcodeTablePtr = &RegOp2MemOpTable1;
3371 } else if (OpNum == 2) {
3372 OpcodeTablePtr = &RegOp2MemOpTable2;
3373 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3374
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]3375 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3376 return true;
Jakob Stoklund Olesen7a7b55e2010-07-09 20:43:13 +0000[diff] [blame]3377 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3378}
3379
3380bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3381 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3382 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3383 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3384 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3385 if (I == MemOp2RegOpTable.end())
3386 return false;
3387 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3388 unsigned Index = I->second.second & TB_INDEX_MASK;
3389 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3390 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3391 if (UnfoldLoad && !FoldedLoad)
3392 return false;
3393 UnfoldLoad &= FoldedLoad;
3394 if (UnfoldStore && !FoldedStore)
3395 return false;
3396 UnfoldStore &= FoldedStore;
3397
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3398 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3399 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]3400 if (!MI->hasOneMemOperand() &&
3401 RC == &X86::VR128RegClass &&
3402 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3403 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3404 // conservatively assume the address is unaligned. That's bad for
3405 // performance.
3406 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3407 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3408 SmallVector<MachineOperand,2> BeforeOps;
3409 SmallVector<MachineOperand,2> AfterOps;
3410 SmallVector<MachineOperand,4> ImpOps;
3411 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3412 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3413 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3414 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]3415 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3416 ImpOps.push_back(Op);
3417 else if (i < Index)
3418 BeforeOps.push_back(Op);
3419 else if (i > Index)
3420 AfterOps.push_back(Op);
3421 }
3422
3423 // Emit the load instruction.
3424 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3425 std::pair<MachineInstr::mmo_iterator,
3426 MachineInstr::mmo_iterator> MMOs =
3427 MF.extractLoadMemRefs(MI->memoperands_begin(),
3428 MI->memoperands_end());
3429 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3430 if (UnfoldStore) {
3431 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3432 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3433 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]3434 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3435 MO.setIsKill(false);
3436 }
3437 }
3438 }
3439
3440 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3441 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3442 MachineInstrBuilder MIB(DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3443
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3444 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3445 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3446 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3447 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3448 if (FoldedLoad)
3449 MIB.addReg(Reg);
3450 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]3451 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3452 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3453 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]3454 MIB.addReg(MO.getReg(),
3455 getDefRegState(MO.isDef()) |
3456 RegState::Implicit |
3457 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]3458 getDeadRegState(MO.isDead()) |
3459 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3460 }
3461 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3462 unsigned NewOpc = 0;
3463 switch (DataMI->getOpcode()) {
3464 default: break;
3465 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3466 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3467 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3468 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3469 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3470 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3471 case X86::CMP8ri: {
3472 MachineOperand &MO0 = DataMI->getOperand(0);
3473 MachineOperand &MO1 = DataMI->getOperand(1);
3474 if (MO1.getImm() == 0) {
3475 switch (DataMI->getOpcode()) {
3476 default: break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3477 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3478 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3479 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3480 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]3481 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3482 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
3483 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
3484 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3485 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3486 MO1.ChangeToRegister(MO0.getReg(), false);
3487 }
3488 }
3489 }
3490 NewMIs.push_back(DataMI);
3491
3492 // Emit the store instruction.
3493 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3494 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3495 std::pair<MachineInstr::mmo_iterator,
3496 MachineInstr::mmo_iterator> MMOs =
3497 MF.extractStoreMemRefs(MI->memoperands_begin(),
3498 MI->memoperands_end());
3499 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3500 }
3501
3502 return true;
3503}
3504
3505bool
3506X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]3507 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]3508 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3509 return false;
3510
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3511 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3512 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3513 if (I == MemOp2RegOpTable.end())
3514 return false;
3515 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3516 unsigned Index = I->second.second & TB_INDEX_MASK;
3517 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3518 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3519 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3520 MachineFunction &MF = DAG.getMachineFunction();
3521 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3522 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]3523 std::vector<SDValue> AddrOps;
3524 std::vector<SDValue> BeforeOps;
3525 std::vector<SDValue> AfterOps;
Dale Johannesen9f3f72f2009-02-06 01:31:28 +0000[diff] [blame]3526 DebugLoc dl = N->getDebugLoc();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3527 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]3528 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]3529 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]3530 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3531 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]3532 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3533 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]3534 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3535 AfterOps.push_back(Op);
3536 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]3537 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3538 AddrOps.push_back(Chain);
3539
3540 // Emit the load instruction.
3541 SDNode *Load = 0;
3542 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]3543 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]3544 std::pair<MachineInstr::mmo_iterator,
3545 MachineInstr::mmo_iterator> MMOs =
3546 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3547 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]3548 if (!(*MMOs.first) &&
3549 RC == &X86::VR128RegClass &&
3550 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3551 // Do not introduce a slow unaligned load.
3552 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3553 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3554 bool isAligned = (*MMOs.first) &&
3555 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]3556 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3557 VT, MVT::Other, &AddrOps[0], AddrOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3558 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3559
3560 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3561 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3562 }
3563
3564 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]3565 std::vector<EVT> VTs;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3566 const TargetRegisterClass *DstRC = 0;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3567 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]3568 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3569 VTs.push_back(*DstRC->vt_begin());
3570 }
3571 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]3572 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]3573 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3574 VTs.push_back(VT);
3575 }
3576 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]3577 BeforeOps.push_back(SDValue(Load, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3578 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]3579 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3580 BeforeOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3581 NewNodes.push_back(NewNode);
3582
3583 // Emit the store instruction.
3584 if (FoldedStore) {
3585 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]3586 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3587 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]3588 std::pair<MachineInstr::mmo_iterator,
3589 MachineInstr::mmo_iterator> MMOs =
3590 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3591 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]3592 if (!(*MMOs.first) &&
3593 RC == &X86::VR128RegClass &&
3594 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3595 // Do not introduce a slow unaligned store.
3596 return false;
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3597 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3598 bool isAligned = (*MMOs.first) &&
3599 (*MMOs.first)->getAlignment() >= Alignment;
Dan Gohman32f71d72009-09-25 18:54:59 +0000[diff] [blame]3600 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3601 isAligned, TM),
3602 dl, MVT::Other,
3603 &AddrOps[0], AddrOps.size());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3604 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3605
3606 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]3607 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3608 }
3609
3610 return true;
3611}
3612
3613unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]3614 bool UnfoldLoad, bool UnfoldStore,
3615 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]3616 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3617 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3618 if (I == MemOp2RegOpTable.end())
3619 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3620 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3621 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3622 if (UnfoldLoad && !FoldedLoad)
3623 return 0;
3624 if (UnfoldStore && !FoldedStore)
3625 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]3626 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]3627 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]3628 return I->second.first;
3629}
3630
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3631bool
3632X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3633 int64_t &Offset1, int64_t &Offset2) const {
3634 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3635 return false;
3636 unsigned Opc1 = Load1->getMachineOpcode();
3637 unsigned Opc2 = Load2->getMachineOpcode();
3638 switch (Opc1) {
3639 default: return false;
3640 case X86::MOV8rm:
3641 case X86::MOV16rm:
3642 case X86::MOV32rm:
3643 case X86::MOV64rm:
3644 case X86::LD_Fp32m:
3645 case X86::LD_Fp64m:
3646 case X86::LD_Fp80m:
3647 case X86::MOVSSrm:
3648 case X86::MOVSDrm:
3649 case X86::MMX_MOVD64rm:
3650 case X86::MMX_MOVQ64rm:
3651 case X86::FsMOVAPSrm:
3652 case X86::FsMOVAPDrm:
3653 case X86::MOVAPSrm:
3654 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3655 case X86::MOVAPDrm:
3656 case X86::MOVDQArm:
3657 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]3658 // AVX load instructions
3659 case X86::VMOVSSrm:
3660 case X86::VMOVSDrm:
3661 case X86::FsVMOVAPSrm:
3662 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3663 case X86::VMOVAPSrm:
3664 case X86::VMOVUPSrm:
3665 case X86::VMOVAPDrm:
3666 case X86::VMOVDQArm:
3667 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3668 case X86::VMOVAPSYrm:
3669 case X86::VMOVUPSYrm:
3670 case X86::VMOVAPDYrm:
3671 case X86::VMOVDQAYrm:
3672 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3673 break;
3674 }
3675 switch (Opc2) {
3676 default: return false;
3677 case X86::MOV8rm:
3678 case X86::MOV16rm:
3679 case X86::MOV32rm:
3680 case X86::MOV64rm:
3681 case X86::LD_Fp32m:
3682 case X86::LD_Fp64m:
3683 case X86::LD_Fp80m:
3684 case X86::MOVSSrm:
3685 case X86::MOVSDrm:
3686 case X86::MMX_MOVD64rm:
3687 case X86::MMX_MOVQ64rm:
3688 case X86::FsMOVAPSrm:
3689 case X86::FsMOVAPDrm:
3690 case X86::MOVAPSrm:
3691 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3692 case X86::MOVAPDrm:
3693 case X86::MOVDQArm:
3694 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]3695 // AVX load instructions
3696 case X86::VMOVSSrm:
3697 case X86::VMOVSDrm:
3698 case X86::FsVMOVAPSrm:
3699 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3700 case X86::VMOVAPSrm:
3701 case X86::VMOVUPSrm:
3702 case X86::VMOVAPDrm:
3703 case X86::VMOVDQArm:
3704 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3705 case X86::VMOVAPSYrm:
3706 case X86::VMOVUPSYrm:
3707 case X86::VMOVAPDYrm:
3708 case X86::VMOVDQAYrm:
3709 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3710 break;
3711 }
3712
3713 // Check if chain operands and base addresses match.
3714 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3715 Load1->getOperand(5) != Load2->getOperand(5))
3716 return false;
3717 // Segment operands should match as well.
3718 if (Load1->getOperand(4) != Load2->getOperand(4))
3719 return false;
3720 // Scale should be 1, Index should be Reg0.
3721 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3722 Load1->getOperand(2) == Load2->getOperand(2)) {
3723 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3724 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3725
3726 // Now let's examine the displacements.
3727 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3728 isa<ConstantSDNode>(Load2->getOperand(3))) {
3729 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3730 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3731 return true;
3732 }
3733 }
3734 return false;
3735}
3736
3737bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3738 int64_t Offset1, int64_t Offset2,
3739 unsigned NumLoads) const {
3740 assert(Offset2 > Offset1);
3741 if ((Offset2 - Offset1) / 8 > 64)
3742 return false;
3743
3744 unsigned Opc1 = Load1->getMachineOpcode();
3745 unsigned Opc2 = Load2->getMachineOpcode();
3746 if (Opc1 != Opc2)
3747 return false; // FIXME: overly conservative?
3748
3749 switch (Opc1) {
3750 default: break;
3751 case X86::LD_Fp32m:
3752 case X86::LD_Fp64m:
3753 case X86::LD_Fp80m:
3754 case X86::MMX_MOVD64rm:
3755 case X86::MMX_MOVQ64rm:
3756 return false;
3757 }
3758
3759 EVT VT = Load1->getValueType(0);
3760 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]3761 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3762 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3763 // have 16 of them to play with.
3764 if (TM.getSubtargetImpl()->is64Bit()) {
3765 if (NumLoads >= 3)
3766 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]3767 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3768 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]3769 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3770 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3771 case MVT::i8:
3772 case MVT::i16:
3773 case MVT::i32:
3774 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]3775 case MVT::f32:
3776 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3777 if (NumLoads)
3778 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]3779 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]3780 }
3781
3782 return true;
3783}
3784
3785
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3786bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]3787ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3788 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]3789 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3790 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3791 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]3792 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3793 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3794}
3795
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]3796bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]3797isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3798 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]3799 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]3800 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3801 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]3802}
3803
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]3804/// getGlobalBaseReg - Return a virtual register initialized with the
3805/// the global base register value. Output instructions required to
3806/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]3807///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3808/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3809///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]3810unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3811 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3812 "X86-64 PIC uses RIP relative addressing");
3813
3814 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3815 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3816 if (GlobalBaseReg != 0)
3817 return GlobalBaseReg;
3818
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3819 // Create the register. The code to initialize it is inserted
3820 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]3821 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]3822 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]3823 X86FI->setGlobalBaseReg(GlobalBaseReg);
3824 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]3825}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]3826
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3827// These are the replaceable SSE instructions. Some of these have Int variants
3828// that we don't include here. We don't want to replace instructions selected
3829// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]3830static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]3831 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]3832 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3833 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3834 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3835 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3836 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3837 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3838 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3839 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3840 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3841 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3842 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3843 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3844 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3845 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3846 // AVX 128-bit support
3847 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3848 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3849 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3850 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3851 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3852 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3853 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3854 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3855 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3856 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3857 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3858 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]3859 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3860 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3861 // AVX 256-bit support
3862 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3863 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3864 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3865 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3866 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]3867 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
3868};
3869
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]3870static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]3871 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]3872 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
3873 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
3874 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
3875 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
3876 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
3877 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
3878 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]3879 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
3880 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3881 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3882 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
3883 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
3884 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3885 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3886};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]3887
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3888// FIXME: Some shuffle and unpack instructions have equivalents in different
3889// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]3890
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]3891static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]3892 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3893 if (ReplaceableInstrs[i][domain-1] == opcode)
3894 return ReplaceableInstrs[i];
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]3895 return 0;
3896}
3897
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]3898static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]3899 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3900 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3901 return ReplaceableInstrsAVX2[i];
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3902 return 0;
3903}
3904
3905std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]3906X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3907 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]3908 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]3909 uint16_t validDomains = 0;
3910 if (domain && lookup(MI->getOpcode(), domain))
3911 validDomains = 0xe;
3912 else if (domain && lookupAVX2(MI->getOpcode(), domain))
3913 validDomains = hasAVX2 ? 0xe : 0x6;
3914 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3915}
3916
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]3917void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3918 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3919 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3920 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]3921 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]3922 if (!table) { // try the other table
3923 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3924 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]3925 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]3926 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]3927 assert(table && "Cannot change domain");
3928 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]3929}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]3930
3931/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3932void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3933 NopInst.setOpcode(X86::NOOP);
3934}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3935
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]3936bool X86InstrInfo::isHighLatencyDef(int opc) const {
3937 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]3938 default: return false;
3939 case X86::DIVSDrm:
3940 case X86::DIVSDrm_Int:
3941 case X86::DIVSDrr:
3942 case X86::DIVSDrr_Int:
3943 case X86::DIVSSrm:
3944 case X86::DIVSSrm_Int:
3945 case X86::DIVSSrr:
3946 case X86::DIVSSrr_Int:
3947 case X86::SQRTPDm:
3948 case X86::SQRTPDm_Int:
3949 case X86::SQRTPDr:
3950 case X86::SQRTPDr_Int:
3951 case X86::SQRTPSm:
3952 case X86::SQRTPSm_Int:
3953 case X86::SQRTPSr:
3954 case X86::SQRTPSr_Int:
3955 case X86::SQRTSDm:
3956 case X86::SQRTSDm_Int:
3957 case X86::SQRTSDr:
3958 case X86::SQRTSDr_Int:
3959 case X86::SQRTSSm:
3960 case X86::SQRTSSm_Int:
3961 case X86::SQRTSSr:
3962 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]3963 // AVX instructions with high latency
3964 case X86::VDIVSDrm:
3965 case X86::VDIVSDrm_Int:
3966 case X86::VDIVSDrr:
3967 case X86::VDIVSDrr_Int:
3968 case X86::VDIVSSrm:
3969 case X86::VDIVSSrm_Int:
3970 case X86::VDIVSSrr:
3971 case X86::VDIVSSrr_Int:
3972 case X86::VSQRTPDm:
3973 case X86::VSQRTPDm_Int:
3974 case X86::VSQRTPDr:
3975 case X86::VSQRTPDr_Int:
3976 case X86::VSQRTPSm:
3977 case X86::VSQRTPSm_Int:
3978 case X86::VSQRTPSr:
3979 case X86::VSQRTPSr_Int:
3980 case X86::VSQRTSDm:
3981 case X86::VSQRTSDm_Int:
3982 case X86::VSQRTSDr:
3983 case X86::VSQRTSSm:
3984 case X86::VSQRTSSm_Int:
3985 case X86::VSQRTSSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]3986 return true;
3987 }
3988}
3989
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]3990bool X86InstrInfo::
3991hasHighOperandLatency(const InstrItineraryData *ItinData,
3992 const MachineRegisterInfo *MRI,
3993 const MachineInstr *DefMI, unsigned DefIdx,
3994 const MachineInstr *UseMI, unsigned UseIdx) const {
3995 return isHighLatencyDef(DefMI->getOpcode());
3996}
3997
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]3998namespace {
3999 /// CGBR - Create Global Base Reg pass. This initializes the PIC
4000 /// global base register for x86-32.
4001 struct CGBR : public MachineFunctionPass {
4002 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]4003 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4004
4005 virtual bool runOnMachineFunction(MachineFunction &MF) {
4006 const X86TargetMachine *TM =
4007 static_cast<const X86TargetMachine *>(&MF.getTarget());
4008
4009 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
4010 "X86-64 PIC uses RIP relative addressing");
4011
4012 // Only emit a global base reg in PIC mode.
4013 if (TM->getRelocationModel() != Reloc::PIC_)
4014 return false;
4015
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]4016 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
4017 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4018
4019 // If we didn't need a GlobalBaseReg, don't insert code.
4020 if (GlobalBaseReg == 0)
4021 return false;
4022
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4023 // Insert the set of GlobalBaseReg into the first MBB of the function
4024 MachineBasicBlock &FirstMBB = MF.front();
4025 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
4026 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
4027 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4028 const X86InstrInfo *TII = TM->getInstrInfo();
4029
4030 unsigned PC;
4031 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]4032 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4033 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]4034 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4035
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4036 // Operand of MovePCtoStack is completely ignored by asm printer. It's
4037 // only used in JIT code emission as displacement to pc.
4038 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4039
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4040 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
4041 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
4042 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4043 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
4044 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4045 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
4046 X86II::MO_GOT_ABSOLUTE_ADDRESS);
4047 }
4048
4049 return true;
4050 }
4051
4052 virtual const char *getPassName() const {
4053 return "X86 PIC Global Base Reg Initialization";
4054 }
4055
4056 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4057 AU.setPreservesCFG();
4058 MachineFunctionPass::getAnalysisUsage(AU);
4059 }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]4060
4061 private:
4062 unsigned BaseReg;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]4063 };
4064}
4065
4066char CGBR::ID = 0;
4067FunctionPass*
4068llvm::createGlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]4069
4070namespace {
4071 struct LDTLSCleanup : public MachineFunctionPass {
4072 static char ID;
4073 LDTLSCleanup() : MachineFunctionPass(ID) {}
4074
4075 virtual bool runOnMachineFunction(MachineFunction &MF) {
4076 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
4077 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
4078 // No point folding accesses if there isn't at least two.
4079 return false;
4080 }
4081
4082 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
4083 return VisitNode(DT->getRootNode(), 0);
4084 }
4085
4086 // Visit the dominator subtree rooted at Node in pre-order.
4087 // If TLSBaseAddrReg is non-null, then use that to replace any
4088 // TLS_base_addr instructions. Otherwise, create the register
4089 // when the first such instruction is seen, and then use it
4090 // as we encounter more instructions.
4091 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
4092 MachineBasicBlock *BB = Node->getBlock();
4093 bool Changed = false;
4094
4095 // Traverse the current block.
4096 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
4097 ++I) {
4098 switch (I->getOpcode()) {
4099 case X86::TLS_base_addr32:
4100 case X86::TLS_base_addr64:
4101 if (TLSBaseAddrReg)
4102 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
4103 else
4104 I = SetRegister(I, &TLSBaseAddrReg);
4105 Changed = true;
4106 break;
4107 default:
4108 break;
4109 }
4110 }
4111
4112 // Visit the children of this block in the dominator tree.
4113 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
4114 I != E; ++I) {
4115 Changed |= VisitNode(*I, TLSBaseAddrReg);
4116 }
4117
4118 return Changed;
4119 }
4120
4121 // Replace the TLS_base_addr instruction I with a copy from
4122 // TLSBaseAddrReg, returning the new instruction.
4123 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
4124 unsigned TLSBaseAddrReg) {
4125 MachineFunction *MF = I->getParent()->getParent();
4126 const X86TargetMachine *TM =
4127 static_cast<const X86TargetMachine *>(&MF->getTarget());
4128 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4129 const X86InstrInfo *TII = TM->getInstrInfo();
4130
4131 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
4132 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
4133 TII->get(TargetOpcode::COPY),
4134 is64Bit ? X86::RAX : X86::EAX)
4135 .addReg(TLSBaseAddrReg);
4136
4137 // Erase the TLS_base_addr instruction.
4138 I->eraseFromParent();
4139
4140 return Copy;
4141 }
4142
4143 // Create a virtal register in *TLSBaseAddrReg, and populate it by
4144 // inserting a copy instruction after I. Returns the new instruction.
4145 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
4146 MachineFunction *MF = I->getParent()->getParent();
4147 const X86TargetMachine *TM =
4148 static_cast<const X86TargetMachine *>(&MF->getTarget());
4149 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4150 const X86InstrInfo *TII = TM->getInstrInfo();
4151
4152 // Create a virtual register for the TLS base address.
4153 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4154 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
4155 ? &X86::GR64RegClass
4156 : &X86::GR32RegClass);
4157
4158 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
4159 MachineInstr *Next = I->getNextNode();
4160 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
4161 TII->get(TargetOpcode::COPY),
4162 *TLSBaseAddrReg)
4163 .addReg(is64Bit ? X86::RAX : X86::EAX);
4164
4165 return Copy;
4166 }
4167
4168 virtual const char *getPassName() const {
4169 return "Local Dynamic TLS Access Clean-up";
4170 }
4171
4172 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4173 AU.setPreservesCFG();
4174 AU.addRequired<MachineDominatorTree>();
4175 MachineFunctionPass::getAnalysisUsage(AU);
4176 }
4177 };
4178}
4179
4180char LDTLSCleanup::ID = 0;
4181FunctionPass*
4182llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }