Jia Liu | 9f61011 | 2012-02-17 08:55:11 +0000 | [diff] [blame] | 1 | //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===// |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | f3ebc3f | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 7 | // |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file contains the Mips implementation of the TargetInstrInfo class. |
| 11 | // |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 12 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 13 | |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 14 | #include "MipsInstrInfo.h" |
Akira Hatanaka | 9c6028f | 2011-07-07 23:56:50 +0000 | [diff] [blame] | 15 | #include "InstPrinter/MipsInstPrinter.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 16 | #include "MipsMachineFunction.h" |
Eric Christopher | d8abc3a | 2015-01-08 18:18:54 +0000 | [diff] [blame] | 17 | #include "MipsSubtarget.h" |
Chandler Carruth | ed0881b | 2012-12-03 16:50:05 +0000 | [diff] [blame] | 18 | #include "llvm/ADT/STLExtras.h" |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Dan Gohman | d5ca7064 | 2009-06-03 20:30:14 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Torok Edwin | 56d0659 | 2009-07-11 20:10:48 +0000 | [diff] [blame] | 21 | #include "llvm/Support/ErrorHandling.h" |
Evan Cheng | 2bb4035 | 2011-08-24 18:08:43 +0000 | [diff] [blame] | 22 | #include "llvm/Support/TargetRegistry.h" |
Evan Cheng | 1e210d0 | 2011-06-28 20:07:07 +0000 | [diff] [blame] | 23 | |
Chandler Carruth | d174b72 | 2014-04-22 02:03:14 +0000 | [diff] [blame] | 24 | using namespace llvm; |
| 25 | |
Juergen Ributzka | d12ccbd | 2013-11-19 00:57:56 +0000 | [diff] [blame] | 26 | #define GET_INSTRINFO_CTOR_DTOR |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 27 | #include "MipsGenInstrInfo.inc" |
| 28 | |
Juergen Ributzka | d12ccbd | 2013-11-19 00:57:56 +0000 | [diff] [blame] | 29 | // Pin the vtable to this file. |
| 30 | void MipsInstrInfo::anchor() {} |
| 31 | |
Eric Christopher | 675cb4d | 2014-07-18 23:25:00 +0000 | [diff] [blame] | 32 | MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) |
| 33 | : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), |
| 34 | Subtarget(STI), UncondBrOpc(UncondBr) {} |
Akira Hatanaka | 9c6028f | 2011-07-07 23:56:50 +0000 | [diff] [blame] | 35 | |
Eric Christopher | 675cb4d | 2014-07-18 23:25:00 +0000 | [diff] [blame] | 36 | const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) { |
| 37 | if (STI.inMips16Mode()) |
| 38 | return llvm::createMips16InstrInfo(STI); |
Akira Hatanaka | fab8929 | 2012-08-02 18:21:47 +0000 | [diff] [blame] | 39 | |
Eric Christopher | 675cb4d | 2014-07-18 23:25:00 +0000 | [diff] [blame] | 40 | return llvm::createMipsSEInstrInfo(STI); |
Akira Hatanaka | fab8929 | 2012-08-02 18:21:47 +0000 | [diff] [blame] | 41 | } |
| 42 | |
Akira Hatanaka | b7fa3c9 | 2012-07-31 21:49:49 +0000 | [diff] [blame] | 43 | bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { |
Dan Gohman | 0d1e9a8 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 44 | return op.isImm() && op.getImm() == 0; |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 47 | /// insertNoop - If data hazard condition is found insert the target nop |
| 48 | /// instruction. |
Simon Dardis | 9a3f32c | 2016-03-29 13:02:19 +0000 | [diff] [blame] | 49 | // FIXME: This appears to be dead code. |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 50 | void MipsInstrInfo:: |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 51 | insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 52 | { |
Chris Lattner | 6f306d7 | 2010-04-02 20:16:16 +0000 | [diff] [blame] | 53 | DebugLoc DL; |
Bill Wendling | f6d609a | 2009-02-12 00:02:55 +0000 | [diff] [blame] | 54 | BuildMI(MBB, MI, DL, get(Mips::NOP)); |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 55 | } |
| 56 | |
Justin Lebar | 0af80cd | 2016-07-15 18:26:59 +0000 | [diff] [blame] | 57 | MachineMemOperand * |
| 58 | MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI, |
| 59 | MachineMemOperand::Flags Flags) const { |
Akira Hatanaka | 1cf7576 | 2011-12-24 03:11:18 +0000 | [diff] [blame] | 60 | MachineFunction &MF = *MBB.getParent(); |
Matthias Braun | 941a705 | 2016-07-28 18:40:00 +0000 | [diff] [blame^] | 61 | MachineFrameInfo &MFI = MF.getFrameInfo(); |
Akira Hatanaka | 1cf7576 | 2011-12-24 03:11:18 +0000 | [diff] [blame] | 62 | unsigned Align = MFI.getObjectAlignment(FI); |
Jia Liu | f54f60f | 2012-02-28 07:46:26 +0000 | [diff] [blame] | 63 | |
Alex Lorenz | e40c8a2 | 2015-08-11 23:09:45 +0000 | [diff] [blame] | 64 | return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), |
Justin Lebar | 0af80cd | 2016-07-15 18:26:59 +0000 | [diff] [blame] | 65 | Flags, MFI.getObjectSize(FI), Align); |
Akira Hatanaka | 1cf7576 | 2011-12-24 03:11:18 +0000 | [diff] [blame] | 66 | } |
| 67 | |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 68 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 69 | // Branch Analysis |
Akira Hatanaka | e248912 | 2011-04-15 21:51:11 +0000 | [diff] [blame] | 70 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 71 | |
Akira Hatanaka | b7fa3c9 | 2012-07-31 21:49:49 +0000 | [diff] [blame] | 72 | void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, |
| 73 | MachineBasicBlock *&BB, |
| 74 | SmallVectorImpl<MachineOperand> &Cond) const { |
Akira Hatanaka | 067d815 | 2013-05-13 17:43:19 +0000 | [diff] [blame] | 75 | assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch"); |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 76 | int NumOp = Inst->getNumExplicitOperands(); |
Jia Liu | f54f60f | 2012-02-28 07:46:26 +0000 | [diff] [blame] | 77 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 78 | // for both int and fp branches, the last explicit operand is the |
| 79 | // MBB. |
| 80 | BB = Inst->getOperand(NumOp-1).getMBB(); |
| 81 | Cond.push_back(MachineOperand::CreateImm(Opc)); |
Bruno Cardoso Lopes | bcaf6e5 | 2008-07-28 19:11:24 +0000 | [diff] [blame] | 82 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 83 | for (int i=0; i<NumOp-1; i++) |
| 84 | Cond.push_back(Inst->getOperand(i)); |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 85 | } |
| 86 | |
Jacques Pienaar | 71c30a1 | 2016-07-15 14:41:04 +0000 | [diff] [blame] | 87 | bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 88 | MachineBasicBlock *&TBB, |
| 89 | MachineBasicBlock *&FBB, |
Evan Cheng | 64dfcac | 2009-02-09 07:14:22 +0000 | [diff] [blame] | 90 | SmallVectorImpl<MachineOperand> &Cond, |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 91 | bool AllowModify) const { |
| 92 | SmallVector<MachineInstr*, 2> BranchInstrs; |
Jacques Pienaar | 71c30a1 | 2016-07-15 14:41:04 +0000 | [diff] [blame] | 93 | BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); |
Akira Hatanaka | fcdd9b1 | 2012-09-13 17:12:37 +0000 | [diff] [blame] | 94 | |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 95 | return (BT == BT_None) || (BT == BT_Indirect); |
Jia Liu | f54f60f | 2012-02-28 07:46:26 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 98 | void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 99 | const DebugLoc &DL, |
| 100 | ArrayRef<MachineOperand> Cond) const { |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 101 | unsigned Opc = Cond[0].getImm(); |
Evan Cheng | 6cc775f | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 102 | const MCInstrDesc &MCID = get(Opc); |
| 103 | MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 104 | |
Akira Hatanaka | fcdd9b1 | 2012-09-13 17:12:37 +0000 | [diff] [blame] | 105 | for (unsigned i = 1; i < Cond.size(); ++i) { |
| 106 | if (Cond[i].isReg()) |
| 107 | MIB.addReg(Cond[i].getReg()); |
| 108 | else if (Cond[i].isImm()) |
| 109 | MIB.addImm(Cond[i].getImm()); |
| 110 | else |
Craig Topper | beb77bd | 2016-04-24 04:38:29 +0000 | [diff] [blame] | 111 | assert(false && "Cannot copy operand"); |
Akira Hatanaka | fcdd9b1 | 2012-09-13 17:12:37 +0000 | [diff] [blame] | 112 | } |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 113 | MIB.addMBB(TBB); |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 114 | } |
| 115 | |
Benjamin Kramer | bdc4956 | 2016-06-12 15:39:02 +0000 | [diff] [blame] | 116 | unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB, |
| 117 | MachineBasicBlock *TBB, |
| 118 | MachineBasicBlock *FBB, |
| 119 | ArrayRef<MachineOperand> Cond, |
| 120 | const DebugLoc &DL) const { |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 121 | // Shouldn't be a fall through. |
| 122 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 123 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 124 | // # of condition operands: |
| 125 | // Unconditional branches: 0 |
| 126 | // Floating point branches: 1 (opc) |
| 127 | // Int BranchZero: 2 (opc, reg) |
| 128 | // Int Branch: 3 (opc, reg0, reg1) |
| 129 | assert((Cond.size() <= 3) && |
| 130 | "# of Mips branch conditions must be <= 3!"); |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 131 | |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 132 | // Two-way Conditional branch. |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 133 | if (FBB) { |
| 134 | BuildCondBr(MBB, TBB, DL, Cond); |
Akira Hatanaka | 5d5e0d8 | 2011-12-12 22:39:35 +0000 | [diff] [blame] | 135 | BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB); |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 136 | return 2; |
| 137 | } |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 138 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 139 | // One way branch. |
| 140 | // Unconditional branch. |
| 141 | if (Cond.empty()) |
Akira Hatanaka | 5d5e0d8 | 2011-12-12 22:39:35 +0000 | [diff] [blame] | 142 | BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB); |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 143 | else // Conditional branch. |
| 144 | BuildCondBr(MBB, TBB, DL, Cond); |
| 145 | return 1; |
Bruno Cardoso Lopes | 35e43c4 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 146 | } |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 147 | |
Eric Christopher | 754d54f | 2014-07-18 20:35:49 +0000 | [diff] [blame] | 148 | unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 149 | MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); |
| 150 | MachineBasicBlock::reverse_iterator FirstBr; |
| 151 | unsigned removed; |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 152 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 153 | // Skip all the debug instructions. |
| 154 | while (I != REnd && I->isDebugValue()) |
| 155 | ++I; |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 156 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 157 | FirstBr = I; |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 158 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 159 | // Up to 2 branches are removed. |
| 160 | // Note that indirect branches are not removed. |
Eric Christopher | 675cb4d | 2014-07-18 23:25:00 +0000 | [diff] [blame] | 161 | for (removed = 0; I != REnd && removed < 2; ++I, ++removed) |
Akira Hatanaka | 067d815 | 2013-05-13 17:43:19 +0000 | [diff] [blame] | 162 | if (!getAnalyzableBrOpc(I->getOpcode())) |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 163 | break; |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 164 | |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 165 | MBB.erase(I.base(), FirstBr.base()); |
| 166 | |
| 167 | return removed; |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 168 | } |
| 169 | |
Bruno Cardoso Lopes | ed874ef | 2011-03-04 17:51:39 +0000 | [diff] [blame] | 170 | /// ReverseBranchCondition - Return the inverse opcode of the |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 171 | /// specified Branch instruction. |
Eric Christopher | 754d54f | 2014-07-18 20:35:49 +0000 | [diff] [blame] | 172 | bool MipsInstrInfo::ReverseBranchCondition( |
| 173 | SmallVectorImpl<MachineOperand> &Cond) const { |
Akira Hatanaka | 93f898f | 2011-04-01 17:39:08 +0000 | [diff] [blame] | 174 | assert( (Cond.size() && Cond.size() <= 3) && |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 175 | "Invalid Mips branch condition!"); |
Akira Hatanaka | 067d815 | 2013-05-13 17:43:19 +0000 | [diff] [blame] | 176 | Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); |
Bruno Cardoso Lopes | 7b616f5 | 2007-08-18 01:56:48 +0000 | [diff] [blame] | 177 | return false; |
| 178 | } |
Dan Gohman | d5ca7064 | 2009-06-03 20:30:14 +0000 | [diff] [blame] | 179 | |
Jacques Pienaar | 71c30a1 | 2016-07-15 14:41:04 +0000 | [diff] [blame] | 180 | MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( |
Eric Christopher | 754d54f | 2014-07-18 20:35:49 +0000 | [diff] [blame] | 181 | MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, |
| 182 | SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, |
| 183 | SmallVectorImpl<MachineInstr *> &BranchInstrs) const { |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 184 | |
| 185 | MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); |
| 186 | |
| 187 | // Skip all the debug instructions. |
| 188 | while (I != REnd && I->isDebugValue()) |
| 189 | ++I; |
| 190 | |
Duncan P. N. Exon Smith | 6307eb5 | 2016-02-23 02:46:52 +0000 | [diff] [blame] | 191 | if (I == REnd || !isUnpredicatedTerminator(*I)) { |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 192 | // This block ends with no branches (it just falls through to its succ). |
| 193 | // Leave TBB/FBB null. |
Craig Topper | 062a2ba | 2014-04-25 05:30:21 +0000 | [diff] [blame] | 194 | TBB = FBB = nullptr; |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 195 | return BT_NoBranch; |
| 196 | } |
| 197 | |
| 198 | MachineInstr *LastInst = &*I; |
| 199 | unsigned LastOpc = LastInst->getOpcode(); |
| 200 | BranchInstrs.push_back(LastInst); |
| 201 | |
| 202 | // Not an analyzable branch (e.g., indirect jump). |
Akira Hatanaka | 067d815 | 2013-05-13 17:43:19 +0000 | [diff] [blame] | 203 | if (!getAnalyzableBrOpc(LastOpc)) |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 204 | return LastInst->isIndirectBranch() ? BT_Indirect : BT_None; |
| 205 | |
| 206 | // Get the second to last instruction in the block. |
| 207 | unsigned SecondLastOpc = 0; |
Craig Topper | 062a2ba | 2014-04-25 05:30:21 +0000 | [diff] [blame] | 208 | MachineInstr *SecondLastInst = nullptr; |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 209 | |
| 210 | if (++I != REnd) { |
| 211 | SecondLastInst = &*I; |
Akira Hatanaka | 067d815 | 2013-05-13 17:43:19 +0000 | [diff] [blame] | 212 | SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode()); |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 213 | |
| 214 | // Not an analyzable branch (must be an indirect jump). |
Duncan P. N. Exon Smith | 6307eb5 | 2016-02-23 02:46:52 +0000 | [diff] [blame] | 215 | if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc) |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 216 | return BT_None; |
| 217 | } |
| 218 | |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 219 | // If there is only one terminator instruction, process it. |
| 220 | if (!SecondLastOpc) { |
Matheus Almeida | 6de62d3 | 2013-10-01 12:53:00 +0000 | [diff] [blame] | 221 | // Unconditional branch. |
Daniel Sanders | f9d8b8c | 2016-05-06 13:23:51 +0000 | [diff] [blame] | 222 | if (LastInst->isUnconditionalBranch()) { |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 223 | TBB = LastInst->getOperand(0).getMBB(); |
| 224 | return BT_Uncond; |
| 225 | } |
| 226 | |
| 227 | // Conditional branch |
| 228 | AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); |
| 229 | return BT_Cond; |
| 230 | } |
| 231 | |
| 232 | // If we reached here, there are two branches. |
| 233 | // If there are three terminators, we don't know what sort of block this is. |
Duncan P. N. Exon Smith | 6307eb5 | 2016-02-23 02:46:52 +0000 | [diff] [blame] | 234 | if (++I != REnd && isUnpredicatedTerminator(*I)) |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 235 | return BT_None; |
| 236 | |
Akira Hatanaka | 28dc83c | 2013-03-01 01:22:26 +0000 | [diff] [blame] | 237 | BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst); |
| 238 | |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 239 | // If second to last instruction is an unconditional branch, |
| 240 | // analyze it and remove the last instruction. |
Daniel Sanders | f9d8b8c | 2016-05-06 13:23:51 +0000 | [diff] [blame] | 241 | if (SecondLastInst->isUnconditionalBranch()) { |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 242 | // Return if the last instruction cannot be removed. |
| 243 | if (!AllowModify) |
| 244 | return BT_None; |
| 245 | |
| 246 | TBB = SecondLastInst->getOperand(0).getMBB(); |
| 247 | LastInst->eraseFromParent(); |
| 248 | BranchInstrs.pop_back(); |
| 249 | return BT_Uncond; |
| 250 | } |
| 251 | |
| 252 | // Conditional branch followed by an unconditional branch. |
| 253 | // The last one must be unconditional. |
Daniel Sanders | f9d8b8c | 2016-05-06 13:23:51 +0000 | [diff] [blame] | 254 | if (!LastInst->isUnconditionalBranch()) |
Akira Hatanaka | 7320b23 | 2013-03-01 01:10:17 +0000 | [diff] [blame] | 255 | return BT_None; |
| 256 | |
| 257 | AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); |
| 258 | FBB = LastInst->getOperand(0).getMBB(); |
| 259 | |
| 260 | return BT_CondUncond; |
| 261 | } |
| 262 | |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 263 | /// Return the corresponding compact (no delay slot) form of a branch. |
| 264 | unsigned MipsInstrInfo::getEquivalentCompactForm( |
| 265 | const MachineBasicBlock::iterator I) const { |
| 266 | unsigned Opcode = I->getOpcode(); |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 267 | bool canUseShortMicroMipsCTI = false; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 268 | |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 269 | if (Subtarget.inMicroMipsMode()) { |
| 270 | switch (Opcode) { |
| 271 | case Mips::BNE: |
Hrvoje Varga | 2db00ce | 2016-07-22 07:18:33 +0000 | [diff] [blame] | 272 | case Mips::BNE_MM: |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 273 | case Mips::BEQ: |
Hrvoje Varga | 2db00ce | 2016-07-22 07:18:33 +0000 | [diff] [blame] | 274 | case Mips::BEQ_MM: |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 275 | // microMIPS has NE,EQ branches that do not have delay slots provided one |
| 276 | // of the operands is zero. |
| 277 | if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) |
| 278 | canUseShortMicroMipsCTI = true; |
| 279 | break; |
| 280 | // For microMIPS the PseudoReturn and PseudoIndirectBranch are always |
| 281 | // expanded to JR_MM, so they can be replaced with JRC16_MM. |
| 282 | case Mips::JR: |
| 283 | case Mips::PseudoReturn: |
| 284 | case Mips::PseudoIndirectBranch: |
| 285 | canUseShortMicroMipsCTI = true; |
| 286 | break; |
| 287 | } |
| 288 | } |
| 289 | |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 290 | // MIPSR6 forbids both operands being the zero register. |
| 291 | if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) && |
| 292 | (I->getOperand(0).isReg() && |
| 293 | (I->getOperand(0).getReg() == Mips::ZERO || |
| 294 | I->getOperand(0).getReg() == Mips::ZERO_64)) && |
| 295 | (I->getOperand(1).isReg() && |
| 296 | (I->getOperand(1).getReg() == Mips::ZERO || |
| 297 | I->getOperand(1).getReg() == Mips::ZERO_64))) |
| 298 | return 0; |
| 299 | |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 300 | if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) { |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 301 | switch (Opcode) { |
| 302 | case Mips::B: |
| 303 | return Mips::BC; |
| 304 | case Mips::BAL: |
| 305 | return Mips::BALC; |
| 306 | case Mips::BEQ: |
Hrvoje Varga | 2db00ce | 2016-07-22 07:18:33 +0000 | [diff] [blame] | 307 | case Mips::BEQ_MM: |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 308 | if (canUseShortMicroMipsCTI) |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 309 | return Mips::BEQZC_MM; |
Simon Dardis | 03676dc | 2016-05-31 09:54:55 +0000 | [diff] [blame] | 310 | else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 311 | return 0; |
| 312 | return Mips::BEQC; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 313 | case Mips::BNE: |
Hrvoje Varga | 2db00ce | 2016-07-22 07:18:33 +0000 | [diff] [blame] | 314 | case Mips::BNE_MM: |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 315 | if (canUseShortMicroMipsCTI) |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 316 | return Mips::BNEZC_MM; |
Simon Dardis | 03676dc | 2016-05-31 09:54:55 +0000 | [diff] [blame] | 317 | else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 318 | return 0; |
| 319 | return Mips::BNEC; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 320 | case Mips::BGE: |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 321 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 322 | return 0; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 323 | return Mips::BGEC; |
| 324 | case Mips::BGEU: |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 325 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 326 | return 0; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 327 | return Mips::BGEUC; |
| 328 | case Mips::BGEZ: |
| 329 | return Mips::BGEZC; |
| 330 | case Mips::BGTZ: |
| 331 | return Mips::BGTZC; |
| 332 | case Mips::BLEZ: |
| 333 | return Mips::BLEZC; |
| 334 | case Mips::BLT: |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 335 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 336 | return 0; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 337 | return Mips::BLTC; |
| 338 | case Mips::BLTU: |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 339 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 340 | return 0; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 341 | return Mips::BLTUC; |
| 342 | case Mips::BLTZ: |
| 343 | return Mips::BLTZC; |
Simon Dardis | 68a204d | 2016-07-26 10:25:07 +0000 | [diff] [blame] | 344 | case Mips::BEQ64: |
| 345 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 346 | return 0; |
| 347 | return Mips::BEQC64; |
| 348 | case Mips::BNE64: |
| 349 | if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) |
| 350 | return 0; |
| 351 | return Mips::BNEC64; |
| 352 | case Mips::BGTZ64: |
| 353 | return Mips::BGTZC64; |
| 354 | case Mips::BGEZ64: |
| 355 | return Mips::BGEZC64; |
| 356 | case Mips::BLTZ64: |
| 357 | return Mips::BLTZC64; |
| 358 | case Mips::BLEZ64: |
| 359 | return Mips::BLEZC64; |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 360 | // For MIPSR6, the instruction 'jic' can be used for these cases. Some |
| 361 | // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'. |
| 362 | case Mips::JR: |
| 363 | case Mips::PseudoReturn: |
| 364 | case Mips::PseudoIndirectBranch: |
| 365 | if (canUseShortMicroMipsCTI) |
| 366 | return Mips::JRC16_MM; |
| 367 | return Mips::JIC; |
| 368 | case Mips::JALRPseudo: |
| 369 | return Mips::JIALC; |
| 370 | case Mips::JR64: |
| 371 | case Mips::PseudoReturn64: |
| 372 | case Mips::PseudoIndirectBranch64: |
| 373 | return Mips::JIC64; |
| 374 | case Mips::JALR64Pseudo: |
| 375 | return Mips::JIALC64; |
Simon Dardis | 669d8dd | 2016-05-18 10:38:01 +0000 | [diff] [blame] | 376 | default: |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 377 | return 0; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | /// Predicate for distingushing between control transfer instructions and all |
| 385 | /// other instructions for handling forbidden slots. Consider inline assembly |
| 386 | /// as unsafe as well. |
| 387 | bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const { |
| 388 | if (MI.isInlineAsm()) |
| 389 | return false; |
| 390 | |
| 391 | return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; |
| 392 | |
| 393 | } |
| 394 | |
| 395 | /// Predicate for distingushing instructions that have forbidden slots. |
| 396 | bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const { |
| 397 | return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; |
| 398 | } |
| 399 | |
Akira Hatanaka | acd1a7d | 2012-06-14 01:16:45 +0000 | [diff] [blame] | 400 | /// Return the number of bytes of code the specified instruction may be. |
Sjoerd Meijer | 89217f8 | 2016-07-28 16:32:22 +0000 | [diff] [blame] | 401 | unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { |
Duncan P. N. Exon Smith | 670900b | 2016-07-15 23:09:47 +0000 | [diff] [blame] | 402 | switch (MI.getOpcode()) { |
Akira Hatanaka | acd1a7d | 2012-06-14 01:16:45 +0000 | [diff] [blame] | 403 | default: |
Duncan P. N. Exon Smith | 670900b | 2016-07-15 23:09:47 +0000 | [diff] [blame] | 404 | return MI.getDesc().getSize(); |
Akira Hatanaka | acd1a7d | 2012-06-14 01:16:45 +0000 | [diff] [blame] | 405 | case TargetOpcode::INLINEASM: { // Inline Asm: Variable size. |
Duncan P. N. Exon Smith | 670900b | 2016-07-15 23:09:47 +0000 | [diff] [blame] | 406 | const MachineFunction *MF = MI.getParent()->getParent(); |
| 407 | const char *AsmStr = MI.getOperand(0).getSymbolName(); |
Akira Hatanaka | acd1a7d | 2012-06-14 01:16:45 +0000 | [diff] [blame] | 408 | return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); |
| 409 | } |
Reed Kotler | 91ae982 | 2013-10-27 21:57:36 +0000 | [diff] [blame] | 410 | case Mips::CONSTPOOL_ENTRY: |
| 411 | // If this machine instr is a constant pool entry, its size is recorded as |
| 412 | // operand #2. |
Duncan P. N. Exon Smith | 670900b | 2016-07-15 23:09:47 +0000 | [diff] [blame] | 413 | return MI.getOperand(2).getImm(); |
Akira Hatanaka | acd1a7d | 2012-06-14 01:16:45 +0000 | [diff] [blame] | 414 | } |
| 415 | } |
Akira Hatanaka | 310e26a | 2013-05-13 17:57:42 +0000 | [diff] [blame] | 416 | |
| 417 | MachineInstrBuilder |
| 418 | MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, |
| 419 | MachineBasicBlock::iterator I) const { |
| 420 | MachineInstrBuilder MIB; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 421 | |
Simon Dardis | 68a204d | 2016-07-26 10:25:07 +0000 | [diff] [blame] | 422 | // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 423 | // Pick the zero form of the branch for readable assembly and for greater |
| 424 | // branch distance in non-microMIPS mode. |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 425 | // FIXME: Certain atomic sequences on mips64 generate 32bit references to |
| 426 | // Mips::ZERO, which is incorrect. This test should be updated to use |
| 427 | // Subtarget.getABI().GetZeroReg() when those atomic sequences and others |
| 428 | // are fixed. |
| 429 | bool BranchWithZeroOperand = |
| 430 | (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() && |
| 431 | (I->getOperand(1).getReg() == Mips::ZERO || |
| 432 | I->getOperand(1).getReg() == Mips::ZERO_64)); |
| 433 | |
| 434 | if (BranchWithZeroOperand) { |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 435 | switch (NewOpc) { |
| 436 | case Mips::BEQC: |
| 437 | NewOpc = Mips::BEQZC; |
| 438 | break; |
| 439 | case Mips::BNEC: |
| 440 | NewOpc = Mips::BNEZC; |
| 441 | break; |
| 442 | case Mips::BGEC: |
| 443 | NewOpc = Mips::BGEZC; |
| 444 | break; |
| 445 | case Mips::BLTC: |
| 446 | NewOpc = Mips::BLTZC; |
| 447 | break; |
Simon Dardis | 68a204d | 2016-07-26 10:25:07 +0000 | [diff] [blame] | 448 | case Mips::BEQC64: |
| 449 | NewOpc = Mips::BEQZC64; |
| 450 | break; |
| 451 | case Mips::BNEC64: |
| 452 | NewOpc = Mips::BNEZC64; |
| 453 | break; |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
Akira Hatanaka | 310e26a | 2013-05-13 17:57:42 +0000 | [diff] [blame] | 457 | MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); |
| 458 | |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 459 | // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an |
| 460 | // immediate 0 as an operand and requires the removal of it's %RA<imp-def> |
| 461 | // implicit operand as copying the implicit operations of the instructio we're |
| 462 | // looking at will give us the correct flags. |
| 463 | if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || |
| 464 | NewOpc == Mips::JIALC64) { |
| 465 | |
| 466 | if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64) |
| 467 | MIB->RemoveOperand(0); |
| 468 | |
| 469 | for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 470 | MIB.addOperand(I->getOperand(J)); |
Simon Dardis | d9d41f5 | 2016-04-05 12:50:29 +0000 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | MIB.addImm(0); |
| 474 | |
| 475 | } else if (BranchWithZeroOperand) { |
| 476 | // For MIPSR6 and microMIPS branches with an explicit zero operand, copy |
| 477 | // everything after the zero. |
| 478 | MIB.addOperand(I->getOperand(0)); |
| 479 | |
| 480 | for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) { |
| 481 | MIB.addOperand(I->getOperand(J)); |
| 482 | } |
| 483 | } else { |
| 484 | // All other cases copy all other operands. |
| 485 | for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { |
| 486 | MIB.addOperand(I->getOperand(J)); |
| 487 | } |
| 488 | } |
| 489 | |
| 490 | MIB.copyImplicitOps(*I); |
Akira Hatanaka | 310e26a | 2013-05-13 17:57:42 +0000 | [diff] [blame] | 491 | |
| 492 | MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); |
| 493 | return MIB; |
| 494 | } |