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gerrit-public.fairphone.software / toolchain / llvm-project / a2cdbce6615bd083cc48237135d78ebbefde0b7a / . / llvm / lib / Target / PowerPC / PPCInstrVSX.td
blob: d91cdb8384e71d3853dfd01a9532b93f69b24144 [file] [log] [blame]
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the VSX extension to the PowerPC instruction set.
11//
12//===----------------------------------------------------------------------===//
13
Bill Schmidtfe723b92015-04-27 19:57:34 +0000[diff] [blame]14// *********************************** NOTE ***********************************
15// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
16// ** which VMX and VSX instructions are lane-sensitive and which are not. **
17// ** A lane-sensitive instruction relies, implicitly or explicitly, on **
18// ** whether lanes are numbered from left to right. An instruction like **
19// ** VADDFP is not lane-sensitive, because each lane of the result vector **
20// ** relies only on the corresponding lane of the source vectors. However, **
21// ** an instruction like VMULESB is lane-sensitive, because "even" and **
22// ** "odd" lanes are different for big-endian and little-endian numbering. **
23// ** **
24// ** When adding new VMX and VSX instructions, please consider whether they **
25// ** are lane-sensitive. If so, they must be added to a switch statement **
26// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). **
27// ****************************************************************************
28
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]29def PPCRegVSRCAsmOperand : AsmOperandClass {
30 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber";
31}
32def vsrc : RegisterOperand<VSRC> {
33 let ParserMatchClass = PPCRegVSRCAsmOperand;
34}
35
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]36def PPCRegVSFRCAsmOperand : AsmOperandClass {
37 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber";
38}
39def vsfrc : RegisterOperand<VSFRC> {
40 let ParserMatchClass = PPCRegVSFRCAsmOperand;
41}
42
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]43def PPCRegVSSRCAsmOperand : AsmOperandClass {
44 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber";
45}
46def vssrc : RegisterOperand<VSSRC> {
47 let ParserMatchClass = PPCRegVSSRCAsmOperand;
48}
49
Bill Schmidtfae5d712014-12-09 16:35:51 +0000[diff] [blame]50// Little-endian-specific nodes.
51def SDT_PPClxvd2x : SDTypeProfile<1, 1, [
52 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
53]>;
54def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [
55 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
56]>;
57def SDT_PPCxxswapd : SDTypeProfile<1, 1, [
58 SDTCisSameAs<0, 1>
59]>;
60
61def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,
62 [SDNPHasChain, SDNPMayLoad]>;
63def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x,
64 [SDNPHasChain, SDNPMayStore]>;
65def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>;
Nemanja Ivanovicc38b5312015-04-11 10:40:42 +0000[diff] [blame]66def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
67def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>;
68def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>;
Bill Schmidtfae5d712014-12-09 16:35:51 +0000[diff] [blame]69
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]70multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, dag OOL, dag IOL,
71 string asmbase, string asmstr, InstrItinClass itin,
72 list<dag> pattern> {
73 let BaseName = asmbase in {
74 def NAME : XX3Form_Rc<opcode, xo, OOL, IOL,
75 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
76 pattern>;
77 let Defs = [CR6] in
78 def o : XX3Form_Rc<opcode, xo, OOL, IOL,
79 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
80 []>, isDOT;
81 }
82}
83
Eric Christopher1b8e7632014-05-22 01:07:24 +0000[diff] [blame]84def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
Bill Schmidtfae5d712014-12-09 16:35:51 +0000[diff] [blame]85def IsLittleEndian : Predicate<"PPCSubTarget->isLittleEndian()">;
86def IsBigEndian : Predicate<"!PPCSubTarget->isLittleEndian()">;
87
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]88let Predicates = [HasVSX] in {
89let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
Craig Topperc50d64b2014-11-26 00:46:26 +0000[diff] [blame]90let hasSideEffects = 0 in { // VSX instructions don't have side effects.
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]91let Uses = [RM] in {
92
93 // Load indexed instructions
Hal Finkel6a778fb2015-03-11 23:28:38 +0000[diff] [blame]94 let mayLoad = 1 in {
Bill Schmidtcb34fd02014-10-09 17:51:35 +0000[diff] [blame]95 def LXSDX : XX1Form<31, 588,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]96 (outs vsfrc:$XT), (ins memrr:$src),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]97 "lxsdx $XT, $src", IIC_LdStLFD,
98 [(set f64:$XT, (load xoaddr:$src))]>;
99
Bill Schmidtcb34fd02014-10-09 17:51:35 +0000[diff] [blame]100 def LXVD2X : XX1Form<31, 844,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]101 (outs vsrc:$XT), (ins memrr:$src),
102 "lxvd2x $XT, $src", IIC_LdStLFD,
Bill Schmidt72954782014-11-12 04:19:40 +0000[diff] [blame]103 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]104
Bill Schmidtcb34fd02014-10-09 17:51:35 +0000[diff] [blame]105 def LXVDSX : XX1Form<31, 332,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]106 (outs vsrc:$XT), (ins memrr:$src),
107 "lxvdsx $XT, $src", IIC_LdStLFD, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]108
Bill Schmidtcb34fd02014-10-09 17:51:35 +0000[diff] [blame]109 def LXVW4X : XX1Form<31, 780,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]110 (outs vsrc:$XT), (ins memrr:$src),
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]111 "lxvw4x $XT, $src", IIC_LdStLFD,
Bill Schmidt72954782014-11-12 04:19:40 +0000[diff] [blame]112 [(set v4i32:$XT, (int_ppc_vsx_lxvw4x xoaddr:$src))]>;
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]113 } // mayLoad
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]114
115 // Store indexed instructions
116 let mayStore = 1 in {
117 def STXSDX : XX1Form<31, 716,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]118 (outs), (ins vsfrc:$XT, memrr:$dst),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]119 "stxsdx $XT, $dst", IIC_LdStSTFD,
120 [(store f64:$XT, xoaddr:$dst)]>;
121
122 def STXVD2X : XX1Form<31, 972,
123 (outs), (ins vsrc:$XT, memrr:$dst),
124 "stxvd2x $XT, $dst", IIC_LdStSTFD,
Hal Finkele3d2b202015-02-01 19:07:41 +0000[diff] [blame]125 [(store v2f64:$XT, xoaddr:$dst)]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]126
127 def STXVW4X : XX1Form<31, 908,
128 (outs), (ins vsrc:$XT, memrr:$dst),
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]129 "stxvw4x $XT, $dst", IIC_LdStSTFD,
Hal Finkele3d2b202015-02-01 19:07:41 +0000[diff] [blame]130 [(store v4i32:$XT, xoaddr:$dst)]>;
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]131
132 } // mayStore
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]133
134 // Add/Mul Instructions
135 let isCommutable = 1 in {
136 def XSADDDP : XX3Form<60, 32,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]137 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]138 "xsadddp $XT, $XA, $XB", IIC_VecFP,
139 [(set f64:$XT, (fadd f64:$XA, f64:$XB))]>;
140 def XSMULDP : XX3Form<60, 48,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]141 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]142 "xsmuldp $XT, $XA, $XB", IIC_VecFP,
143 [(set f64:$XT, (fmul f64:$XA, f64:$XB))]>;
144
145 def XVADDDP : XX3Form<60, 96,
146 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
147 "xvadddp $XT, $XA, $XB", IIC_VecFP,
148 [(set v2f64:$XT, (fadd v2f64:$XA, v2f64:$XB))]>;
149
150 def XVADDSP : XX3Form<60, 64,
151 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
152 "xvaddsp $XT, $XA, $XB", IIC_VecFP,
153 [(set v4f32:$XT, (fadd v4f32:$XA, v4f32:$XB))]>;
154
155 def XVMULDP : XX3Form<60, 112,
156 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
157 "xvmuldp $XT, $XA, $XB", IIC_VecFP,
158 [(set v2f64:$XT, (fmul v2f64:$XA, v2f64:$XB))]>;
159
160 def XVMULSP : XX3Form<60, 80,
161 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
162 "xvmulsp $XT, $XA, $XB", IIC_VecFP,
163 [(set v4f32:$XT, (fmul v4f32:$XA, v4f32:$XB))]>;
164 }
165
166 // Subtract Instructions
167 def XSSUBDP : XX3Form<60, 40,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]168 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]169 "xssubdp $XT, $XA, $XB", IIC_VecFP,
170 [(set f64:$XT, (fsub f64:$XA, f64:$XB))]>;
171
172 def XVSUBDP : XX3Form<60, 104,
173 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
174 "xvsubdp $XT, $XA, $XB", IIC_VecFP,
175 [(set v2f64:$XT, (fsub v2f64:$XA, v2f64:$XB))]>;
176 def XVSUBSP : XX3Form<60, 72,
177 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
178 "xvsubsp $XT, $XA, $XB", IIC_VecFP,
179 [(set v4f32:$XT, (fsub v4f32:$XA, v4f32:$XB))]>;
180
181 // FMA Instructions
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]182 let BaseName = "XSMADDADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]183 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]184 def XSMADDADP : XX3Form<60, 33,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]185 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]186 "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
187 [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]188 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
189 AltVSXFMARel;
190 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]191 def XSMADDMDP : XX3Form<60, 41,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]192 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]193 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]194 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
195 AltVSXFMARel;
196 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]197
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]198 let BaseName = "XSMSUBADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]199 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]200 def XSMSUBADP : XX3Form<60, 49,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]201 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]202 "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
203 [(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]204 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
205 AltVSXFMARel;
206 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]207 def XSMSUBMDP : XX3Form<60, 57,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]208 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]209 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]210 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
211 AltVSXFMARel;
212 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]213
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]214 let BaseName = "XSNMADDADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]215 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]216 def XSNMADDADP : XX3Form<60, 161,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]217 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]218 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
219 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]220 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
221 AltVSXFMARel;
222 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]223 def XSNMADDMDP : XX3Form<60, 169,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]224 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]225 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]226 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
227 AltVSXFMARel;
228 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]229
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]230 let BaseName = "XSNMSUBADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]231 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]232 def XSNMSUBADP : XX3Form<60, 177,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]233 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]234 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
235 [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]236 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
237 AltVSXFMARel;
238 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]239 def XSNMSUBMDP : XX3Form<60, 185,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]240 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]241 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]242 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
243 AltVSXFMARel;
244 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]245
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]246 let BaseName = "XVMADDADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]247 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]248 def XVMADDADP : XX3Form<60, 97,
249 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
250 "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
251 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]252 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
253 AltVSXFMARel;
254 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]255 def XVMADDMDP : XX3Form<60, 105,
256 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
257 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]258 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
259 AltVSXFMARel;
260 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]261
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]262 let BaseName = "XVMADDASP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]263 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]264 def XVMADDASP : XX3Form<60, 65,
265 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
266 "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
267 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]268 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
269 AltVSXFMARel;
270 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]271 def XVMADDMSP : XX3Form<60, 73,
272 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
273 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]274 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
275 AltVSXFMARel;
276 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]277
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]278 let BaseName = "XVMSUBADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]279 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]280 def XVMSUBADP : XX3Form<60, 113,
281 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
282 "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
283 [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]284 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
285 AltVSXFMARel;
286 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]287 def XVMSUBMDP : XX3Form<60, 121,
288 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
289 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]290 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
291 AltVSXFMARel;
292 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]293
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]294 let BaseName = "XVMSUBASP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]295 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]296 def XVMSUBASP : XX3Form<60, 81,
297 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
298 "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
299 [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]300 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
301 AltVSXFMARel;
302 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]303 def XVMSUBMSP : XX3Form<60, 89,
304 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
305 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]306 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
307 AltVSXFMARel;
308 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]309
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]310 let BaseName = "XVNMADDADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]311 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]312 def XVNMADDADP : XX3Form<60, 225,
313 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
314 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
315 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]316 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
317 AltVSXFMARel;
318 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]319 def XVNMADDMDP : XX3Form<60, 233,
320 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
321 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]322 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
323 AltVSXFMARel;
324 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]325
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]326 let BaseName = "XVNMADDASP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]327 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]328 def XVNMADDASP : XX3Form<60, 193,
329 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
330 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
331 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]332 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
333 AltVSXFMARel;
334 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]335 def XVNMADDMSP : XX3Form<60, 201,
336 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
337 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]338 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
339 AltVSXFMARel;
340 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]341
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]342 let BaseName = "XVNMSUBADP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]343 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]344 def XVNMSUBADP : XX3Form<60, 241,
345 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
346 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
347 [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]348 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
349 AltVSXFMARel;
350 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]351 def XVNMSUBMDP : XX3Form<60, 249,
352 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
353 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]354 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
355 AltVSXFMARel;
356 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]357
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]358 let BaseName = "XVNMSUBASP" in {
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]359 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]360 def XVNMSUBASP : XX3Form<60, 209,
361 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
362 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
363 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]364 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
365 AltVSXFMARel;
366 let IsVSXFMAAlt = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]367 def XVNMSUBMSP : XX3Form<60, 217,
368 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
369 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
Hal Finkel25e04542014-03-25 18:55:11 +0000[diff] [blame]370 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
371 AltVSXFMARel;
372 }
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]373
374 // Division Instructions
375 def XSDIVDP : XX3Form<60, 56,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]376 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]377 "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]378 [(set f64:$XT, (fdiv f64:$XA, f64:$XB))]>;
379 def XSSQRTDP : XX2Form<60, 75,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]380 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]381 "xssqrtdp $XT, $XB", IIC_FPSqrtD,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]382 [(set f64:$XT, (fsqrt f64:$XB))]>;
383
384 def XSREDP : XX2Form<60, 90,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]385 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]386 "xsredp $XT, $XB", IIC_VecFP,
387 [(set f64:$XT, (PPCfre f64:$XB))]>;
388 def XSRSQRTEDP : XX2Form<60, 74,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]389 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]390 "xsrsqrtedp $XT, $XB", IIC_VecFP,
391 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
392
393 def XSTDIVDP : XX3Form_1<60, 61,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]394 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]395 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]396 def XSTSQRTDP : XX2Form_1<60, 106,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]397 (outs crrc:$crD), (ins vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]398 "xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]399
400 def XVDIVDP : XX3Form<60, 120,
401 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]402 "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]403 [(set v2f64:$XT, (fdiv v2f64:$XA, v2f64:$XB))]>;
404 def XVDIVSP : XX3Form<60, 88,
405 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]406 "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]407 [(set v4f32:$XT, (fdiv v4f32:$XA, v4f32:$XB))]>;
408
409 def XVSQRTDP : XX2Form<60, 203,
410 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]411 "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]412 [(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
413 def XVSQRTSP : XX2Form<60, 139,
414 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]415 "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]416 [(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
417
418 def XVTDIVDP : XX3Form_1<60, 125,
419 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]420 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]421 def XVTDIVSP : XX3Form_1<60, 93,
422 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]423 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]424
425 def XVTSQRTDP : XX2Form_1<60, 234,
426 (outs crrc:$crD), (ins vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]427 "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]428 def XVTSQRTSP : XX2Form_1<60, 170,
429 (outs crrc:$crD), (ins vsrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]430 "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]431
432 def XVREDP : XX2Form<60, 218,
433 (outs vsrc:$XT), (ins vsrc:$XB),
434 "xvredp $XT, $XB", IIC_VecFP,
435 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>;
436 def XVRESP : XX2Form<60, 154,
437 (outs vsrc:$XT), (ins vsrc:$XB),
438 "xvresp $XT, $XB", IIC_VecFP,
439 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>;
440
441 def XVRSQRTEDP : XX2Form<60, 202,
442 (outs vsrc:$XT), (ins vsrc:$XB),
443 "xvrsqrtedp $XT, $XB", IIC_VecFP,
444 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>;
445 def XVRSQRTESP : XX2Form<60, 138,
446 (outs vsrc:$XT), (ins vsrc:$XB),
447 "xvrsqrtesp $XT, $XB", IIC_VecFP,
448 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>;
449
450 // Compare Instructions
451 def XSCMPODP : XX3Form_1<60, 43,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]452 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]453 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]454 def XSCMPUDP : XX3Form_1<60, 35,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]455 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkele8fba982014-03-29 13:20:31 +0000[diff] [blame]456 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]457
458 defm XVCMPEQDP : XX3Form_Rcr<60, 99,
459 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]460 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
461 [(set v2i64:$XT,
462 (int_ppc_vsx_xvcmpeqdp v2f64:$XA, v2f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]463 defm XVCMPEQSP : XX3Form_Rcr<60, 67,
464 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]465 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare,
466 [(set v4i32:$XT,
467 (int_ppc_vsx_xvcmpeqsp v4f32:$XA, v4f32:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]468 defm XVCMPGEDP : XX3Form_Rcr<60, 115,
469 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]470 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare,
471 [(set v2i64:$XT,
472 (int_ppc_vsx_xvcmpgedp v2f64:$XA, v2f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]473 defm XVCMPGESP : XX3Form_Rcr<60, 83,
474 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]475 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare,
476 [(set v4i32:$XT,
477 (int_ppc_vsx_xvcmpgesp v4f32:$XA, v4f32:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]478 defm XVCMPGTDP : XX3Form_Rcr<60, 107,
479 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]480 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare,
481 [(set v2i64:$XT,
482 (int_ppc_vsx_xvcmpgtdp v2f64:$XA, v2f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]483 defm XVCMPGTSP : XX3Form_Rcr<60, 75,
484 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Nemanja Ivanovicf502a422015-06-26 19:26:53 +0000[diff] [blame]485 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare,
486 [(set v4i32:$XT,
487 (int_ppc_vsx_xvcmpgtsp v4f32:$XA, v4f32:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]488
489 // Move Instructions
490 def XSABSDP : XX2Form<60, 345,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]491 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]492 "xsabsdp $XT, $XB", IIC_VecFP,
493 [(set f64:$XT, (fabs f64:$XB))]>;
494 def XSNABSDP : XX2Form<60, 361,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]495 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]496 "xsnabsdp $XT, $XB", IIC_VecFP,
497 [(set f64:$XT, (fneg (fabs f64:$XB)))]>;
498 def XSNEGDP : XX2Form<60, 377,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]499 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]500 "xsnegdp $XT, $XB", IIC_VecFP,
501 [(set f64:$XT, (fneg f64:$XB))]>;
502 def XSCPSGNDP : XX3Form<60, 176,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]503 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]504 "xscpsgndp $XT, $XA, $XB", IIC_VecFP,
505 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>;
506
507 def XVABSDP : XX2Form<60, 473,
508 (outs vsrc:$XT), (ins vsrc:$XB),
509 "xvabsdp $XT, $XB", IIC_VecFP,
510 [(set v2f64:$XT, (fabs v2f64:$XB))]>;
511
512 def XVABSSP : XX2Form<60, 409,
513 (outs vsrc:$XT), (ins vsrc:$XB),
514 "xvabssp $XT, $XB", IIC_VecFP,
515 [(set v4f32:$XT, (fabs v4f32:$XB))]>;
516
517 def XVCPSGNDP : XX3Form<60, 240,
518 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
519 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP,
520 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>;
521 def XVCPSGNSP : XX3Form<60, 208,
522 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
523 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP,
524 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>;
525
526 def XVNABSDP : XX2Form<60, 489,
527 (outs vsrc:$XT), (ins vsrc:$XB),
528 "xvnabsdp $XT, $XB", IIC_VecFP,
529 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>;
530 def XVNABSSP : XX2Form<60, 425,
531 (outs vsrc:$XT), (ins vsrc:$XB),
532 "xvnabssp $XT, $XB", IIC_VecFP,
533 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>;
534
535 def XVNEGDP : XX2Form<60, 505,
536 (outs vsrc:$XT), (ins vsrc:$XB),
537 "xvnegdp $XT, $XB", IIC_VecFP,
538 [(set v2f64:$XT, (fneg v2f64:$XB))]>;
539 def XVNEGSP : XX2Form<60, 441,
540 (outs vsrc:$XT), (ins vsrc:$XB),
541 "xvnegsp $XT, $XB", IIC_VecFP,
542 [(set v4f32:$XT, (fneg v4f32:$XB))]>;
543
544 // Conversion Instructions
545 def XSCVDPSP : XX2Form<60, 265,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]546 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]547 "xscvdpsp $XT, $XB", IIC_VecFP, []>;
548 def XSCVDPSXDS : XX2Form<60, 344,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]549 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]550 "xscvdpsxds $XT, $XB", IIC_VecFP,
551 [(set f64:$XT, (PPCfctidz f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]552 def XSCVDPSXWS : XX2Form<60, 88,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]553 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]554 "xscvdpsxws $XT, $XB", IIC_VecFP,
555 [(set f64:$XT, (PPCfctiwz f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]556 def XSCVDPUXDS : XX2Form<60, 328,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]557 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]558 "xscvdpuxds $XT, $XB", IIC_VecFP,
559 [(set f64:$XT, (PPCfctiduz f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]560 def XSCVDPUXWS : XX2Form<60, 72,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]561 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]562 "xscvdpuxws $XT, $XB", IIC_VecFP,
563 [(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]564 def XSCVSPDP : XX2Form<60, 329,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]565 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]566 "xscvspdp $XT, $XB", IIC_VecFP, []>;
567 def XSCVSXDDP : XX2Form<60, 376,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]568 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]569 "xscvsxddp $XT, $XB", IIC_VecFP,
570 [(set f64:$XT, (PPCfcfid f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]571 def XSCVUXDDP : XX2Form<60, 360,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]572 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel4a912252014-03-23 05:35:00 +0000[diff] [blame]573 "xscvuxddp $XT, $XB", IIC_VecFP,
574 [(set f64:$XT, (PPCfcfidu f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]575
576 def XVCVDPSP : XX2Form<60, 393,
577 (outs vsrc:$XT), (ins vsrc:$XB),
578 "xvcvdpsp $XT, $XB", IIC_VecFP, []>;
579 def XVCVDPSXDS : XX2Form<60, 472,
580 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkel7279f4b2014-03-26 19:13:54 +0000[diff] [blame]581 "xvcvdpsxds $XT, $XB", IIC_VecFP,
582 [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]583 def XVCVDPSXWS : XX2Form<60, 216,
584 (outs vsrc:$XT), (ins vsrc:$XB),
585 "xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
586 def XVCVDPUXDS : XX2Form<60, 456,
587 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkel7279f4b2014-03-26 19:13:54 +0000[diff] [blame]588 "xvcvdpuxds $XT, $XB", IIC_VecFP,
589 [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]590 def XVCVDPUXWS : XX2Form<60, 200,
591 (outs vsrc:$XT), (ins vsrc:$XB),
592 "xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
593
594 def XVCVSPDP : XX2Form<60, 457,
595 (outs vsrc:$XT), (ins vsrc:$XB),
596 "xvcvspdp $XT, $XB", IIC_VecFP, []>;
597 def XVCVSPSXDS : XX2Form<60, 408,
598 (outs vsrc:$XT), (ins vsrc:$XB),
599 "xvcvspsxds $XT, $XB", IIC_VecFP, []>;
600 def XVCVSPSXWS : XX2Form<60, 152,
601 (outs vsrc:$XT), (ins vsrc:$XB),
602 "xvcvspsxws $XT, $XB", IIC_VecFP, []>;
603 def XVCVSPUXDS : XX2Form<60, 392,
604 (outs vsrc:$XT), (ins vsrc:$XB),
605 "xvcvspuxds $XT, $XB", IIC_VecFP, []>;
606 def XVCVSPUXWS : XX2Form<60, 136,
607 (outs vsrc:$XT), (ins vsrc:$XB),
608 "xvcvspuxws $XT, $XB", IIC_VecFP, []>;
609 def XVCVSXDDP : XX2Form<60, 504,
610 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkel7279f4b2014-03-26 19:13:54 +0000[diff] [blame]611 "xvcvsxddp $XT, $XB", IIC_VecFP,
612 [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]613 def XVCVSXDSP : XX2Form<60, 440,
614 (outs vsrc:$XT), (ins vsrc:$XB),
615 "xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
616 def XVCVSXWDP : XX2Form<60, 248,
617 (outs vsrc:$XT), (ins vsrc:$XB),
618 "xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
619 def XVCVSXWSP : XX2Form<60, 184,
620 (outs vsrc:$XT), (ins vsrc:$XB),
621 "xvcvsxwsp $XT, $XB", IIC_VecFP, []>;
622 def XVCVUXDDP : XX2Form<60, 488,
623 (outs vsrc:$XT), (ins vsrc:$XB),
Hal Finkel7279f4b2014-03-26 19:13:54 +0000[diff] [blame]624 "xvcvuxddp $XT, $XB", IIC_VecFP,
625 [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]626 def XVCVUXDSP : XX2Form<60, 424,
627 (outs vsrc:$XT), (ins vsrc:$XB),
628 "xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
629 def XVCVUXWDP : XX2Form<60, 232,
630 (outs vsrc:$XT), (ins vsrc:$XB),
631 "xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
632 def XVCVUXWSP : XX2Form<60, 168,
633 (outs vsrc:$XT), (ins vsrc:$XB),
634 "xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
635
636 // Rounding Instructions
637 def XSRDPI : XX2Form<60, 73,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]638 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]639 "xsrdpi $XT, $XB", IIC_VecFP,
640 [(set f64:$XT, (frnd f64:$XB))]>;
641 def XSRDPIC : XX2Form<60, 107,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]642 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]643 "xsrdpic $XT, $XB", IIC_VecFP,
644 [(set f64:$XT, (fnearbyint f64:$XB))]>;
645 def XSRDPIM : XX2Form<60, 121,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]646 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]647 "xsrdpim $XT, $XB", IIC_VecFP,
648 [(set f64:$XT, (ffloor f64:$XB))]>;
649 def XSRDPIP : XX2Form<60, 105,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]650 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]651 "xsrdpip $XT, $XB", IIC_VecFP,
652 [(set f64:$XT, (fceil f64:$XB))]>;
653 def XSRDPIZ : XX2Form<60, 89,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]654 (outs vsfrc:$XT), (ins vsfrc:$XB),
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]655 "xsrdpiz $XT, $XB", IIC_VecFP,
656 [(set f64:$XT, (ftrunc f64:$XB))]>;
657
658 def XVRDPI : XX2Form<60, 201,
659 (outs vsrc:$XT), (ins vsrc:$XB),
660 "xvrdpi $XT, $XB", IIC_VecFP,
661 [(set v2f64:$XT, (frnd v2f64:$XB))]>;
662 def XVRDPIC : XX2Form<60, 235,
663 (outs vsrc:$XT), (ins vsrc:$XB),
664 "xvrdpic $XT, $XB", IIC_VecFP,
665 [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>;
666 def XVRDPIM : XX2Form<60, 249,
667 (outs vsrc:$XT), (ins vsrc:$XB),
668 "xvrdpim $XT, $XB", IIC_VecFP,
669 [(set v2f64:$XT, (ffloor v2f64:$XB))]>;
670 def XVRDPIP : XX2Form<60, 233,
671 (outs vsrc:$XT), (ins vsrc:$XB),
672 "xvrdpip $XT, $XB", IIC_VecFP,
673 [(set v2f64:$XT, (fceil v2f64:$XB))]>;
674 def XVRDPIZ : XX2Form<60, 217,
675 (outs vsrc:$XT), (ins vsrc:$XB),
676 "xvrdpiz $XT, $XB", IIC_VecFP,
677 [(set v2f64:$XT, (ftrunc v2f64:$XB))]>;
678
679 def XVRSPI : XX2Form<60, 137,
680 (outs vsrc:$XT), (ins vsrc:$XB),
681 "xvrspi $XT, $XB", IIC_VecFP,
682 [(set v4f32:$XT, (frnd v4f32:$XB))]>;
683 def XVRSPIC : XX2Form<60, 171,
684 (outs vsrc:$XT), (ins vsrc:$XB),
685 "xvrspic $XT, $XB", IIC_VecFP,
686 [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>;
687 def XVRSPIM : XX2Form<60, 185,
688 (outs vsrc:$XT), (ins vsrc:$XB),
689 "xvrspim $XT, $XB", IIC_VecFP,
690 [(set v4f32:$XT, (ffloor v4f32:$XB))]>;
691 def XVRSPIP : XX2Form<60, 169,
692 (outs vsrc:$XT), (ins vsrc:$XB),
693 "xvrspip $XT, $XB", IIC_VecFP,
694 [(set v4f32:$XT, (fceil v4f32:$XB))]>;
695 def XVRSPIZ : XX2Form<60, 153,
696 (outs vsrc:$XT), (ins vsrc:$XB),
697 "xvrspiz $XT, $XB", IIC_VecFP,
698 [(set v4f32:$XT, (ftrunc v4f32:$XB))]>;
699
700 // Max/Min Instructions
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]701 let isCommutable = 1 in {
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]702 def XSMAXDP : XX3Form<60, 160,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]703 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]704 "xsmaxdp $XT, $XA, $XB", IIC_VecFP,
705 [(set vsfrc:$XT,
706 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]707 def XSMINDP : XX3Form<60, 168,
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]708 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]709 "xsmindp $XT, $XA, $XB", IIC_VecFP,
710 [(set vsfrc:$XT,
711 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]712
713 def XVMAXDP : XX3Form<60, 224,
714 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]715 "xvmaxdp $XT, $XA, $XB", IIC_VecFP,
716 [(set vsrc:$XT,
717 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]718 def XVMINDP : XX3Form<60, 232,
719 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]720 "xvmindp $XT, $XA, $XB", IIC_VecFP,
721 [(set vsrc:$XT,
722 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]723
724 def XVMAXSP : XX3Form<60, 192,
725 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]726 "xvmaxsp $XT, $XA, $XB", IIC_VecFP,
727 [(set vsrc:$XT,
728 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]729 def XVMINSP : XX3Form<60, 200,
730 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Bill Schmidt1ca69fa2014-10-31 19:19:07 +0000[diff] [blame]731 "xvminsp $XT, $XA, $XB", IIC_VecFP,
732 [(set vsrc:$XT,
733 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>;
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]734 } // isCommutable
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]735} // Uses = [RM]
736
737 // Logical Instructions
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]738 let isCommutable = 1 in
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]739 def XXLAND : XX3Form<60, 130,
740 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkelbd4de9d2014-03-26 04:55:40 +0000[diff] [blame]741 "xxland $XT, $XA, $XB", IIC_VecGeneral,
742 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]743 def XXLANDC : XX3Form<60, 138,
744 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkelbd4de9d2014-03-26 04:55:40 +0000[diff] [blame]745 "xxlandc $XT, $XA, $XB", IIC_VecGeneral,
746 [(set v4i32:$XT, (and v4i32:$XA,
747 (vnot_ppc v4i32:$XB)))]>;
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]748 let isCommutable = 1 in {
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]749 def XXLNOR : XX3Form<60, 162,
750 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkelbd4de9d2014-03-26 04:55:40 +0000[diff] [blame]751 "xxlnor $XT, $XA, $XB", IIC_VecGeneral,
752 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA,
753 v4i32:$XB)))]>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]754 def XXLOR : XX3Form<60, 146,
755 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkelbd4de9d2014-03-26 04:55:40 +0000[diff] [blame]756 "xxlor $XT, $XA, $XB", IIC_VecGeneral,
757 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>;
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]758 let isCodeGenOnly = 1 in
759 def XXLORf: XX3Form<60, 146,
760 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
761 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]762 def XXLXOR : XX3Form<60, 154,
763 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
Hal Finkelbd4de9d2014-03-26 04:55:40 +0000[diff] [blame]764 "xxlxor $XT, $XA, $XB", IIC_VecGeneral,
765 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>;
Hal Finkele01d3212014-03-24 15:07:28 +0000[diff] [blame]766 } // isCommutable
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]767
768 // Permutation Instructions
769 def XXMRGHW : XX3Form<60, 18,
770 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
771 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>;
772 def XXMRGLW : XX3Form<60, 50,
773 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
774 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
775
776 def XXPERMDI : XX3Form_2<60, 10,
777 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
778 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
779 def XXSEL : XX4Form<60, 3,
780 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
781 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
782
783 def XXSLDWI : XX3Form_2<60, 2,
784 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
785 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
786 def XXSPLTW : XX2Form_2<60, 164,
787 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
788 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
Craig Topperc50d64b2014-11-26 00:46:26 +0000[diff] [blame]789} // hasSideEffects
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]790
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]791// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
792// instruction selection into a branch sequence.
793let usesCustomInserter = 1, // Expanded after instruction selection.
794 PPC970_Single = 1 in {
795
796 def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst),
797 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
798 "#SELECT_CC_VSRC",
799 []>;
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]800 def SELECT_VSRC: Pseudo<(outs vsrc:$dst),
801 (ins crbitrc:$cond, vsrc:$T, vsrc:$F),
802 "#SELECT_VSRC",
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]803 [(set v2f64:$dst,
804 (select i1:$cond, v2f64:$T, v2f64:$F))]>;
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]805 def SELECT_CC_VSFRC: Pseudo<(outs f8rc:$dst),
806 (ins crrc:$cond, f8rc:$T, f8rc:$F,
807 i32imm:$BROPC), "#SELECT_CC_VSFRC",
808 []>;
809 def SELECT_VSFRC: Pseudo<(outs f8rc:$dst),
810 (ins crbitrc:$cond, f8rc:$T, f8rc:$F),
811 "#SELECT_VSFRC",
812 [(set f64:$dst,
813 (select i1:$cond, f64:$T, f64:$F))]>;
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]814 def SELECT_CC_VSSRC: Pseudo<(outs f4rc:$dst),
815 (ins crrc:$cond, f4rc:$T, f4rc:$F,
816 i32imm:$BROPC), "#SELECT_CC_VSSRC",
817 []>;
818 def SELECT_VSSRC: Pseudo<(outs f4rc:$dst),
819 (ins crbitrc:$cond, f4rc:$T, f4rc:$F),
820 "#SELECT_VSSRC",
821 [(set f32:$dst,
822 (select i1:$cond, f32:$T, f32:$F))]>;
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]823} // usesCustomInserter
824} // AddedComplexity
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]825
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]826def : InstAlias<"xvmovdp $XT, $XB",
827 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
828def : InstAlias<"xvmovsp $XT, $XB",
829 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
830
831def : InstAlias<"xxspltd $XT, $XB, 0",
832 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
833def : InstAlias<"xxspltd $XT, $XB, 1",
834 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
835def : InstAlias<"xxmrghd $XT, $XA, $XB",
836 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
837def : InstAlias<"xxmrgld $XT, $XA, $XB",
838 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
839def : InstAlias<"xxswapd $XT, $XB",
840 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
841
842let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
Bill Schmidt10f6eb92014-12-09 16:43:32 +0000[diff] [blame]843
844let Predicates = [IsBigEndian] in {
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]845def : Pat<(v2f64 (scalar_to_vector f64:$A)),
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]846 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]847
848def : Pat<(f64 (vector_extract v2f64:$S, 0)),
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]849 (f64 (EXTRACT_SUBREG $S, sub_64))>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]850def : Pat<(f64 (vector_extract v2f64:$S, 1)),
Hal Finkel19be5062014-03-29 05:29:01 +0000[diff] [blame]851 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
Bill Schmidt10f6eb92014-12-09 16:43:32 +0000[diff] [blame]852}
853
854let Predicates = [IsLittleEndian] in {
855def : Pat<(v2f64 (scalar_to_vector f64:$A)),
856 (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64),
857 (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>;
858
859def : Pat<(f64 (vector_extract v2f64:$S, 0)),
860 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
861def : Pat<(f64 (vector_extract v2f64:$S, 1)),
862 (f64 (EXTRACT_SUBREG $S, sub_64))>;
863}
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]864
865// Additional fnmsub patterns: -a*c + b == -(a*c - b)
866def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
867 (XSNMSUBADP $B, $C, $A)>;
868def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
869 (XSNMSUBADP $B, $C, $A)>;
870
871def : Pat<(fma (fneg v2f64:$A), v2f64:$C, v2f64:$B),
872 (XVNMSUBADP $B, $C, $A)>;
873def : Pat<(fma v2f64:$A, (fneg v2f64:$C), v2f64:$B),
874 (XVNMSUBADP $B, $C, $A)>;
875
876def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
877 (XVNMSUBASP $B, $C, $A)>;
878def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
879 (XVNMSUBASP $B, $C, $A)>;
880
Hal Finkel9e0baa62014-04-01 19:24:27 +0000[diff] [blame]881def : Pat<(v2f64 (bitconvert v4f32:$A)),
882 (COPY_TO_REGCLASS $A, VSRC)>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]883def : Pat<(v2f64 (bitconvert v4i32:$A)),
884 (COPY_TO_REGCLASS $A, VSRC)>;
885def : Pat<(v2f64 (bitconvert v8i16:$A)),
886 (COPY_TO_REGCLASS $A, VSRC)>;
887def : Pat<(v2f64 (bitconvert v16i8:$A)),
888 (COPY_TO_REGCLASS $A, VSRC)>;
889
Hal Finkel9e0baa62014-04-01 19:24:27 +0000[diff] [blame]890def : Pat<(v4f32 (bitconvert v2f64:$A)),
891 (COPY_TO_REGCLASS $A, VRRC)>;
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]892def : Pat<(v4i32 (bitconvert v2f64:$A)),
893 (COPY_TO_REGCLASS $A, VRRC)>;
894def : Pat<(v8i16 (bitconvert v2f64:$A)),
895 (COPY_TO_REGCLASS $A, VRRC)>;
896def : Pat<(v16i8 (bitconvert v2f64:$A)),
897 (COPY_TO_REGCLASS $A, VRRC)>;
898
Hal Finkel9e0baa62014-04-01 19:24:27 +0000[diff] [blame]899def : Pat<(v2i64 (bitconvert v4f32:$A)),
900 (COPY_TO_REGCLASS $A, VSRC)>;
Hal Finkela6c8b512014-03-26 16:12:58 +0000[diff] [blame]901def : Pat<(v2i64 (bitconvert v4i32:$A)),
902 (COPY_TO_REGCLASS $A, VSRC)>;
903def : Pat<(v2i64 (bitconvert v8i16:$A)),
904 (COPY_TO_REGCLASS $A, VSRC)>;
905def : Pat<(v2i64 (bitconvert v16i8:$A)),
906 (COPY_TO_REGCLASS $A, VSRC)>;
907
Hal Finkel9e0baa62014-04-01 19:24:27 +0000[diff] [blame]908def : Pat<(v4f32 (bitconvert v2i64:$A)),
909 (COPY_TO_REGCLASS $A, VRRC)>;
Hal Finkela6c8b512014-03-26 16:12:58 +0000[diff] [blame]910def : Pat<(v4i32 (bitconvert v2i64:$A)),
911 (COPY_TO_REGCLASS $A, VRRC)>;
912def : Pat<(v8i16 (bitconvert v2i64:$A)),
913 (COPY_TO_REGCLASS $A, VRRC)>;
914def : Pat<(v16i8 (bitconvert v2i64:$A)),
915 (COPY_TO_REGCLASS $A, VRRC)>;
916
Hal Finkel9281c9a2014-03-26 18:26:30 +0000[diff] [blame]917def : Pat<(v2f64 (bitconvert v2i64:$A)),
918 (COPY_TO_REGCLASS $A, VRRC)>;
919def : Pat<(v2i64 (bitconvert v2f64:$A)),
920 (COPY_TO_REGCLASS $A, VRRC)>;
921
Kit Bartond4eb73c2015-05-05 16:10:44 +0000[diff] [blame]922def : Pat<(v2f64 (bitconvert v1i128:$A)),
923 (COPY_TO_REGCLASS $A, VRRC)>;
924def : Pat<(v1i128 (bitconvert v2f64:$A)),
925 (COPY_TO_REGCLASS $A, VRRC)>;
926
Hal Finkel5c0d1452014-03-30 13:22:59 +0000[diff] [blame]927// sign extension patterns
928// To extend "in place" from v2i32 to v2i64, we have input data like:
929// | undef | i32 | undef | i32 |
930// but xvcvsxwdp expects the input in big-Endian format:
931// | i32 | undef | i32 | undef |
932// so we need to shift everything to the left by one i32 (word) before
933// the conversion.
934def : Pat<(sext_inreg v2i64:$C, v2i32),
935 (XVCVDPSXDS (XVCVSXWDP (XXSLDWI $C, $C, 1)))>;
936def : Pat<(v2f64 (sint_to_fp (sext_inreg v2i64:$C, v2i32))),
937 (XVCVSXWDP (XXSLDWI $C, $C, 1))>;
938
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]939// Loads.
Bill Schmidt72954782014-11-12 04:19:40 +0000[diff] [blame]940def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
941def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]942def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
Bill Schmidtfae5d712014-12-09 16:35:51 +0000[diff] [blame]943def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>;
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]944
945// Stores.
Hal Finkele3d2b202015-02-01 19:07:41 +0000[diff] [blame]946def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
947 (STXVD2X $rS, xoaddr:$dst)>;
Bill Schmidt72954782014-11-12 04:19:40 +0000[diff] [blame]948def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
Hal Finkele3d2b202015-02-01 19:07:41 +0000[diff] [blame]949def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
950 (STXVW4X $rS, xoaddr:$dst)>;
Bill Schmidtfae5d712014-12-09 16:35:51 +0000[diff] [blame]951def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
952
953// Permutes.
954def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>;
955def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>;
956def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>;
957def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>;
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]958
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]959// Selects.
960def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]961 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
962def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)),
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]963 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
964def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]965 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
966def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)),
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]967 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
968def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
969 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
970def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]971 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
972def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)),
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]973 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
974def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]975 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
976def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)),
Bill Schmidt61e65232014-10-22 13:13:40 +0000[diff] [blame]977 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
978def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
979 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
980
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]981def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]982 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
983def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]984 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
985def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]986 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
987def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]988 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
989def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
990 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>;
991def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]992 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>;
993def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]994 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>;
995def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]996 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>;
997def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
Bill Schmidt9c54bbd2014-10-22 16:58:20 +0000[diff] [blame]998 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>;
999def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
1000 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
1001
Bill Schmidt76746922014-11-14 12:10:40 +0000[diff] [blame]1002// Divides.
1003def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
1004 (XVDIVSP $A, $B)>;
1005def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
1006 (XVDIVDP $A, $B)>;
1007
Nemanja Ivanovic984a3612015-07-14 17:25:20 +0000[diff] [blame]1008// Reciprocal estimate
1009def : Pat<(int_ppc_vsx_xvresp v4f32:$A),
1010 (XVRESP $A)>;
1011def : Pat<(int_ppc_vsx_xvredp v2f64:$A),
1012 (XVREDP $A)>;
1013
Nemanja Ivanovicd358b8f2015-07-05 06:03:51 +0000[diff] [blame]1014// Recip. square root estimate
1015def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
1016 (XVRSQRTESP $A)>;
1017def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
1018 (XVRSQRTEDP $A)>;
1019
Hal Finkel27774d92014-03-13 07:58:58 +0000[diff] [blame]1020} // AddedComplexity
1021} // HasVSX
1022
Kit Barton298beb52015-02-18 16:21:46 +0000[diff] [blame]1023// The following VSX instructions were introduced in Power ISA 2.07
1024/* FIXME: if the operands are v2i64, these patterns will not match.
1025 we should define new patterns or otherwise match the same patterns
1026 when the elements are larger than i32.
1027*/
1028def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
Nemanja Ivanovicc38b5312015-04-11 10:40:42 +0000[diff] [blame]1029def HasDirectMove : Predicate<"PPCSubTarget->hasDirectMove()">;
Kit Barton298beb52015-02-18 16:21:46 +0000[diff] [blame]1030let Predicates = [HasP8Vector] in {
1031let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1032 let isCommutable = 1 in {
1033 def XXLEQV : XX3Form<60, 186,
1034 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1035 "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
1036 [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
1037 def XXLNAND : XX3Form<60, 178,
1038 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1039 "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
1040 [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
Kit Barton298beb52015-02-18 16:21:46 +0000[diff] [blame]1041 v4i32:$XB)))]>;
1042 } // isCommutable
Nemanja Ivanovicd9e4b4f2015-07-10 14:25:17 +0000[diff] [blame]1043
Nemanja Ivanovic5655fb32015-07-10 12:38:08 +0000[diff] [blame]1044 def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
1045 (XXLEQV $A, $B)>;
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1046
1047 def XXLORC : XX3Form<60, 170,
1048 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
1049 "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
1050 [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
1051
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]1052 // VSX scalar loads introduced in ISA 2.07
1053 let mayLoad = 1 in {
1054 def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
1055 "lxsspx $XT, $src", IIC_LdStLFD,
1056 [(set f32:$XT, (load xoaddr:$src))]>;
1057 def LXSIWAX : XX1Form<31, 76, (outs vsfrc:$XT), (ins memrr:$src),
1058 "lxsiwax $XT, $src", IIC_LdStLFD,
1059 [(set f64:$XT, (PPClfiwax xoaddr:$src))]>;
1060 def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
1061 "lxsiwzx $XT, $src", IIC_LdStLFD,
1062 [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
1063 } // mayLoad
1064
1065 // VSX scalar stores introduced in ISA 2.07
1066 let mayStore = 1 in {
1067 def STXSSPX : XX1Form<31, 652, (outs), (ins vssrc:$XT, memrr:$dst),
1068 "stxsspx $XT, $dst", IIC_LdStSTFD,
1069 [(store f32:$XT, xoaddr:$dst)]>;
1070 def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
1071 "stxsiwx $XT, $dst", IIC_LdStSTFD,
1072 [(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
1073 } // mayStore
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1074
1075 def : Pat<(f64 (extloadf32 xoaddr:$src)),
1076 (COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>;
1077 def : Pat<(f64 (fextend f32:$src)),
1078 (COPY_TO_REGCLASS $src, VSFRC)>;
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1079
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1080 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1081 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1082 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1083 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1084 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1085 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
1086 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1087 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
1088 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
1089 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>;
1090 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1091 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>;
1092 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1093 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>;
1094 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1095 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
1096 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1097 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
1098 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame^]1099 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1100
1101 // VSX Elementary Scalar FP arithmetic (SP)
1102 let isCommutable = 1 in {
1103 def XSADDSP : XX3Form<60, 0,
1104 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1105 "xsaddsp $XT, $XA, $XB", IIC_VecFP,
1106 [(set f32:$XT, (fadd f32:$XA, f32:$XB))]>;
1107 def XSMULSP : XX3Form<60, 16,
1108 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1109 "xsmulsp $XT, $XA, $XB", IIC_VecFP,
1110 [(set f32:$XT, (fmul f32:$XA, f32:$XB))]>;
1111 } // isCommutable
1112
1113 def XSDIVSP : XX3Form<60, 24,
1114 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1115 "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
1116 [(set f32:$XT, (fdiv f32:$XA, f32:$XB))]>;
1117 def XSRESP : XX2Form<60, 26,
1118 (outs vssrc:$XT), (ins vssrc:$XB),
1119 "xsresp $XT, $XB", IIC_VecFP,
1120 [(set f32:$XT, (PPCfre f32:$XB))]>;
1121 def XSSQRTSP : XX2Form<60, 11,
1122 (outs vssrc:$XT), (ins vssrc:$XB),
1123 "xssqrtsp $XT, $XB", IIC_FPSqrtS,
1124 [(set f32:$XT, (fsqrt f32:$XB))]>;
1125 def XSRSQRTESP : XX2Form<60, 10,
1126 (outs vssrc:$XT), (ins vssrc:$XB),
1127 "xsrsqrtesp $XT, $XB", IIC_VecFP,
1128 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
1129 def XSSUBSP : XX3Form<60, 8,
1130 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
1131 "xssubsp $XT, $XA, $XB", IIC_VecFP,
1132 [(set f32:$XT, (fsub f32:$XA, f32:$XB))]>;
Nemanja Ivanovic376e1732015-05-29 17:13:25 +0000[diff] [blame]1133
1134 // FMA Instructions
1135 let BaseName = "XSMADDASP" in {
1136 let isCommutable = 1 in
1137 def XSMADDASP : XX3Form<60, 1,
1138 (outs vssrc:$XT),
1139 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1140 "xsmaddasp $XT, $XA, $XB", IIC_VecFP,
1141 [(set f32:$XT, (fma f32:$XA, f32:$XB, f32:$XTi))]>,
1142 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1143 AltVSXFMARel;
1144 let IsVSXFMAAlt = 1 in
1145 def XSMADDMSP : XX3Form<60, 9,
1146 (outs vssrc:$XT),
1147 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1148 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1149 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1150 AltVSXFMARel;
1151 }
1152
1153 let BaseName = "XSMSUBASP" in {
1154 let isCommutable = 1 in
1155 def XSMSUBASP : XX3Form<60, 17,
1156 (outs vssrc:$XT),
1157 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1158 "xsmsubasp $XT, $XA, $XB", IIC_VecFP,
1159 [(set f32:$XT, (fma f32:$XA, f32:$XB,
1160 (fneg f32:$XTi)))]>,
1161 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1162 AltVSXFMARel;
1163 let IsVSXFMAAlt = 1 in
1164 def XSMSUBMSP : XX3Form<60, 25,
1165 (outs vssrc:$XT),
1166 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1167 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1168 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1169 AltVSXFMARel;
1170 }
1171
1172 let BaseName = "XSNMADDASP" in {
1173 let isCommutable = 1 in
1174 def XSNMADDASP : XX3Form<60, 129,
1175 (outs vssrc:$XT),
1176 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1177 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
1178 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
1179 f32:$XTi)))]>,
1180 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1181 AltVSXFMARel;
1182 let IsVSXFMAAlt = 1 in
1183 def XSNMADDMSP : XX3Form<60, 137,
1184 (outs vssrc:$XT),
1185 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1186 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
1187 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1188 AltVSXFMARel;
1189 }
1190
1191 let BaseName = "XSNMSUBASP" in {
1192 let isCommutable = 1 in
1193 def XSNMSUBASP : XX3Form<60, 145,
1194 (outs vssrc:$XT),
1195 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1196 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
1197 [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
1198 (fneg f32:$XTi))))]>,
1199 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1200 AltVSXFMARel;
1201 let IsVSXFMAAlt = 1 in
1202 def XSNMSUBMSP : XX3Form<60, 153,
1203 (outs vssrc:$XT),
1204 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
1205 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
1206 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
1207 AltVSXFMARel;
1208 }
Nemanja Ivanovic1c39ca62015-08-13 17:40:44 +0000[diff] [blame]1209
1210 // Single Precision Conversions (FP <-> INT)
1211 def XSCVSXDSP : XX2Form<60, 312,
1212 (outs vssrc:$XT), (ins vsfrc:$XB),
1213 "xscvsxdsp $XT, $XB", IIC_VecFP,
1214 [(set f32:$XT, (PPCfcfids f64:$XB))]>;
1215 def XSCVUXDSP : XX2Form<60, 296,
1216 (outs vssrc:$XT), (ins vsfrc:$XB),
1217 "xscvuxdsp $XT, $XB", IIC_VecFP,
1218 [(set f32:$XT, (PPCfcfidus f64:$XB))]>;
1219
1220 // Conversions between vector and scalar single precision
1221 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
1222 "xscvdpspn $XT, $XB", IIC_VecFP, []>;
1223 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
1224 "xscvspdpn $XT, $XB", IIC_VecFP, []>;
1225
Nemanja Ivanovicf3c94b12015-05-07 18:24:05 +0000[diff] [blame]1226} // AddedComplexity = 400
Kit Barton298beb52015-02-18 16:21:46 +0000[diff] [blame]1227} // HasP8Vector
Nemanja Ivanovicc38b5312015-04-11 10:40:42 +0000[diff] [blame]1228
1229let Predicates = [HasDirectMove, HasVSX] in {
Nemanja Ivanovicf02def62015-05-21 19:32:49 +0000[diff] [blame]1230 // VSX direct move instructions
1231 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
1232 "mfvsrd $rA, $XT", IIC_VecGeneral,
1233 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1234 Requires<[In64BitMode]>;
1235 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
1236 "mfvsrwz $rA, $XT", IIC_VecGeneral,
1237 [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
1238 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
1239 "mtvsrd $XT, $rA", IIC_VecGeneral,
1240 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1241 Requires<[In64BitMode]>;
1242 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
1243 "mtvsrwa $XT, $rA", IIC_VecGeneral,
1244 [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
1245 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
1246 "mtvsrwz $XT, $rA", IIC_VecGeneral,
1247 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
Nemanja Ivanovicc38b5312015-04-11 10:40:42 +0000[diff] [blame]1248} // HasDirectMove, HasVSX
Nemanja Ivanovic1c39ca62015-08-13 17:40:44 +0000[diff] [blame]1249
1250/* Direct moves of various size entities from GPR's into VSR's. Each lines
1251 the value up into element 0 (both BE and LE). Namely, entities smaller than
1252 a doubleword are shifted left and moved for BE. For LE, they're moved, then
1253 swapped to go into the least significant element of the VSR.
1254*/
1255def Moves {
1256 dag BE_BYTE_0 = (MTVSRD
1257 (RLDICR
1258 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7));
1259 dag BE_HALF_0 = (MTVSRD
1260 (RLDICR
1261 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15));
1262 dag BE_WORD_0 = (MTVSRD
1263 (RLDICR
1264 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31));
1265 dag BE_DWORD_0 = (MTVSRD $A);
1266
1267 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32));
1268 dag LE_WORD_1 = (v2i64 (COPY_TO_REGCLASS LE_MTVSRW, VSRC));
1269 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2);
1270 dag LE_DWORD_1 = (v2i64 (COPY_TO_REGCLASS BE_DWORD_0, VSRC));
1271 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2);
1272}
1273
1274let Predicates = [IsBigEndian, HasP8Vector] in {
1275 def : Pat<(v4f32 (scalar_to_vector f32:$A)),
1276 (v4f32 (XSCVDPSPN $A))>;
1277} // IsBigEndian, HasP8Vector
1278
1279let Predicates = [IsBigEndian, HasDirectMove] in {
1280 def : Pat<(v16i8 (scalar_to_vector i32:$A)),
1281 (v16i8 (COPY_TO_REGCLASS Moves.BE_BYTE_0, VSRC))>;
1282 def : Pat<(v8i16 (scalar_to_vector i32:$A)),
1283 (v8i16 (COPY_TO_REGCLASS Moves.BE_HALF_0, VSRC))>;
1284 def : Pat<(v4i32 (scalar_to_vector i32:$A)),
1285 (v4i32 (COPY_TO_REGCLASS Moves.BE_WORD_0, VSRC))>;
1286 def : Pat<(v2i64 (scalar_to_vector i64:$A)),
1287 (v2i64 (COPY_TO_REGCLASS Moves.BE_DWORD_0, VSRC))>;
1288} // IsBigEndian, HasDirectMove
1289
1290let Predicates = [IsLittleEndian, HasP8Vector] in {
1291 def : Pat<(v4f32 (scalar_to_vector f32:$A)),
1292 (v4f32 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1))>;
1293} // IsLittleEndian, HasP8Vector
1294
1295let Predicates = [IsLittleEndian, HasDirectMove] in {
1296 def : Pat<(v16i8 (scalar_to_vector i32:$A)),
1297 (v16i8 (COPY_TO_REGCLASS Moves.LE_WORD_0, VSRC))>;
1298 def : Pat<(v8i16 (scalar_to_vector i32:$A)),
1299 (v8i16 (COPY_TO_REGCLASS Moves.LE_WORD_0, VSRC))>;
1300 def : Pat<(v4i32 (scalar_to_vector i32:$A)),
1301 (v4i32 (COPY_TO_REGCLASS Moves.LE_WORD_0, VSRC))>;
1302 def : Pat<(v2i64 (scalar_to_vector i64:$A)),
1303 (v2i64 Moves.LE_DWORD_0)>;
1304} // IsLittleEndian, HasDirectMove
1305