Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 1 | //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// |
| 2 | // |
Chandler Carruth | 2946cd7 | 2019-01-19 08:50:56 +0000 | [diff] [blame] | 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // Implements the info about RISCV target spec. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "RISCVTargetMachine.h" |
Sam Elliott | 96c8bc7 | 2019-06-21 13:36:09 +0000 | [diff] [blame] | 14 | #include "RISCV.h" |
Mandeep Singh Grang | 98bc25a | 2018-03-24 18:37:19 +0000 | [diff] [blame] | 15 | #include "RISCVTargetObjectFile.h" |
Sam Elliott | 96c8bc7 | 2019-06-21 13:36:09 +0000 | [diff] [blame] | 16 | #include "RISCVTargetTransformInfo.h" |
Richard Trieu | 51fc56d | 2019-05-15 00:24:15 +0000 | [diff] [blame] | 17 | #include "TargetInfo/RISCVTargetInfo.h" |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 18 | #include "llvm/ADT/STLExtras.h" |
Sam Elliott | 96c8bc7 | 2019-06-21 13:36:09 +0000 | [diff] [blame] | 19 | #include "llvm/Analysis/TargetTransformInfo.h" |
Daniel Sanders | a16bd4f | 2019-08-20 22:53:24 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/GlobalISel/IRTranslator.h" |
| 21 | #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" |
| 22 | #include "llvm/CodeGen/GlobalISel/Legalizer.h" |
| 23 | #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" |
Chandler Carruth | 6bda14b | 2017-06-06 11:49:48 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/Passes.h" |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" |
| 26 | #include "llvm/CodeGen/TargetPassConfig.h" |
| 27 | #include "llvm/IR/LegacyPassManager.h" |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 28 | #include "llvm/Support/FormattedStream.h" |
| 29 | #include "llvm/Support/TargetRegistry.h" |
| 30 | #include "llvm/Target/TargetOptions.h" |
| 31 | using namespace llvm; |
| 32 | |
Tom Stellard | 4b0b261 | 2019-06-11 03:21:13 +0000 | [diff] [blame] | 33 | extern "C" void LLVMInitializeRISCVTarget() { |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 34 | RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); |
| 35 | RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); |
Alex Bradbury | 21aea51 | 2018-09-19 10:54:22 +0000 | [diff] [blame] | 36 | auto PR = PassRegistry::getPassRegistry(); |
Daniel Sanders | a16bd4f | 2019-08-20 22:53:24 +0000 | [diff] [blame] | 37 | initializeGlobalISel(*PR); |
Alex Bradbury | 21aea51 | 2018-09-19 10:54:22 +0000 | [diff] [blame] | 38 | initializeRISCVExpandPseudoPass(*PR); |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 39 | } |
| 40 | |
Alex Bradbury | 6aae216 | 2019-02-19 14:42:00 +0000 | [diff] [blame] | 41 | static StringRef computeDataLayout(const Triple &TT) { |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 42 | if (TT.isArch64Bit()) { |
Mandeep Singh Grang | 47fbc59 | 2017-11-16 20:30:49 +0000 | [diff] [blame] | 43 | return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 44 | } else { |
| 45 | assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); |
Alex Bradbury | e4f731b | 2017-02-14 05:20:20 +0000 | [diff] [blame] | 46 | return "e-m:e-p:32:32-i64:64-n32-S128"; |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 47 | } |
| 48 | } |
| 49 | |
| 50 | static Reloc::Model getEffectiveRelocModel(const Triple &TT, |
| 51 | Optional<Reloc::Model> RM) { |
| 52 | if (!RM.hasValue()) |
| 53 | return Reloc::Static; |
| 54 | return *RM; |
| 55 | } |
| 56 | |
| 57 | RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, |
| 58 | StringRef CPU, StringRef FS, |
| 59 | const TargetOptions &Options, |
| 60 | Optional<Reloc::Model> RM, |
Rafael Espindola | 79e238a | 2017-08-03 02:16:21 +0000 | [diff] [blame] | 61 | Optional<CodeModel::Model> CM, |
| 62 | CodeGenOpt::Level OL, bool JIT) |
Matthias Braun | bb8507e | 2017-10-12 22:57:28 +0000 | [diff] [blame] | 63 | : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, |
| 64 | getEffectiveRelocModel(TT, RM), |
David Green | ca29c27 | 2018-12-07 12:10:23 +0000 | [diff] [blame] | 65 | getEffectiveCodeModel(CM, CodeModel::Small), OL), |
Jonas Devlieghere | 0eaee54 | 2019-08-15 15:54:37 +0000 | [diff] [blame] | 66 | TLOF(std::make_unique<RISCVELFTargetObjectFile>()), |
Alex Bradbury | fea4957 | 2019-03-09 09:28:06 +0000 | [diff] [blame] | 67 | Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) { |
Alex Bradbury | e4f731b | 2017-02-14 05:20:20 +0000 | [diff] [blame] | 68 | initAsmInfo(); |
| 69 | } |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 70 | |
Sam Elliott | 96c8bc7 | 2019-06-21 13:36:09 +0000 | [diff] [blame] | 71 | TargetTransformInfo |
| 72 | RISCVTargetMachine::getTargetTransformInfo(const Function &F) { |
| 73 | return TargetTransformInfo(RISCVTTIImpl(this, F)); |
| 74 | } |
| 75 | |
Alex Bradbury | 8971842 | 2017-10-19 21:37:38 +0000 | [diff] [blame] | 76 | namespace { |
| 77 | class RISCVPassConfig : public TargetPassConfig { |
| 78 | public: |
| 79 | RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) |
| 80 | : TargetPassConfig(TM, PM) {} |
| 81 | |
| 82 | RISCVTargetMachine &getRISCVTargetMachine() const { |
| 83 | return getTM<RISCVTargetMachine>(); |
| 84 | } |
| 85 | |
Alex Bradbury | dc790dd | 2018-06-13 11:58:46 +0000 | [diff] [blame] | 86 | void addIRPasses() override; |
Alex Bradbury | 8971842 | 2017-10-19 21:37:38 +0000 | [diff] [blame] | 87 | bool addInstSelector() override; |
Daniel Sanders | a16bd4f | 2019-08-20 22:53:24 +0000 | [diff] [blame] | 88 | bool addIRTranslator() override; |
| 89 | bool addLegalizeMachineIR() override; |
| 90 | bool addRegBankSelect() override; |
| 91 | bool addGlobalInstructionSelect() override; |
Alex Bradbury | 315cd3a | 2018-01-10 21:05:07 +0000 | [diff] [blame] | 92 | void addPreEmitPass() override; |
Alex Bradbury | 21aea51 | 2018-09-19 10:54:22 +0000 | [diff] [blame] | 93 | void addPreEmitPass2() override; |
Sameer AbuAsal | 9b65ffb | 2018-06-27 20:51:42 +0000 | [diff] [blame] | 94 | void addPreRegAlloc() override; |
Alex Bradbury | 8971842 | 2017-10-19 21:37:38 +0000 | [diff] [blame] | 95 | }; |
| 96 | } |
| 97 | |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 98 | TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { |
Alex Bradbury | 8971842 | 2017-10-19 21:37:38 +0000 | [diff] [blame] | 99 | return new RISCVPassConfig(*this, PM); |
| 100 | } |
| 101 | |
Alex Bradbury | dc790dd | 2018-06-13 11:58:46 +0000 | [diff] [blame] | 102 | void RISCVPassConfig::addIRPasses() { |
| 103 | addPass(createAtomicExpandPass()); |
| 104 | TargetPassConfig::addIRPasses(); |
| 105 | } |
| 106 | |
Alex Bradbury | 8971842 | 2017-10-19 21:37:38 +0000 | [diff] [blame] | 107 | bool RISCVPassConfig::addInstSelector() { |
| 108 | addPass(createRISCVISelDag(getRISCVTargetMachine())); |
| 109 | |
| 110 | return false; |
Alex Bradbury | b2e5472 | 2016-11-01 17:27:54 +0000 | [diff] [blame] | 111 | } |
Alex Bradbury | 315cd3a | 2018-01-10 21:05:07 +0000 | [diff] [blame] | 112 | |
Daniel Sanders | a16bd4f | 2019-08-20 22:53:24 +0000 | [diff] [blame] | 113 | bool RISCVPassConfig::addIRTranslator() { |
| 114 | addPass(new IRTranslator()); |
| 115 | return false; |
| 116 | } |
| 117 | |
| 118 | bool RISCVPassConfig::addLegalizeMachineIR() { |
| 119 | addPass(new Legalizer()); |
| 120 | return false; |
| 121 | } |
| 122 | |
| 123 | bool RISCVPassConfig::addRegBankSelect() { |
| 124 | addPass(new RegBankSelect()); |
| 125 | return false; |
| 126 | } |
| 127 | |
| 128 | bool RISCVPassConfig::addGlobalInstructionSelect() { |
| 129 | addPass(new InstructionSelect()); |
| 130 | return false; |
| 131 | } |
| 132 | |
Alex Bradbury | 315cd3a | 2018-01-10 21:05:07 +0000 | [diff] [blame] | 133 | void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } |
Sameer AbuAsal | 9b65ffb | 2018-06-27 20:51:42 +0000 | [diff] [blame] | 134 | |
Alex Bradbury | 21aea51 | 2018-09-19 10:54:22 +0000 | [diff] [blame] | 135 | void RISCVPassConfig::addPreEmitPass2() { |
| 136 | // Schedule the expansion of AMOs at the last possible moment, avoiding the |
| 137 | // possibility for other passes to break the requirements for forward |
| 138 | // progress in the LR/SC block. |
| 139 | addPass(createRISCVExpandPseudoPass()); |
| 140 | } |
| 141 | |
Sameer AbuAsal | 9b65ffb | 2018-06-27 20:51:42 +0000 | [diff] [blame] | 142 | void RISCVPassConfig::addPreRegAlloc() { |
| 143 | addPass(createRISCVMergeBaseOffsetOptPass()); |
| 144 | } |