blob: 5ffc6eda6bd7c8c2ae5a55d22ba6e8e1abf41d8d [file] [log] [blame]
Alex Bradburyb2e54722016-11-01 17:27:54 +00001//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Alex Bradburyb2e54722016-11-01 17:27:54 +00006//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISCV target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
Sam Elliott96c8bc72019-06-21 13:36:09 +000014#include "RISCV.h"
Mandeep Singh Grang98bc25a2018-03-24 18:37:19 +000015#include "RISCVTargetObjectFile.h"
Sam Elliott96c8bc72019-06-21 13:36:09 +000016#include "RISCVTargetTransformInfo.h"
Richard Trieu51fc56d2019-05-15 00:24:15 +000017#include "TargetInfo/RISCVTargetInfo.h"
Alex Bradburyb2e54722016-11-01 17:27:54 +000018#include "llvm/ADT/STLExtras.h"
Sam Elliott96c8bc72019-06-21 13:36:09 +000019#include "llvm/Analysis/TargetTransformInfo.h"
Daniel Sandersa16bd4f2019-08-20 22:53:24 +000020#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
22#include "llvm/CodeGen/GlobalISel/Legalizer.h"
23#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000024#include "llvm/CodeGen/Passes.h"
Alex Bradburyb2e54722016-11-01 17:27:54 +000025#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26#include "llvm/CodeGen/TargetPassConfig.h"
27#include "llvm/IR/LegacyPassManager.h"
Alex Bradburyb2e54722016-11-01 17:27:54 +000028#include "llvm/Support/FormattedStream.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Target/TargetOptions.h"
31using namespace llvm;
32
Tom Stellard4b0b2612019-06-11 03:21:13 +000033extern "C" void LLVMInitializeRISCVTarget() {
Alex Bradburyb2e54722016-11-01 17:27:54 +000034 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
35 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
Alex Bradbury21aea512018-09-19 10:54:22 +000036 auto PR = PassRegistry::getPassRegistry();
Daniel Sandersa16bd4f2019-08-20 22:53:24 +000037 initializeGlobalISel(*PR);
Alex Bradbury21aea512018-09-19 10:54:22 +000038 initializeRISCVExpandPseudoPass(*PR);
Alex Bradburyb2e54722016-11-01 17:27:54 +000039}
40
Alex Bradbury6aae2162019-02-19 14:42:00 +000041static StringRef computeDataLayout(const Triple &TT) {
Alex Bradburyb2e54722016-11-01 17:27:54 +000042 if (TT.isArch64Bit()) {
Mandeep Singh Grang47fbc592017-11-16 20:30:49 +000043 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
Alex Bradburyb2e54722016-11-01 17:27:54 +000044 } else {
45 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
Alex Bradburye4f731b2017-02-14 05:20:20 +000046 return "e-m:e-p:32:32-i64:64-n32-S128";
Alex Bradburyb2e54722016-11-01 17:27:54 +000047 }
48}
49
50static Reloc::Model getEffectiveRelocModel(const Triple &TT,
51 Optional<Reloc::Model> RM) {
52 if (!RM.hasValue())
53 return Reloc::Static;
54 return *RM;
55}
56
57RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
58 StringRef CPU, StringRef FS,
59 const TargetOptions &Options,
60 Optional<Reloc::Model> RM,
Rafael Espindola79e238a2017-08-03 02:16:21 +000061 Optional<CodeModel::Model> CM,
62 CodeGenOpt::Level OL, bool JIT)
Matthias Braunbb8507e2017-10-12 22:57:28 +000063 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
64 getEffectiveRelocModel(TT, RM),
David Greenca29c272018-12-07 12:10:23 +000065 getEffectiveCodeModel(CM, CodeModel::Small), OL),
Jonas Devlieghere0eaee542019-08-15 15:54:37 +000066 TLOF(std::make_unique<RISCVELFTargetObjectFile>()),
Alex Bradburyfea49572019-03-09 09:28:06 +000067 Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
Alex Bradburye4f731b2017-02-14 05:20:20 +000068 initAsmInfo();
69}
Alex Bradburyb2e54722016-11-01 17:27:54 +000070
Sam Elliott96c8bc72019-06-21 13:36:09 +000071TargetTransformInfo
72RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
73 return TargetTransformInfo(RISCVTTIImpl(this, F));
74}
75
Alex Bradbury89718422017-10-19 21:37:38 +000076namespace {
77class RISCVPassConfig : public TargetPassConfig {
78public:
79 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
80 : TargetPassConfig(TM, PM) {}
81
82 RISCVTargetMachine &getRISCVTargetMachine() const {
83 return getTM<RISCVTargetMachine>();
84 }
85
Alex Bradburydc790dd2018-06-13 11:58:46 +000086 void addIRPasses() override;
Alex Bradbury89718422017-10-19 21:37:38 +000087 bool addInstSelector() override;
Daniel Sandersa16bd4f2019-08-20 22:53:24 +000088 bool addIRTranslator() override;
89 bool addLegalizeMachineIR() override;
90 bool addRegBankSelect() override;
91 bool addGlobalInstructionSelect() override;
Alex Bradbury315cd3a2018-01-10 21:05:07 +000092 void addPreEmitPass() override;
Alex Bradbury21aea512018-09-19 10:54:22 +000093 void addPreEmitPass2() override;
Sameer AbuAsal9b65ffb2018-06-27 20:51:42 +000094 void addPreRegAlloc() override;
Alex Bradbury89718422017-10-19 21:37:38 +000095};
96}
97
Alex Bradburyb2e54722016-11-01 17:27:54 +000098TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
Alex Bradbury89718422017-10-19 21:37:38 +000099 return new RISCVPassConfig(*this, PM);
100}
101
Alex Bradburydc790dd2018-06-13 11:58:46 +0000102void RISCVPassConfig::addIRPasses() {
103 addPass(createAtomicExpandPass());
104 TargetPassConfig::addIRPasses();
105}
106
Alex Bradbury89718422017-10-19 21:37:38 +0000107bool RISCVPassConfig::addInstSelector() {
108 addPass(createRISCVISelDag(getRISCVTargetMachine()));
109
110 return false;
Alex Bradburyb2e54722016-11-01 17:27:54 +0000111}
Alex Bradbury315cd3a2018-01-10 21:05:07 +0000112
Daniel Sandersa16bd4f2019-08-20 22:53:24 +0000113bool RISCVPassConfig::addIRTranslator() {
114 addPass(new IRTranslator());
115 return false;
116}
117
118bool RISCVPassConfig::addLegalizeMachineIR() {
119 addPass(new Legalizer());
120 return false;
121}
122
123bool RISCVPassConfig::addRegBankSelect() {
124 addPass(new RegBankSelect());
125 return false;
126}
127
128bool RISCVPassConfig::addGlobalInstructionSelect() {
129 addPass(new InstructionSelect());
130 return false;
131}
132
Alex Bradbury315cd3a2018-01-10 21:05:07 +0000133void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
Sameer AbuAsal9b65ffb2018-06-27 20:51:42 +0000134
Alex Bradbury21aea512018-09-19 10:54:22 +0000135void RISCVPassConfig::addPreEmitPass2() {
136 // Schedule the expansion of AMOs at the last possible moment, avoiding the
137 // possibility for other passes to break the requirements for forward
138 // progress in the LR/SC block.
139 addPass(createRISCVExpandPseudoPass());
140}
141
Sameer AbuAsal9b65ffb2018-06-27 20:51:42 +0000142void RISCVPassConfig::addPreRegAlloc() {
143 addPass(createRISCVMergeBaseOffsetOptPass());
144}