Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 1 | //===-- VOP3PInstructions.td - Vector Instruction Defintions --------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // VOP3P Classes |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> : |
| 15 | VOP3P_Pseudo<OpName, P, |
| 16 | !if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret) |
| 17 | >; |
| 18 | |
Dmitry Preobrazhensky | b2d24e2 | 2017-07-07 14:29:06 +0000 | [diff] [blame] | 19 | // Non-packed instructions that use the VOP3P encoding. |
| 20 | // VOP3 neg/abs and VOP3P opsel/opsel_hi modifiers are allowed. |
Matt Arsenault | e135c4c | 2017-09-20 20:53:49 +0000 | [diff] [blame] | 21 | class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0, |
| 22 | SDPatternOperator node = null_frag> : |
Dmitry Preobrazhensky | b2d24e2 | 2017-07-07 14:29:06 +0000 | [diff] [blame] | 23 | VOP3P_Pseudo<OpName, P> { |
Matt Arsenault | c8f8cda | 2017-08-30 22:18:40 +0000 | [diff] [blame] | 24 | // These operands are only sort of f16 operands. Depending on |
| 25 | // op_sel_hi, these may be interpreted as f32. The inline immediate |
| 26 | // values are really f16 converted to f32, so we treat these as f16 |
| 27 | // operands. |
Dmitry Preobrazhensky | b2d24e2 | 2017-07-07 14:29:06 +0000 | [diff] [blame] | 28 | let InOperandList = |
Matt Arsenault | e135c4c | 2017-09-20 20:53:49 +0000 | [diff] [blame] | 29 | !con( |
| 30 | !con( |
| 31 | (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0, |
| 32 | FP16InputMods:$src1_modifiers, VCSrc_f16:$src1, |
| 33 | FP16InputMods:$src2_modifiers, VCSrc_f16:$src2, |
| 34 | clampmod:$clamp), |
| 35 | !if(UseTiedOutput, (ins VGPR_32:$vdst_in), (ins))), |
| 36 | (ins op_sel:$op_sel, op_sel_hi:$op_sel_hi)); |
| 37 | |
| 38 | let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", ""); |
| 39 | let DisableEncoding = !if(UseTiedOutput, "$vdst_in", ""); |
Dmitry Preobrazhensky | b2d24e2 | 2017-07-07 14:29:06 +0000 | [diff] [blame] | 40 | let AsmOperands = |
| 41 | " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$op_sel$op_sel_hi$clamp"; |
| 42 | } |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 43 | |
| 44 | let isCommutable = 1 in { |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 45 | def V_PK_FMA_F16 : VOP3PInst<"v_pk_fma_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16_V2F16>, fma>; |
Dmitry Preobrazhensky | 095ec3da | 2017-07-18 09:24:10 +0000 | [diff] [blame] | 46 | def V_PK_MAD_I16 : VOP3PInst<"v_pk_mad_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; |
| 47 | def V_PK_MAD_U16 : VOP3PInst<"v_pk_mad_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16_V2I16>>; |
| 48 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 49 | def V_PK_ADD_F16 : VOP3PInst<"v_pk_add_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fadd>; |
| 50 | def V_PK_MUL_F16 : VOP3PInst<"v_pk_mul_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmul>; |
| 51 | def V_PK_MAX_F16 : VOP3PInst<"v_pk_max_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fmaxnum>; |
| 52 | def V_PK_MIN_F16 : VOP3PInst<"v_pk_min_f16", VOP3_Profile<VOP_V2F16_V2F16_V2F16>, fminnum>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 53 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 54 | def V_PK_ADD_U16 : VOP3PInst<"v_pk_add_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, add>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 55 | def V_PK_ADD_I16 : VOP3PInst<"v_pk_add_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>; |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 56 | def V_PK_MUL_LO_U16 : VOP3PInst<"v_pk_mul_lo_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, mul>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 57 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 58 | def V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smin>; |
| 59 | def V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umin>; |
| 60 | def V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, smax>; |
| 61 | def V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, umax>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 62 | } |
| 63 | |
Dmitry Preobrazhensky | 095ec3da | 2017-07-18 09:24:10 +0000 | [diff] [blame] | 64 | def V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>>; |
| 65 | def V_PK_SUB_I16 : VOP3PInst<"v_pk_sub_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, sub>; |
| 66 | |
Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 67 | def V_PK_LSHLREV_B16 : VOP3PInst<"v_pk_lshlrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshl_rev>; |
| 68 | def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, ashr_rev>; |
| 69 | def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 70 | |
Matt Arsenault | 28f52e5 | 2017-10-25 07:00:51 +0000 | [diff] [blame] | 71 | |
| 72 | let SubtargetPredicate = HasMadMixInsts in { |
Dmitry Preobrazhensky | b2d24e2 | 2017-07-07 14:29:06 +0000 | [diff] [blame] | 73 | // These are VOP3a-like opcodes which accept no omod. |
| 74 | // Size of src arguments (16/32) is controlled by op_sel. |
| 75 | // For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi. |
Matt Arsenault | c8f8cda | 2017-08-30 22:18:40 +0000 | [diff] [blame] | 76 | let isCommutable = 1 in { |
Matt Arsenault | 644883f | 2017-09-20 19:09:28 +0000 | [diff] [blame] | 77 | def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>; |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 78 | |
| 79 | // Clamp modifier is applied after conversion to f16. |
Matt Arsenault | e135c4c | 2017-09-20 20:53:49 +0000 | [diff] [blame] | 80 | def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 81 | |
| 82 | let ClampLo = 0, ClampHi = 1 in { |
Matt Arsenault | e135c4c | 2017-09-20 20:53:49 +0000 | [diff] [blame] | 83 | def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>; |
Matt Arsenault | c8f8cda | 2017-08-30 22:18:40 +0000 | [diff] [blame] | 84 | } |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 85 | } |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 86 | |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 87 | def : GCNPat < |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 88 | (f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), |
| 89 | (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), |
| 90 | (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), |
| 91 | (V_MAD_MIXLO_F16 $src0_modifiers, $src0, |
| 92 | $src1_modifiers, $src1, |
| 93 | $src2_modifiers, $src2, |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 94 | DSTCLAMP.NONE, |
Matt Arsenault | e135c4c | 2017-09-20 20:53:49 +0000 | [diff] [blame] | 95 | (i32 (IMPLICIT_DEF))) |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 96 | >; |
| 97 | |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 98 | // FIXME: Special case handling for maxhi (especially for clamp) |
| 99 | // because dealing with the write to high half of the register is |
| 100 | // difficult. |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 101 | def : GCNPat < |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 102 | (build_vector f16:$elt0, (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), |
| 103 | (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), |
| 104 | (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), |
| 105 | (v2f16 (V_MAD_MIXHI_F16 $src0_modifiers, $src0, |
| 106 | $src1_modifiers, $src1, |
| 107 | $src2_modifiers, $src2, |
| 108 | DSTCLAMP.NONE, |
| 109 | $elt0)) |
| 110 | >; |
| 111 | |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 112 | def : GCNPat < |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 113 | (build_vector |
| 114 | f16:$elt0, |
| 115 | (AMDGPUclamp (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), |
| 116 | (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), |
| 117 | (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers)))))), |
| 118 | (v2f16 (V_MAD_MIXHI_F16 $src0_modifiers, $src0, |
| 119 | $src1_modifiers, $src1, |
| 120 | $src2_modifiers, $src2, |
| 121 | DSTCLAMP.ENABLE, |
| 122 | $elt0)) |
| 123 | >; |
| 124 | |
Matt Arsenault | 90c7593 | 2017-10-03 00:06:41 +0000 | [diff] [blame] | 125 | def : GCNPat < |
Matt Arsenault | 8cbb488 | 2017-09-20 21:01:24 +0000 | [diff] [blame] | 126 | (AMDGPUclamp (build_vector |
| 127 | (fpround (fmad (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)), |
| 128 | (f32 (VOP3PMadMixMods f16:$lo_src1, i32:$lo_src1_modifiers)), |
| 129 | (f32 (VOP3PMadMixMods f16:$lo_src2, i32:$lo_src2_modifiers)))), |
| 130 | (fpround (fmad (f32 (VOP3PMadMixMods f16:$hi_src0, i32:$hi_src0_modifiers)), |
| 131 | (f32 (VOP3PMadMixMods f16:$hi_src1, i32:$hi_src1_modifiers)), |
| 132 | (f32 (VOP3PMadMixMods f16:$hi_src2, i32:$hi_src2_modifiers)))))), |
| 133 | (v2f16 (V_MAD_MIXHI_F16 $hi_src0_modifiers, $hi_src0, |
| 134 | $hi_src1_modifiers, $hi_src1, |
| 135 | $hi_src2_modifiers, $hi_src2, |
| 136 | DSTCLAMP.ENABLE, |
| 137 | (V_MAD_MIXLO_F16 $lo_src0_modifiers, $lo_src0, |
| 138 | $lo_src1_modifiers, $lo_src1, |
| 139 | $lo_src2_modifiers, $lo_src2, |
| 140 | DSTCLAMP.ENABLE, |
| 141 | (i32 (IMPLICIT_DEF))))) |
| 142 | >; |
| 143 | |
Matt Arsenault | 28f52e5 | 2017-10-25 07:00:51 +0000 | [diff] [blame] | 144 | } // End SubtargetPredicate = [HasMadMixInsts] |
Matt Arsenault | 7693512 | 2017-09-20 20:28:39 +0000 | [diff] [blame] | 145 | |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 146 | multiclass VOP3P_Real_vi<bits<10> op> { |
| 147 | def _vi : VOP3P_Real<!cast<VOP3P_Pseudo>(NAME), SIEncodingFamily.VI>, |
| 148 | VOP3Pe <op, !cast<VOP3P_Pseudo>(NAME).Pfl> { |
| 149 | let AssemblerPredicates = [HasVOP3PInsts]; |
| 150 | let DecoderNamespace = "VI"; |
| 151 | } |
| 152 | } |
| 153 | |
Dmitry Preobrazhensky | 095ec3da | 2017-07-18 09:24:10 +0000 | [diff] [blame] | 154 | defm V_PK_MAD_I16 : VOP3P_Real_vi <0x380>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 155 | defm V_PK_MUL_LO_U16 : VOP3P_Real_vi <0x381>; |
| 156 | defm V_PK_ADD_I16 : VOP3P_Real_vi <0x382>; |
| 157 | defm V_PK_SUB_I16 : VOP3P_Real_vi <0x383>; |
| 158 | defm V_PK_LSHLREV_B16 : VOP3P_Real_vi <0x384>; |
| 159 | defm V_PK_LSHRREV_B16 : VOP3P_Real_vi <0x385>; |
| 160 | defm V_PK_ASHRREV_I16 : VOP3P_Real_vi <0x386>; |
| 161 | defm V_PK_MAX_I16 : VOP3P_Real_vi <0x387>; |
| 162 | defm V_PK_MIN_I16 : VOP3P_Real_vi <0x388>; |
Dmitry Preobrazhensky | 095ec3da | 2017-07-18 09:24:10 +0000 | [diff] [blame] | 163 | defm V_PK_MAD_U16 : VOP3P_Real_vi <0x389>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 164 | |
| 165 | defm V_PK_ADD_U16 : VOP3P_Real_vi <0x38a>; |
Dmitry Preobrazhensky | 095ec3da | 2017-07-18 09:24:10 +0000 | [diff] [blame] | 166 | defm V_PK_SUB_U16 : VOP3P_Real_vi <0x38b>; |
Matt Arsenault | 9be7b0d | 2017-02-27 18:49:11 +0000 | [diff] [blame] | 167 | defm V_PK_MAX_U16 : VOP3P_Real_vi <0x38c>; |
| 168 | defm V_PK_MIN_U16 : VOP3P_Real_vi <0x38d>; |
| 169 | defm V_PK_FMA_F16 : VOP3P_Real_vi <0x38e>; |
| 170 | defm V_PK_ADD_F16 : VOP3P_Real_vi <0x38f>; |
| 171 | defm V_PK_MUL_F16 : VOP3P_Real_vi <0x390>; |
| 172 | defm V_PK_MIN_F16 : VOP3P_Real_vi <0x391>; |
| 173 | defm V_PK_MAX_F16 : VOP3P_Real_vi <0x392>; |
| 174 | |
| 175 | defm V_MAD_MIX_F32 : VOP3P_Real_vi <0x3a0>; |
| 176 | defm V_MAD_MIXLO_F16 : VOP3P_Real_vi <0x3a1>; |
| 177 | defm V_MAD_MIXHI_F16 : VOP3P_Real_vi <0x3a2>; |