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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 2f608b5bb218bddff9da91afc61f9975c340ef1b [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]16
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoon6f358372012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]19#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
Patrik Hagglund8d09a6c2014-03-15 09:11:41 +0000[diff] [blame]28struct EVT;
Eric Christopher234a1ec2015-03-12 06:07:16 +0000[diff] [blame]29class HexagonSubtarget;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]30
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]31class HexagonInstrInfo : public HexagonGenInstrInfo {
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]32 virtual void anchor();
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]33 const HexagonRegisterInfo RI;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]34
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]35public:
36 explicit HexagonInstrInfo(HexagonSubtarget &ST);
37
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]38 /// TargetInstrInfo overrides.
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]39 ///
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]40
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]41 /// If the specified machine instruction is a direct
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]46 unsigned isLoadFromStackSlot(const MachineInstr *MI,
47 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]48
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]49 /// If the specified machine instruction is a direct
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]50 /// store to a stack slot, return the virtual or physical register number of
51 /// the source reg along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than storing to the stack slot.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]54 unsigned isStoreToStackSlot(const MachineInstr *MI,
55 int &FrameIndex) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]56
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]57 /// Analyze the branching code at the end of MBB, returning
58 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
59 /// implemented for a target). Upon success, this returns false and returns
60 /// with the following information in various cases:
61 ///
62 /// 1. If this block ends with no branches (it just falls through to its succ)
63 /// just return false, leaving TBB/FBB null.
64 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
65 /// the destination block.
66 /// 3. If this block ends with a conditional branch and it falls through to a
67 /// successor block, it sets TBB to be the branch destination block and a
68 /// list of operands that evaluate the condition. These operands can be
69 /// passed to other TargetInstrInfo methods to create new branches.
70 /// 4. If this block ends with a conditional branch followed by an
71 /// unconditional branch, it returns the 'true' destination in TBB, the
72 /// 'false' destination in FBB, and a list of operands that evaluate the
73 /// condition. These operands can be passed to other TargetInstrInfo
74 /// methods to create new branches.
75 ///
76 /// Note that RemoveBranch and InsertBranch must be implemented to support
77 /// cases where this method returns success.
78 ///
79 /// If AllowModify is true, then this routine is allowed to modify the basic
80 /// block (e.g. delete instructions after the unconditional branch).
81 ///
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]82 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
83 MachineBasicBlock *&FBB,
84 SmallVectorImpl<MachineOperand> &Cond,
85 bool AllowModify) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]86
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]87 /// Remove the branching code at the end of the specific MBB.
88 /// This is only invoked in cases where AnalyzeBranch returns success. It
89 /// returns the number of instructions that were removed.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]90 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]91
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]92 /// Insert branch code into the end of the specified MachineBasicBlock.
93 /// The operands to this method are the same as those
94 /// returned by AnalyzeBranch. This is only invoked in cases where
95 /// AnalyzeBranch returns success. It returns the number of instructions
96 /// inserted.
97 ///
98 /// It is also invoked by tail merging to add unconditional branches in
99 /// cases where AnalyzeBranch doesn't apply because there was no original
100 /// branch to analyze. At least this much must be implemented, else tail
101 /// merging needs to be disabled.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]102 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]103 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]104 DebugLoc DL) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]105
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]106 /// Return true if it's profitable to predicate
107 /// instructions with accumulated instruction latency of "NumCycles"
108 /// of the specified basic block, where the probability of the instructions
109 /// being executed is given by Probability, and Confidence is a measure
110 /// of our confidence that it will be properly predicted.
111 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
112 unsigned ExtraPredCycles,
113 BranchProbability Probability) const override;
Krzysztof Parzyszekcfe285e2013-02-11 20:04:29 +0000[diff] [blame]114
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]115 /// Second variant of isProfitableToIfCvt. This one
116 /// checks for the case where two basic blocks from true and false path
117 /// of a if-then-else (diamond) are predicated on mutally exclusive
118 /// predicates, where the probability of the true path being taken is given
119 /// by Probability, and Confidence is a measure of our confidence that it
120 /// will be properly predicted.
121 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
122 unsigned NumTCycles, unsigned ExtraTCycles,
123 MachineBasicBlock &FMBB,
124 unsigned NumFCycles, unsigned ExtraFCycles,
125 BranchProbability Probability) const override;
126
127 /// Return true if it's profitable for if-converter to duplicate instructions
128 /// of specified accumulated instruction latencies in the specified MBB to
129 /// enable if-conversion.
130 /// The probability of the instructions being executed is given by
131 /// Probability, and Confidence is a measure of our confidence that it
132 /// will be properly predicted.
133 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
134 BranchProbability Probability) const override;
135
136 /// Emit instructions to copy a pair of physical registers.
137 ///
138 /// This function should support copies within any legal register class as
139 /// well as any cross-class copies created during instruction selection.
140 ///
141 /// The source and destination registers may overlap, which may require a
142 /// careful implementation when multiple copy instructions are required for
143 /// large registers. See for example the ARM target.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]144 void copyPhysReg(MachineBasicBlock &MBB,
145 MachineBasicBlock::iterator I, DebugLoc DL,
146 unsigned DestReg, unsigned SrcReg,
147 bool KillSrc) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]148
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]149 /// Store the specified register of the given register class to the specified
150 /// stack frame index. The store instruction is to be added to the given
151 /// machine basic block before the specified machine instruction. If isKill
152 /// is true, the register operand is the last use and must be marked kill.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]153 void storeRegToStackSlot(MachineBasicBlock &MBB,
154 MachineBasicBlock::iterator MBBI,
155 unsigned SrcReg, bool isKill, int FrameIndex,
156 const TargetRegisterClass *RC,
157 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]158
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]159 /// Load the specified register of the given register class from the specified
160 /// stack frame index. The load instruction is to be added to the given
161 /// machine basic block before the specified machine instruction.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]162 void loadRegFromStackSlot(MachineBasicBlock &MBB,
163 MachineBasicBlock::iterator MBBI,
164 unsigned DestReg, int FrameIndex,
165 const TargetRegisterClass *RC,
166 const TargetRegisterInfo *TRI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]167
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]168 /// This function is called for all pseudo instructions
Colin LeMahieu7b1799c2015-03-09 22:05:21 +0000[diff] [blame]169 /// that remain after register allocation. Many pseudo instructions are
170 /// created to help register allocation. This is the place to convert them
171 /// into real instructions. The target can edit MI in place, or it can insert
172 /// new instructions and erase MI. The function should return true if
173 /// anything was changed.
174 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
175
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]176 /// Reverses the branch condition of the specified condition list,
177 /// returning false on success and true if it cannot be reversed.
178 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
179 const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]180
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]181 /// Insert a noop into the instruction stream at the specified point.
182 void insertNoop(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator MI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]184
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]185 /// Returns true if the instruction is already predicated.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]186 bool isPredicated(const MachineInstr &MI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]187
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]188 /// Convert the instruction into a predicated instruction.
189 /// It returns true if the operation was successful.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]190 bool PredicateInstruction(MachineInstr &MI,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]191 ArrayRef<MachineOperand> Cond) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]192
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]193 /// Returns true if the first specified predicate
194 /// subsumes the second, e.g. GE subsumes GT.
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]195 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
196 ArrayRef<MachineOperand> Pred2) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]197
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]198 /// If the specified instruction defines any predicate
199 /// or condition code register(s) used for predication, returns true as well
200 /// as the definition predicate(s) by reference.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]201 bool DefinesPredicate(MachineInstr &MI,
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]202 std::vector<MachineOperand> &Pred) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]203
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]204 /// Return true if the specified instruction can be predicated.
205 /// By default, this returns true for every instruction with a
206 /// PredicateOperand.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]207 bool isPredicable(MachineInstr &MI) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]208
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]209 /// Test if the given instruction should be considered a scheduling boundary.
210 /// This primarily includes labels and terminators.
Craig Topper906c2cd2014-04-29 07:58:16 +0000[diff] [blame]211 bool isSchedulingBoundary(const MachineInstr *MI,
212 const MachineBasicBlock *MBB,
213 const MachineFunction &MF) const override;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]214
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]215 /// Measure the specified inline asm to determine an approximation of its
216 /// length.
217 unsigned getInlineAsmLength(const char *Str,
218 const MCAsmInfo &MAI) const override;
219
220 /// Allocate and return a hazard recognizer to use for this target when
221 /// scheduling the machine instructions after register allocation.
222 ScheduleHazardRecognizer*
223 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
224 const ScheduleDAG *DAG) const override;
225
226 /// For a comparison instruction, return the source registers
227 /// in SrcReg and SrcReg2 if having two register operands, and the value it
228 /// compares against in CmpValue. Return true if the comparison instruction
229 /// can be analyzed.
230 bool analyzeCompare(const MachineInstr *MI,
231 unsigned &SrcReg, unsigned &SrcReg2,
232 int &Mask, int &Value) const override;
233
234 /// Compute the instruction latency of a given instruction.
235 /// If the instruction has higher cost when predicated, it's returned via
236 /// PredCost.
237 unsigned getInstrLatency(const InstrItineraryData *ItinData,
238 const MachineInstr *MI,
239 unsigned *PredCost = 0) const override;
240
241 /// Create machine specific model for scheduling.
242 DFAPacketizer *
243 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
244
245 // Sometimes, it is possible for the target
246 // to tell, even without aliasing information, that two MIs access different
247 // memory addresses. This function returns true if two MIs access different
248 // memory addresses and false otherwise.
249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
250 AliasAnalysis *AA = nullptr)
251 const override;
252
253
254 /// HexagonInstrInfo specifics.
255 ///
256
257 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
258
259 unsigned createVR(MachineFunction* MF, MVT VT) const;
260
261 bool isAbsoluteSet(const MachineInstr* MI) const;
262 bool isAccumulator(const MachineInstr *MI) const;
263 bool isComplex(const MachineInstr *MI) const;
264 bool isCompoundBranchInstr(const MachineInstr *MI) const;
265 bool isCondInst(const MachineInstr *MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]266 bool isConditionalALU32 (const MachineInstr* MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]267 bool isConditionalLoad(const MachineInstr* MI) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]268 bool isConditionalStore(const MachineInstr* MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]269 bool isConditionalTransfer(const MachineInstr* MI) const;
270 bool isConstExtended(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]271 bool isDeallocRet(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]272 bool isDependent(const MachineInstr *ProdMI,
273 const MachineInstr *ConsMI) const;
274 bool isDotCurInst(const MachineInstr* MI) const;
275 bool isDotNewInst(const MachineInstr* MI) const;
276 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]277 bool isEarlySourceInstr(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]278 bool isEndLoopN(unsigned Opcode) const;
279 bool isExpr(unsigned OpType) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]280 bool isExtendable(const MachineInstr* MI) const;
281 bool isExtended(const MachineInstr* MI) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]282 bool isFloat(const MachineInstr *MI) const;
Krzysztof Parzyszek56bbf542015-12-16 19:36:12 +0000[diff] [blame]283 bool isHVXMemWithAIndirect(const MachineInstr *I,
284 const MachineInstr *J) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]285 bool isIndirectCall(const MachineInstr *MI) const;
286 bool isIndirectL4Return(const MachineInstr *MI) const;
287 bool isJumpR(const MachineInstr *MI) const;
288 bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]289 bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
290 const MachineInstr *ESMI) const;
291 bool isLateResultInstr(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]292 bool isLateSourceInstr(const MachineInstr *MI) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]293 bool isLoopN(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]294 bool isMemOp(const MachineInstr *MI) const;
295 bool isNewValue(const MachineInstr* MI) const;
296 bool isNewValue(unsigned Opcode) const;
297 bool isNewValueInst(const MachineInstr* MI) const;
298 bool isNewValueJump(const MachineInstr* MI) const;
299 bool isNewValueJump(unsigned Opcode) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]300 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]301 bool isNewValueStore(unsigned Opcode) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]302 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
303 bool isPostIncrement(const MachineInstr* MI) const;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]304 bool isPredicatedNew(const MachineInstr &MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]305 bool isPredicatedNew(unsigned Opcode) const;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]306 bool isPredicatedTrue(const MachineInstr &MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]307 bool isPredicatedTrue(unsigned Opcode) const;
308 bool isPredicated(unsigned Opcode) const;
309 bool isPredicateLate(unsigned Opcode) const;
310 bool isPredictedTaken(unsigned Opcode) const;
311 bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
Krzysztof Parzyszekfd02aad2016-02-12 18:37:23 +0000[diff] [blame]312 bool isSignExtendingLoad(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]313 bool isSolo(const MachineInstr* MI) const;
314 bool isSpillPredRegOp(const MachineInstr *MI) const;
315 bool isTC1(const MachineInstr *MI) const;
316 bool isTC2(const MachineInstr *MI) const;
317 bool isTC2Early(const MachineInstr *MI) const;
318 bool isTC4x(const MachineInstr *MI) const;
319 bool isV60VectorInstruction(const MachineInstr *MI) const;
320 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
321 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
322 bool isVecAcc(const MachineInstr *MI) const;
323 bool isVecALU(const MachineInstr *MI) const;
324 bool isVecUsableNextPacket(const MachineInstr *ProdMI,
325 const MachineInstr *ConsMI) const;
Krzysztof Parzyszekfd02aad2016-02-12 18:37:23 +0000[diff] [blame]326 bool isZeroExtendingLoad(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]327
328
Krzysztof Parzyszek56bbf542015-12-16 19:36:12 +0000[diff] [blame]329 bool canExecuteInBundle(const MachineInstr *First,
330 const MachineInstr *Second) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]331 bool hasEHLabel(const MachineBasicBlock *B) const;
332 bool hasNonExtEquivalent(const MachineInstr *MI) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]333 bool hasPseudoInstrPair(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]334 bool hasUncondBranch(const MachineBasicBlock *B) const;
335 bool mayBeCurLoad(const MachineInstr* MI) const;
336 bool mayBeNewStore(const MachineInstr* MI) const;
337 bool producesStall(const MachineInstr *ProdMI,
338 const MachineInstr *ConsMI) const;
339 bool producesStall(const MachineInstr *MI,
340 MachineBasicBlock::const_instr_iterator MII) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]341 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]342 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
343 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
344
345
Krzysztof Parzyszekf5cbac92016-04-29 15:49:13 +0000[diff] [blame]346 short getAbsoluteForm(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]347 unsigned getAddrMode(const MachineInstr* MI) const;
348 unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
349 unsigned &AccessSize) const;
350 bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
351 unsigned &OffsetPos) const;
Krzysztof Parzyszekf5cbac92016-04-29 15:49:13 +0000[diff] [blame]352 short getBaseWithLongOffset(short Opcode) const;
353 short getBaseWithLongOffset(const MachineInstr *MI) const;
354 short getBaseWithRegOffset(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]355 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
356 unsigned getCExtOpNum(const MachineInstr *MI) const;
357 HexagonII::CompoundGroup
358 getCompoundCandidateGroup(const MachineInstr *MI) const;
359 unsigned getCompoundOpcode(const MachineInstr *GA,
360 const MachineInstr *GB) const;
361 int getCondOpcode(int Opc, bool sense) const;
362 int getDotCurOp(const MachineInstr* MI) const;
363 int getDotNewOp(const MachineInstr* MI) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]364 int getDotNewPredJumpOp(const MachineInstr *MI,
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]365 const MachineBranchProbabilityInfo *MBPI) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]366 int getDotNewPredOp(const MachineInstr *MI,
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]367 const MachineBranchProbabilityInfo *MBPI) const;
368 int getDotOldOp(const int opc) const;
369 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
370 const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]371 short getEquivalentHWInstr(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]372 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
373 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
374 const MachineInstr *MI) const;
375 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
376 unsigned getInvertedPredicatedOpcode(const int Opc) const;
377 int getMaxValue(const MachineInstr *MI) const;
378 unsigned getMemAccessSize(const MachineInstr* MI) const;
379 int getMinValue(const MachineInstr *MI) const;
380 short getNonExtOpcode(const MachineInstr *MI) const;
381 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
382 unsigned &PredRegPos, unsigned &PredRegFlags) const;
Krzysztof Parzyszek5e6f2bd2015-12-14 21:32:25 +0000[diff] [blame]383 short getPseudoInstrPair(const MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]384 short getRegForm(const MachineInstr *MI) const;
385 unsigned getSize(const MachineInstr *MI) const;
386 uint64_t getType(const MachineInstr* MI) const;
387 unsigned getUnits(const MachineInstr* MI) const;
388 unsigned getValidSubTargets(const unsigned Opcode) const;
389
390
391 /// getInstrTimingClassLatency - Compute the instruction latency of a given
392 /// instruction using Timing Class information, if available.
393 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
394 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]395
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]396
397 void immediateExtend(MachineInstr *MI) const;
Krzysztof Parzyszekb9a1c3a2015-11-24 14:55:26 +0000[diff] [blame]398 bool invertAndChangeJumpTarget(MachineInstr* MI,
399 MachineBasicBlock* NewTarget) const;
400 void genAllInsnTimingClasses(MachineFunction &MF) const;
401 bool reversePredSense(MachineInstr* MI) const;
402 unsigned reversePrediction(unsigned Opcode) const;
403 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
Krzysztof Parzyszekf5cbac92016-04-29 15:49:13 +0000[diff] [blame]404 short xformRegToImmOffset(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]405};
406
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]407}
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]408
409#endif