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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / test / CodeGen / AArch64 / zero-reg.ll
blob: 62b2ea34ade15dcd04f753a08b4290f70e164fb6 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]2
3@var32 = global i32 0
4@var64 = global i64 0
5
6define void @test_zr() {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]7; CHECK-LABEL: test_zr:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]8
9 store i32 0, i32* @var32
Tim Northover46ecdf52014-04-16 11:53:07 +0000[diff] [blame]10; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]11 store i64 0, i64* @var64
Tim Northover46ecdf52014-04-16 11:53:07 +0000[diff] [blame]12; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]13
14 ret void
15; CHECK: ret
16}
17
18define void @test_sp(i32 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]19; CHECK-LABEL: test_sp:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]20
21; Important correctness point here is that LLVM doesn't try to use xzr
22; as an addressing register: "str w0, [xzr]" is not a valid A64
23; instruction (0b11111 in the Rn field would mean "sp").
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]24 %addr = getelementptr i32, i32* null, i64 0
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]25 store i32 %val, i32* %addr
Tim Northover46ecdf52014-04-16 11:53:07 +0000[diff] [blame]26; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]27
28 ret void
29; CHECK: ret
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]30}