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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / test / CodeGen / ARM / big-endian-neon-extend.ll
blob: f8542b708b8ad70082b2a9649eb8e18e10847577 [file] [log] [blame]
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]1; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
2
3define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
4; CHECK-LABEL: vector_ext_2i8_to_2i64:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]5; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]6; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
7; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
8; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
9; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame]10; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]11; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]12 %1 = load <2 x i8>, <2 x i8>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]13 %2 = zext <2 x i8> %1 to <2 x i64>
14 store <2 x i64> %2, <2 x i64>* %storeaddr
15 ret void
16}
17
18define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
19; CHECK-LABEL: vector_ext_2i16_to_2i64:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]20; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]21; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
22; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
23; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame]24; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]25; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]26 %1 = load <2 x i16>, <2 x i16>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]27 %2 = zext <2 x i16> %1 to <2 x i64>
28 store <2 x i64> %2, <2 x i64>* %storeaddr
29 ret void
30}
31
32
33define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
34; CHECK-LABEL: vector_ext_2i8_to_2i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]35; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
36; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
37; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
38; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
39; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
40; CHECK-NEXT: vstr [[REG]], [r1]
41; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]42 %1 = load <2 x i8>, <2 x i8>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]43 %2 = zext <2 x i8> %1 to <2 x i32>
44 store <2 x i32> %2, <2 x i32>* %storeaddr
45 ret void
46}
47
48define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
49; CHECK-LABEL: vector_ext_2i16_to_2i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]50; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
51; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
52; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
53; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
54; CHECK-NEXT: vstr [[REG]], [r1]
55; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]56 %1 = load <2 x i16>, <2 x i16>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]57 %2 = zext <2 x i16> %1 to <2 x i32>
58 store <2 x i32> %2, <2 x i32>* %storeaddr
59 ret void
60}
61
62define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
63; CHECK-LABEL: vector_ext_2i8_to_2i16:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]64; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
65; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
66; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
67; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
68; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame]69; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
70; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]71; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
72; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]73 %1 = load <2 x i8>, <2 x i8>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]74 %2 = zext <2 x i8> %1 to <2 x i16>
75 store <2 x i16> %2, <2 x i16>* %storeaddr
76 ret void
77}
78
79define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
80; CHECK-LABEL: vector_ext_4i8_to_4i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]81; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
82; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
83; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
84; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
85; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame]86; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]87; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]88 %1 = load <4 x i8>, <4 x i8>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]89 %2 = zext <4 x i8> %1 to <4 x i32>
90 store <4 x i32> %2, <4 x i32>* %storeaddr
91 ret void
92}
93
94define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
95; CHECK-LABEL: vector_ext_4i8_to_4i16:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]96; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
97; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
98; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
99; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
100; CHECK-NEXT: vstr [[REG]], [r1]
101; CHECK-NEXT: bx lr
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]102 %1 = load <4 x i8>, <4 x i8>* %loadaddr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]103 %2 = zext <4 x i8> %1 to <4 x i16>
104 store <4 x i16> %2, <4 x i16>* %storeaddr
105 ret void
106}