Clement Courbet | 44b4c54 | 2018-06-19 11:28:59 +0000 | [diff] [blame] | 1 | //===-- Target.cpp ----------------------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | #include "../Target.h" |
| 10 | |
Clement Courbet | 4860b98 | 2018-06-26 08:49:30 +0000 | [diff] [blame] | 11 | #include "../Latency.h" |
| 12 | #include "../Uops.h" |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 13 | #include "MCTargetDesc/X86BaseInfo.h" |
Clement Courbet | a51efc2 | 2018-06-25 13:12:02 +0000 | [diff] [blame] | 14 | #include "MCTargetDesc/X86MCTargetDesc.h" |
Clement Courbet | 6fd00e3 | 2018-06-20 11:54:35 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Clement Courbet | a51efc2 | 2018-06-25 13:12:02 +0000 | [diff] [blame] | 16 | #include "X86RegisterInfo.h" |
Clement Courbet | e785169 | 2018-07-03 06:17:05 +0000 | [diff] [blame] | 17 | #include "X86Subtarget.h" |
Clement Courbet | a51efc2 | 2018-06-25 13:12:02 +0000 | [diff] [blame] | 18 | #include "llvm/MC/MCInstBuilder.h" |
Clement Courbet | 6fd00e3 | 2018-06-20 11:54:35 +0000 | [diff] [blame] | 19 | |
Clement Courbet | 44b4c54 | 2018-06-19 11:28:59 +0000 | [diff] [blame] | 20 | namespace exegesis { |
| 21 | |
| 22 | namespace { |
| 23 | |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 24 | static llvm::Error IsInvalidOpcode(const Instruction &Instr) { |
| 25 | const auto OpcodeName = Instr.Name; |
| 26 | if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") || |
| 27 | OpcodeName.startswith("ADJCALLSTACK")) |
| 28 | return llvm::make_error<BenchmarkFailure>( |
| 29 | "Unsupported opcode: Push/Pop/AdjCallStack"); |
| 30 | return llvm::Error::success(); |
| 31 | } |
| 32 | |
| 33 | static unsigned GetX86FPFlags(const Instruction &Instr) { |
| 34 | return Instr.Description->TSFlags & llvm::X86II::FPTypeMask; |
| 35 | } |
| 36 | |
| 37 | class X86LatencySnippetGenerator : public LatencySnippetGenerator { |
| 38 | public: |
| 39 | using LatencySnippetGenerator::LatencySnippetGenerator; |
Clement Courbet | 4860b98 | 2018-06-26 08:49:30 +0000 | [diff] [blame] | 40 | |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 41 | llvm::Expected<std::vector<CodeTemplate>> |
| 42 | generateCodeTemplates(const Instruction &Instr) const override { |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 43 | if (auto E = IsInvalidOpcode(Instr)) |
| 44 | return std::move(E); |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 45 | |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 46 | switch (GetX86FPFlags(Instr)) { |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 47 | case llvm::X86II::NotFP: |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 48 | return LatencySnippetGenerator::generateCodeTemplates(Instr); |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 49 | case llvm::X86II::ZeroArgFP: |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 50 | case llvm::X86II::OneArgFP: |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 51 | case llvm::X86II::SpecialFP: |
| 52 | case llvm::X86II::CompareFP: |
| 53 | case llvm::X86II::CondMovFP: |
| 54 | return llvm::make_error<BenchmarkFailure>("Unsupported x87 Instruction"); |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 55 | case llvm::X86II::OneArgFPRW: |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 56 | case llvm::X86II::TwoArgFP: |
| 57 | // These are instructions like |
| 58 | // - `ST(0) = fsqrt(ST(0))` (OneArgFPRW) |
| 59 | // - `ST(0) = ST(0) + ST(i)` (TwoArgFP) |
| 60 | // They are intrinsically serial and do not modify the state of the stack. |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 61 | return generateSelfAliasingCodeTemplates(Instr); |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 62 | default: |
| 63 | llvm_unreachable("Unknown FP Type!"); |
| 64 | } |
| 65 | } |
| 66 | }; |
| 67 | |
| 68 | class X86UopsSnippetGenerator : public UopsSnippetGenerator { |
| 69 | public: |
| 70 | using UopsSnippetGenerator::UopsSnippetGenerator; |
| 71 | |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 72 | llvm::Expected<std::vector<CodeTemplate>> |
| 73 | generateCodeTemplates(const Instruction &Instr) const override { |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 74 | if (auto E = IsInvalidOpcode(Instr)) |
| 75 | return std::move(E); |
| 76 | |
| 77 | switch (GetX86FPFlags(Instr)) { |
| 78 | case llvm::X86II::NotFP: |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 79 | return UopsSnippetGenerator::generateCodeTemplates(Instr); |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 80 | case llvm::X86II::ZeroArgFP: |
| 81 | case llvm::X86II::OneArgFP: |
| 82 | case llvm::X86II::SpecialFP: |
| 83 | return llvm::make_error<BenchmarkFailure>("Unsupported x87 Instruction"); |
| 84 | case llvm::X86II::OneArgFPRW: |
| 85 | case llvm::X86II::TwoArgFP: |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 86 | // These are instructions like |
| 87 | // - `ST(0) = fsqrt(ST(0))` (OneArgFPRW) |
| 88 | // - `ST(0) = ST(0) + ST(i)` (TwoArgFP) |
| 89 | // They are intrinsically serial and do not modify the state of the stack. |
| 90 | // We generate the same code for latency and uops. |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 91 | return generateSelfAliasingCodeTemplates(Instr); |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 92 | case llvm::X86II::CompareFP: |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 93 | case llvm::X86II::CondMovFP: |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 94 | // We can compute uops for any FP instruction that does not grow or shrink |
| 95 | // the stack (either do not touch the stack or push as much as they pop). |
Guillaume Chatelet | 296a862 | 2018-10-15 09:09:19 +0000 | [diff] [blame] | 96 | return generateUnconstrainedCodeTemplates( |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 97 | Instr, "instruction does not grow/shrink the FP stack"); |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 98 | default: |
| 99 | llvm_unreachable("Unknown FP Type!"); |
| 100 | } |
Clement Courbet | 4860b98 | 2018-06-26 08:49:30 +0000 | [diff] [blame] | 101 | } |
| 102 | }; |
| 103 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 104 | static unsigned GetLoadImmediateOpcode(unsigned RegBitWidth) { |
| 105 | switch (RegBitWidth) { |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 106 | case 8: |
| 107 | return llvm::X86::MOV8ri; |
| 108 | case 16: |
| 109 | return llvm::X86::MOV16ri; |
| 110 | case 32: |
| 111 | return llvm::X86::MOV32ri; |
| 112 | case 64: |
| 113 | return llvm::X86::MOV64ri; |
| 114 | } |
| 115 | llvm_unreachable("Invalid Value Width"); |
| 116 | } |
| 117 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 118 | // Generates instruction to load an immediate value into a register. |
| 119 | static llvm::MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth, |
| 120 | const llvm::APInt &Value) { |
| 121 | if (Value.getBitWidth() > RegBitWidth) |
| 122 | llvm_unreachable("Value must fit in the Register"); |
| 123 | return llvm::MCInstBuilder(GetLoadImmediateOpcode(RegBitWidth)) |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 124 | .addReg(Reg) |
| 125 | .addImm(Value.getZExtValue()); |
| 126 | } |
| 127 | |
| 128 | // Allocates scratch memory on the stack. |
| 129 | static llvm::MCInst allocateStackSpace(unsigned Bytes) { |
| 130 | return llvm::MCInstBuilder(llvm::X86::SUB64ri8) |
| 131 | .addReg(llvm::X86::RSP) |
| 132 | .addReg(llvm::X86::RSP) |
| 133 | .addImm(Bytes); |
| 134 | } |
| 135 | |
| 136 | // Fills scratch memory at offset `OffsetBytes` with value `Imm`. |
| 137 | static llvm::MCInst fillStackSpace(unsigned MovOpcode, unsigned OffsetBytes, |
| 138 | uint64_t Imm) { |
| 139 | return llvm::MCInstBuilder(MovOpcode) |
| 140 | // Address = ESP |
| 141 | .addReg(llvm::X86::RSP) // BaseReg |
| 142 | .addImm(1) // ScaleAmt |
| 143 | .addReg(0) // IndexReg |
| 144 | .addImm(OffsetBytes) // Disp |
| 145 | .addReg(0) // Segment |
| 146 | // Immediate. |
| 147 | .addImm(Imm); |
| 148 | } |
| 149 | |
| 150 | // Loads scratch memory into register `Reg` using opcode `RMOpcode`. |
| 151 | static llvm::MCInst loadToReg(unsigned Reg, unsigned RMOpcode) { |
| 152 | return llvm::MCInstBuilder(RMOpcode) |
| 153 | .addReg(Reg) |
| 154 | // Address = ESP |
| 155 | .addReg(llvm::X86::RSP) // BaseReg |
| 156 | .addImm(1) // ScaleAmt |
| 157 | .addReg(0) // IndexReg |
| 158 | .addImm(0) // Disp |
| 159 | .addReg(0); // Segment |
| 160 | } |
| 161 | |
| 162 | // Releases scratch memory. |
| 163 | static llvm::MCInst releaseStackSpace(unsigned Bytes) { |
| 164 | return llvm::MCInstBuilder(llvm::X86::ADD64ri8) |
| 165 | .addReg(llvm::X86::RSP) |
| 166 | .addReg(llvm::X86::RSP) |
| 167 | .addImm(Bytes); |
| 168 | } |
| 169 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 170 | // Reserves some space on the stack, fills it with the content of the provided |
| 171 | // constant and provide methods to load the stack value into a register. |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 172 | struct ConstantInliner { |
Clement Courbet | 78b2e73 | 2018-09-25 07:31:44 +0000 | [diff] [blame] | 173 | explicit ConstantInliner(const llvm::APInt &Constant) : Constant_(Constant) {} |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 174 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 175 | std::vector<llvm::MCInst> loadAndFinalize(unsigned Reg, unsigned RegBitWidth, |
| 176 | unsigned Opcode) { |
Clement Courbet | 78b2e73 | 2018-09-25 07:31:44 +0000 | [diff] [blame] | 177 | assert((RegBitWidth & 7) == 0 && |
| 178 | "RegBitWidth must be a multiple of 8 bits"); |
| 179 | initStack(RegBitWidth / 8); |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 180 | add(loadToReg(Reg, Opcode)); |
Clement Courbet | 78b2e73 | 2018-09-25 07:31:44 +0000 | [diff] [blame] | 181 | add(releaseStackSpace(RegBitWidth / 8)); |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 182 | return std::move(Instructions); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 183 | } |
| 184 | |
Clement Courbet | c51f452 | 2018-10-19 09:56:54 +0000 | [diff] [blame^] | 185 | std::vector<llvm::MCInst> loadX87STAndFinalize(unsigned Reg) { |
| 186 | initStack(kF80Bytes); |
| 187 | add(llvm::MCInstBuilder(llvm::X86::LD_F80m) |
| 188 | // Address = ESP |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 189 | .addReg(llvm::X86::RSP) // BaseReg |
| 190 | .addImm(1) // ScaleAmt |
| 191 | .addReg(0) // IndexReg |
| 192 | .addImm(0) // Disp |
| 193 | .addReg(0)); // Segment |
| 194 | if (Reg != llvm::X86::ST0) |
| 195 | add(llvm::MCInstBuilder(llvm::X86::ST_Frr).addReg(Reg)); |
Clement Courbet | c51f452 | 2018-10-19 09:56:54 +0000 | [diff] [blame^] | 196 | add(releaseStackSpace(kF80Bytes)); |
| 197 | return std::move(Instructions); |
| 198 | } |
| 199 | |
| 200 | std::vector<llvm::MCInst> loadX87FPAndFinalize(unsigned Reg) { |
| 201 | initStack(kF80Bytes); |
| 202 | add(llvm::MCInstBuilder(llvm::X86::LD_Fp80m) |
| 203 | .addReg(Reg) |
| 204 | // Address = ESP |
| 205 | .addReg(llvm::X86::RSP) // BaseReg |
| 206 | .addImm(1) // ScaleAmt |
| 207 | .addReg(0) // IndexReg |
| 208 | .addImm(0) // Disp |
| 209 | .addReg(0)); // Segment |
| 210 | add(releaseStackSpace(kF80Bytes)); |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 211 | return std::move(Instructions); |
| 212 | } |
| 213 | |
| 214 | std::vector<llvm::MCInst> popFlagAndFinalize() { |
Clement Courbet | 78b2e73 | 2018-09-25 07:31:44 +0000 | [diff] [blame] | 215 | initStack(8); |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 216 | add(llvm::MCInstBuilder(llvm::X86::POPF64)); |
Simon Pilgrim | f652ef3 | 2018-09-18 15:38:16 +0000 | [diff] [blame] | 217 | return std::move(Instructions); |
| 218 | } |
| 219 | |
| 220 | private: |
Clement Courbet | c51f452 | 2018-10-19 09:56:54 +0000 | [diff] [blame^] | 221 | static constexpr const unsigned kF80Bytes = 10; // 80 bits. |
| 222 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 223 | ConstantInliner &add(const llvm::MCInst &Inst) { |
| 224 | Instructions.push_back(Inst); |
| 225 | return *this; |
| 226 | } |
| 227 | |
Clement Courbet | 78b2e73 | 2018-09-25 07:31:44 +0000 | [diff] [blame] | 228 | void initStack(unsigned Bytes) { |
| 229 | assert(Constant_.getBitWidth() <= Bytes * 8 && |
| 230 | "Value does not have the correct size"); |
| 231 | const llvm::APInt WideConstant = Constant_.getBitWidth() < Bytes * 8 |
| 232 | ? Constant_.sext(Bytes * 8) |
| 233 | : Constant_; |
| 234 | add(allocateStackSpace(Bytes)); |
| 235 | size_t ByteOffset = 0; |
| 236 | for (; Bytes - ByteOffset >= 4; ByteOffset += 4) |
| 237 | add(fillStackSpace( |
| 238 | llvm::X86::MOV32mi, ByteOffset, |
| 239 | WideConstant.extractBits(32, ByteOffset * 8).getZExtValue())); |
| 240 | if (Bytes - ByteOffset >= 2) { |
| 241 | add(fillStackSpace( |
| 242 | llvm::X86::MOV16mi, ByteOffset, |
| 243 | WideConstant.extractBits(16, ByteOffset * 8).getZExtValue())); |
| 244 | ByteOffset += 2; |
| 245 | } |
| 246 | if (Bytes - ByteOffset >= 1) |
| 247 | add(fillStackSpace( |
| 248 | llvm::X86::MOV8mi, ByteOffset, |
| 249 | WideConstant.extractBits(8, ByteOffset * 8).getZExtValue())); |
| 250 | } |
| 251 | |
| 252 | llvm::APInt Constant_; |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 253 | std::vector<llvm::MCInst> Instructions; |
| 254 | }; |
| 255 | |
Clement Courbet | 44b4c54 | 2018-06-19 11:28:59 +0000 | [diff] [blame] | 256 | class ExegesisX86Target : public ExegesisTarget { |
Clement Courbet | 6fd00e3 | 2018-06-20 11:54:35 +0000 | [diff] [blame] | 257 | void addTargetSpecificPasses(llvm::PassManagerBase &PM) const override { |
| 258 | // Lowers FP pseudo-instructions, e.g. ABS_Fp32 -> ABS_F. |
Clement Courbet | 717c976 | 2018-06-28 07:41:16 +0000 | [diff] [blame] | 259 | PM.add(llvm::createX86FloatingPointStackifierPass()); |
Clement Courbet | 6fd00e3 | 2018-06-20 11:54:35 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Guillaume Chatelet | fb94354 | 2018-08-01 14:41:45 +0000 | [diff] [blame] | 262 | unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override { |
| 263 | if (!TT.isArch64Bit()) { |
| 264 | // FIXME: This would require popping from the stack, so we would have to |
| 265 | // add some additional setup code. |
| 266 | return 0; |
| 267 | } |
| 268 | return TT.isOSWindows() ? llvm::X86::RCX : llvm::X86::RDI; |
| 269 | } |
| 270 | |
| 271 | unsigned getMaxMemoryAccessSize() const override { return 64; } |
| 272 | |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 273 | void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg, |
Guillaume Chatelet | fb94354 | 2018-08-01 14:41:45 +0000 | [diff] [blame] | 274 | unsigned Offset) const override { |
| 275 | // FIXME: For instructions that read AND write to memory, we use the same |
| 276 | // value for input and output. |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 277 | for (size_t I = 0, E = IT.Instr.Operands.size(); I < E; ++I) { |
| 278 | const Operand *Op = &IT.Instr.Operands[I]; |
Guillaume Chatelet | 09c2839 | 2018-10-09 08:59:10 +0000 | [diff] [blame] | 279 | if (Op->isExplicit() && Op->isMemory()) { |
Guillaume Chatelet | fb94354 | 2018-08-01 14:41:45 +0000 | [diff] [blame] | 280 | // Case 1: 5-op memory. |
| 281 | assert((I + 5 <= E) && "x86 memory references are always 5 ops"); |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 282 | IT.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg |
| 283 | Op = &IT.Instr.Operands[++I]; |
Guillaume Chatelet | 09c2839 | 2018-10-09 08:59:10 +0000 | [diff] [blame] | 284 | assert(Op->isMemory()); |
| 285 | assert(Op->isExplicit()); |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 286 | IT.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt |
| 287 | Op = &IT.Instr.Operands[++I]; |
Guillaume Chatelet | 09c2839 | 2018-10-09 08:59:10 +0000 | [diff] [blame] | 288 | assert(Op->isMemory()); |
| 289 | assert(Op->isExplicit()); |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 290 | IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg |
| 291 | Op = &IT.Instr.Operands[++I]; |
Guillaume Chatelet | 09c2839 | 2018-10-09 08:59:10 +0000 | [diff] [blame] | 292 | assert(Op->isMemory()); |
| 293 | assert(Op->isExplicit()); |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 294 | IT.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp |
| 295 | Op = &IT.Instr.Operands[++I]; |
Guillaume Chatelet | 09c2839 | 2018-10-09 08:59:10 +0000 | [diff] [blame] | 296 | assert(Op->isMemory()); |
| 297 | assert(Op->isExplicit()); |
Guillaume Chatelet | 70ac019 | 2018-09-27 09:23:04 +0000 | [diff] [blame] | 298 | IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment |
Guillaume Chatelet | fb94354 | 2018-08-01 14:41:45 +0000 | [diff] [blame] | 299 | // Case2: segment:index addressing. We assume that ES is 0. |
| 300 | } |
| 301 | } |
| 302 | } |
| 303 | |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 304 | std::vector<llvm::MCInst> setRegTo(const llvm::MCSubtargetInfo &STI, |
| 305 | unsigned Reg, |
| 306 | const llvm::APInt &Value) const override { |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 307 | if (llvm::X86::GR8RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 308 | return {loadImmediate(Reg, 8, Value)}; |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 309 | if (llvm::X86::GR16RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 310 | return {loadImmediate(Reg, 16, Value)}; |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 311 | if (llvm::X86::GR32RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 312 | return {loadImmediate(Reg, 32, Value)}; |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 313 | if (llvm::X86::GR64RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 314 | return {loadImmediate(Reg, 64, Value)}; |
| 315 | ConstantInliner CI(Value); |
Guillaume Chatelet | 5ad2909 | 2018-09-18 11:26:27 +0000 | [diff] [blame] | 316 | if (llvm::X86::VR64RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 317 | return CI.loadAndFinalize(Reg, 64, llvm::X86::MMX_MOVQ64rm); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 318 | if (llvm::X86::VR128XRegClass.contains(Reg)) { |
| 319 | if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 320 | return CI.loadAndFinalize(Reg, 128, llvm::X86::VMOVDQU32Z128rm); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 321 | if (STI.getFeatureBits()[llvm::X86::FeatureAVX]) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 322 | return CI.loadAndFinalize(Reg, 128, llvm::X86::VMOVDQUrm); |
| 323 | return CI.loadAndFinalize(Reg, 128, llvm::X86::MOVDQUrm); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 324 | } |
| 325 | if (llvm::X86::VR256XRegClass.contains(Reg)) { |
| 326 | if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 327 | return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQU32Z256rm); |
| 328 | if (STI.getFeatureBits()[llvm::X86::FeatureAVX]) |
| 329 | return CI.loadAndFinalize(Reg, 256, llvm::X86::VMOVDQUYrm); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 330 | } |
| 331 | if (llvm::X86::VR512RegClass.contains(Reg)) |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 332 | if (STI.getFeatureBits()[llvm::X86::FeatureAVX512]) |
| 333 | return CI.loadAndFinalize(Reg, 512, llvm::X86::VMOVDQU32Zrm); |
| 334 | if (llvm::X86::RSTRegClass.contains(Reg)) { |
Clement Courbet | c51f452 | 2018-10-19 09:56:54 +0000 | [diff] [blame^] | 335 | return CI.loadX87STAndFinalize(Reg); |
| 336 | } |
| 337 | if (llvm::X86::RFP32RegClass.contains(Reg) || |
| 338 | llvm::X86::RFP64RegClass.contains(Reg) || |
| 339 | llvm::X86::RFP80RegClass.contains(Reg)) { |
| 340 | return CI.loadX87FPAndFinalize(Reg); |
Guillaume Chatelet | 8721ad9 | 2018-09-18 11:26:35 +0000 | [diff] [blame] | 341 | } |
Guillaume Chatelet | c96a97b | 2018-09-20 12:22:18 +0000 | [diff] [blame] | 342 | if (Reg == llvm::X86::EFLAGS) |
| 343 | return CI.popFlagAndFinalize(); |
| 344 | return {}; // Not yet implemented. |
Clement Courbet | a51efc2 | 2018-06-25 13:12:02 +0000 | [diff] [blame] | 345 | } |
| 346 | |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 347 | std::unique_ptr<SnippetGenerator> |
| 348 | createLatencySnippetGenerator(const LLVMState &State) const override { |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 349 | return llvm::make_unique<X86LatencySnippetGenerator>(State); |
Clement Courbet | 4860b98 | 2018-06-26 08:49:30 +0000 | [diff] [blame] | 350 | } |
| 351 | |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 352 | std::unique_ptr<SnippetGenerator> |
| 353 | createUopsSnippetGenerator(const LLVMState &State) const override { |
Guillaume Chatelet | 946fb05 | 2018-10-12 15:12:22 +0000 | [diff] [blame] | 354 | return llvm::make_unique<X86UopsSnippetGenerator>(State); |
Clement Courbet | 4860b98 | 2018-06-26 08:49:30 +0000 | [diff] [blame] | 355 | } |
| 356 | |
Clement Courbet | 44b4c54 | 2018-06-19 11:28:59 +0000 | [diff] [blame] | 357 | bool matchesArch(llvm::Triple::ArchType Arch) const override { |
| 358 | return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86; |
| 359 | } |
| 360 | }; |
| 361 | |
| 362 | } // namespace |
| 363 | |
Clement Courbet | cff2caa | 2018-06-25 11:22:23 +0000 | [diff] [blame] | 364 | static ExegesisTarget *getTheExegesisX86Target() { |
Clement Courbet | 44b4c54 | 2018-06-19 11:28:59 +0000 | [diff] [blame] | 365 | static ExegesisX86Target Target; |
| 366 | return &Target; |
| 367 | } |
| 368 | |
| 369 | void InitializeX86ExegesisTarget() { |
| 370 | ExegesisTarget::registerTarget(getTheExegesisX86Target()); |
| 371 | } |
| 372 | |
Clement Courbet | cff2caa | 2018-06-25 11:22:23 +0000 | [diff] [blame] | 373 | } // namespace exegesis |