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gerrit-public.fairphone.software / toolchain / llvm-project / cc08e1fe1b3feef12a1eba31f8afcc3bbefc733e / . / llvm / lib / Target / ARM64 / Utils / ARM64BaseInfo.h
blob: 8075d6b37c9a1b267b3c2fb05b3728e260ba64ee [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the ARM64 target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef ARM64BASEINFO_H
18#define ARM64BASEINFO_H
19
Bradley Smith2ba17a42014-04-09 14:42:27 +0000[diff] [blame]20// FIXME: Is it easiest to fix this layering violation by moving the .inc
21// #includes from ARM64MCTargetDesc.h to here?
22#include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and friends.
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringSwitch.h"
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
26
27namespace llvm {
28
29inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
31 case ARM64::X0: return ARM64::W0;
32 case ARM64::X1: return ARM64::W1;
33 case ARM64::X2: return ARM64::W2;
34 case ARM64::X3: return ARM64::W3;
35 case ARM64::X4: return ARM64::W4;
36 case ARM64::X5: return ARM64::W5;
37 case ARM64::X6: return ARM64::W6;
38 case ARM64::X7: return ARM64::W7;
39 case ARM64::X8: return ARM64::W8;
40 case ARM64::X9: return ARM64::W9;
41 case ARM64::X10: return ARM64::W10;
42 case ARM64::X11: return ARM64::W11;
43 case ARM64::X12: return ARM64::W12;
44 case ARM64::X13: return ARM64::W13;
45 case ARM64::X14: return ARM64::W14;
46 case ARM64::X15: return ARM64::W15;
47 case ARM64::X16: return ARM64::W16;
48 case ARM64::X17: return ARM64::W17;
49 case ARM64::X18: return ARM64::W18;
50 case ARM64::X19: return ARM64::W19;
51 case ARM64::X20: return ARM64::W20;
52 case ARM64::X21: return ARM64::W21;
53 case ARM64::X22: return ARM64::W22;
54 case ARM64::X23: return ARM64::W23;
55 case ARM64::X24: return ARM64::W24;
56 case ARM64::X25: return ARM64::W25;
57 case ARM64::X26: return ARM64::W26;
58 case ARM64::X27: return ARM64::W27;
59 case ARM64::X28: return ARM64::W28;
60 case ARM64::FP: return ARM64::W29;
61 case ARM64::LR: return ARM64::W30;
62 case ARM64::SP: return ARM64::WSP;
63 case ARM64::XZR: return ARM64::WZR;
64 }
65 // For anything else, return it unchanged.
66 return Reg;
67}
68
69inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
71 case ARM64::W0: return ARM64::X0;
72 case ARM64::W1: return ARM64::X1;
73 case ARM64::W2: return ARM64::X2;
74 case ARM64::W3: return ARM64::X3;
75 case ARM64::W4: return ARM64::X4;
76 case ARM64::W5: return ARM64::X5;
77 case ARM64::W6: return ARM64::X6;
78 case ARM64::W7: return ARM64::X7;
79 case ARM64::W8: return ARM64::X8;
80 case ARM64::W9: return ARM64::X9;
81 case ARM64::W10: return ARM64::X10;
82 case ARM64::W11: return ARM64::X11;
83 case ARM64::W12: return ARM64::X12;
84 case ARM64::W13: return ARM64::X13;
85 case ARM64::W14: return ARM64::X14;
86 case ARM64::W15: return ARM64::X15;
87 case ARM64::W16: return ARM64::X16;
88 case ARM64::W17: return ARM64::X17;
89 case ARM64::W18: return ARM64::X18;
90 case ARM64::W19: return ARM64::X19;
91 case ARM64::W20: return ARM64::X20;
92 case ARM64::W21: return ARM64::X21;
93 case ARM64::W22: return ARM64::X22;
94 case ARM64::W23: return ARM64::X23;
95 case ARM64::W24: return ARM64::X24;
96 case ARM64::W25: return ARM64::X25;
97 case ARM64::W26: return ARM64::X26;
98 case ARM64::W27: return ARM64::X27;
99 case ARM64::W28: return ARM64::X28;
100 case ARM64::W29: return ARM64::FP;
101 case ARM64::W30: return ARM64::LR;
102 case ARM64::WSP: return ARM64::SP;
103 case ARM64::WZR: return ARM64::XZR;
104 }
105 // For anything else, return it unchanged.
106 return Reg;
107}
108
109static inline unsigned getBRegFromDReg(unsigned Reg) {
110 switch (Reg) {
111 case ARM64::D0: return ARM64::B0;
112 case ARM64::D1: return ARM64::B1;
113 case ARM64::D2: return ARM64::B2;
114 case ARM64::D3: return ARM64::B3;
115 case ARM64::D4: return ARM64::B4;
116 case ARM64::D5: return ARM64::B5;
117 case ARM64::D6: return ARM64::B6;
118 case ARM64::D7: return ARM64::B7;
119 case ARM64::D8: return ARM64::B8;
120 case ARM64::D9: return ARM64::B9;
121 case ARM64::D10: return ARM64::B10;
122 case ARM64::D11: return ARM64::B11;
123 case ARM64::D12: return ARM64::B12;
124 case ARM64::D13: return ARM64::B13;
125 case ARM64::D14: return ARM64::B14;
126 case ARM64::D15: return ARM64::B15;
127 case ARM64::D16: return ARM64::B16;
128 case ARM64::D17: return ARM64::B17;
129 case ARM64::D18: return ARM64::B18;
130 case ARM64::D19: return ARM64::B19;
131 case ARM64::D20: return ARM64::B20;
132 case ARM64::D21: return ARM64::B21;
133 case ARM64::D22: return ARM64::B22;
134 case ARM64::D23: return ARM64::B23;
135 case ARM64::D24: return ARM64::B24;
136 case ARM64::D25: return ARM64::B25;
137 case ARM64::D26: return ARM64::B26;
138 case ARM64::D27: return ARM64::B27;
139 case ARM64::D28: return ARM64::B28;
140 case ARM64::D29: return ARM64::B29;
141 case ARM64::D30: return ARM64::B30;
142 case ARM64::D31: return ARM64::B31;
143 }
144 // For anything else, return it unchanged.
145 return Reg;
146}
147
148
149static inline unsigned getDRegFromBReg(unsigned Reg) {
150 switch (Reg) {
151 case ARM64::B0: return ARM64::D0;
152 case ARM64::B1: return ARM64::D1;
153 case ARM64::B2: return ARM64::D2;
154 case ARM64::B3: return ARM64::D3;
155 case ARM64::B4: return ARM64::D4;
156 case ARM64::B5: return ARM64::D5;
157 case ARM64::B6: return ARM64::D6;
158 case ARM64::B7: return ARM64::D7;
159 case ARM64::B8: return ARM64::D8;
160 case ARM64::B9: return ARM64::D9;
161 case ARM64::B10: return ARM64::D10;
162 case ARM64::B11: return ARM64::D11;
163 case ARM64::B12: return ARM64::D12;
164 case ARM64::B13: return ARM64::D13;
165 case ARM64::B14: return ARM64::D14;
166 case ARM64::B15: return ARM64::D15;
167 case ARM64::B16: return ARM64::D16;
168 case ARM64::B17: return ARM64::D17;
169 case ARM64::B18: return ARM64::D18;
170 case ARM64::B19: return ARM64::D19;
171 case ARM64::B20: return ARM64::D20;
172 case ARM64::B21: return ARM64::D21;
173 case ARM64::B22: return ARM64::D22;
174 case ARM64::B23: return ARM64::D23;
175 case ARM64::B24: return ARM64::D24;
176 case ARM64::B25: return ARM64::D25;
177 case ARM64::B26: return ARM64::D26;
178 case ARM64::B27: return ARM64::D27;
179 case ARM64::B28: return ARM64::D28;
180 case ARM64::B29: return ARM64::D29;
181 case ARM64::B30: return ARM64::D30;
182 case ARM64::B31: return ARM64::D31;
183 }
184 // For anything else, return it unchanged.
185 return Reg;
186}
187
188namespace ARM64CC {
189
190// The CondCodes constants map directly to the 4-bit encoding of the condition
191// field for predicated instructions.
192enum CondCode { // Meaning (integer) Meaning (floating-point)
193 EQ = 0x0, // Equal Equal
194 NE = 0x1, // Not equal Not equal, or unordered
Tim Northover20ad3592014-04-30 13:14:03 +0000[diff] [blame]195 HS = 0x2, // Unsigned higher or same >, ==, or unordered
196 LO = 0x3, // Unsigned lower Less than
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]197 MI = 0x4, // Minus, negative Less than
198 PL = 0x5, // Plus, positive or zero >, ==, or unordered
199 VS = 0x6, // Overflow Unordered
200 VC = 0x7, // No overflow Not unordered
201 HI = 0x8, // Unsigned higher Greater than, or unordered
202 LS = 0x9, // Unsigned lower or same Less than or equal
203 GE = 0xa, // Greater than or equal Greater than or equal
204 LT = 0xb, // Less than Less than, or unordered
205 GT = 0xc, // Greater than Greater than
206 LE = 0xd, // Less than or equal <, ==, or unordered
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]207 AL = 0xe, // Always (unconditional) Always (unconditional)
208 NV = 0xf, // Always (unconditional) Always (unconditional)
209 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
210 Invalid
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]211};
212
213inline static const char *getCondCodeName(CondCode Code) {
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]214 switch (Code) {
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]215 default: llvm_unreachable("Unknown condition code");
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]216 case EQ: return "eq";
217 case NE: return "ne";
Tim Northover20ad3592014-04-30 13:14:03 +0000[diff] [blame]218 case HS: return "hs";
219 case LO: return "lo";
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]220 case MI: return "mi";
221 case PL: return "pl";
222 case VS: return "vs";
223 case VC: return "vc";
224 case HI: return "hi";
225 case LS: return "ls";
226 case GE: return "ge";
227 case LT: return "lt";
228 case GT: return "gt";
229 case LE: return "le";
230 case AL: return "al";
Bradley Smith527bf862014-04-09 14:42:07 +0000[diff] [blame]231 case NV: return "nv";
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]232 }
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]233}
234
235inline static CondCode getInvertedCondCode(CondCode Code) {
236 switch (Code) {
237 default: llvm_unreachable("Unknown condition code");
238 case EQ: return NE;
239 case NE: return EQ;
Tim Northover20ad3592014-04-30 13:14:03 +0000[diff] [blame]240 case HS: return LO;
241 case LO: return HS;
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]242 case MI: return PL;
243 case PL: return MI;
244 case VS: return VC;
245 case VC: return VS;
246 case HI: return LS;
247 case LS: return HI;
248 case GE: return LT;
249 case LT: return GE;
250 case GT: return LE;
251 case LE: return GT;
252 }
253}
254
255/// Given a condition code, return NZCV flags that would satisfy that condition.
256/// The flag bits are in the format expected by the ccmp instructions.
257/// Note that many different flag settings can satisfy a given condition code,
258/// this function just returns one of them.
259inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
260 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
261 enum { N = 8, Z = 4, C = 2, V = 1 };
262 switch (Code) {
263 default: llvm_unreachable("Unknown condition code");
264 case EQ: return Z; // Z == 1
265 case NE: return 0; // Z == 0
Tim Northover20ad3592014-04-30 13:14:03 +0000[diff] [blame]266 case HS: return C; // C == 1
267 case LO: return 0; // C == 0
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]268 case MI: return N; // N == 1
269 case PL: return 0; // N == 0
270 case VS: return V; // V == 1
271 case VC: return 0; // V == 0
272 case HI: return C; // C == 1 && Z == 0
273 case LS: return 0; // C == 0 || Z == 1
274 case GE: return 0; // N == V
275 case LT: return N; // N != V
276 case GT: return 0; // Z == 0 && N == V
277 case LE: return Z; // Z == 1 || N != V
278 }
279}
280} // end namespace ARM64CC
281
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]282/// Instances of this class can perform bidirectional mapping from random
283/// identifier strings to operand encodings. For example "MSR" takes a named
284/// system-register which must be encoded somehow and decoded for printing. This
285/// central location means that the information for those transformations is not
286/// duplicated and remains in sync.
287///
288/// FIXME: currently the algorithm is a completely unoptimised linear
289/// search. Obviously this could be improved, but we would probably want to work
290/// out just how often these instructions are emitted before working on it. It
291/// might even be optimal to just reorder the tables for the common instructions
292/// rather than changing the algorithm.
293struct ARM64NamedImmMapper {
294 struct Mapping {
295 const char *Name;
296 uint32_t Value;
297 };
298
299 template<int N>
300 ARM64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
301 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
302
303 StringRef toString(uint32_t Value, bool &Valid) const;
304 uint32_t fromString(StringRef Name, bool &Valid) const;
305
306 /// Many of the instructions allow an alternative assembly form consisting of
307 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
308 /// N being 0 indicates no immediate syntax-form is allowed.
309 bool validImm(uint32_t Value) const;
310protected:
311 const Mapping *Pairs;
312 size_t NumPairs;
313 uint32_t TooBigImm;
314};
315
316namespace ARM64AT {
317 enum ATValues {
318 Invalid = -1, // Op0 Op1 CRn CRm Op2
319 S1E1R = 0x43c0, // 01 000 0111 1000 000
320 S1E2R = 0x63c0, // 01 100 0111 1000 000
321 S1E3R = 0x73c0, // 01 110 0111 1000 000
322 S1E1W = 0x43c1, // 01 000 0111 1000 001
323 S1E2W = 0x63c1, // 01 100 0111 1000 001
324 S1E3W = 0x73c1, // 01 110 0111 1000 001
325 S1E0R = 0x43c2, // 01 000 0111 1000 010
326 S1E0W = 0x43c3, // 01 000 0111 1000 011
327 S12E1R = 0x63c4, // 01 100 0111 1000 100
328 S12E1W = 0x63c5, // 01 100 0111 1000 101
329 S12E0R = 0x63c6, // 01 100 0111 1000 110
330 S12E0W = 0x63c7 // 01 100 0111 1000 111
331 };
332
333 struct ATMapper : ARM64NamedImmMapper {
334 const static Mapping ATPairs[];
335
336 ATMapper();
337 };
338
339}
340namespace ARM64DB {
341 enum DBValues {
342 Invalid = -1,
343 OSHLD = 0x1,
344 OSHST = 0x2,
345 OSH = 0x3,
346 NSHLD = 0x5,
347 NSHST = 0x6,
348 NSH = 0x7,
349 ISHLD = 0x9,
350 ISHST = 0xa,
351 ISH = 0xb,
352 LD = 0xd,
353 ST = 0xe,
354 SY = 0xf
355 };
356
357 struct DBarrierMapper : ARM64NamedImmMapper {
358 const static Mapping DBarrierPairs[];
359
360 DBarrierMapper();
361 };
362}
363
364namespace ARM64DC {
365 enum DCValues {
366 Invalid = -1, // Op1 CRn CRm Op2
367 ZVA = 0x5ba1, // 01 011 0111 0100 001
368 IVAC = 0x43b1, // 01 000 0111 0110 001
369 ISW = 0x43b2, // 01 000 0111 0110 010
370 CVAC = 0x5bd1, // 01 011 0111 1010 001
371 CSW = 0x43d2, // 01 000 0111 1010 010
372 CVAU = 0x5bd9, // 01 011 0111 1011 001
373 CIVAC = 0x5bf1, // 01 011 0111 1110 001
374 CISW = 0x43f2 // 01 000 0111 1110 010
375 };
376
377 struct DCMapper : ARM64NamedImmMapper {
378 const static Mapping DCPairs[];
379
380 DCMapper();
381 };
382
383}
384
385namespace ARM64IC {
386 enum ICValues {
387 Invalid = -1, // Op1 CRn CRm Op2
388 IALLUIS = 0x0388, // 000 0111 0001 000
389 IALLU = 0x03a8, // 000 0111 0101 000
390 IVAU = 0x1ba9 // 011 0111 0101 001
391 };
392
393
394 struct ICMapper : ARM64NamedImmMapper {
395 const static Mapping ICPairs[];
396
397 ICMapper();
398 };
399
400 static inline bool NeedsRegister(ICValues Val) {
401 return Val == IVAU;
402 }
403}
404
405namespace ARM64ISB {
406 enum ISBValues {
407 Invalid = -1,
408 SY = 0xf
409 };
410 struct ISBMapper : ARM64NamedImmMapper {
411 const static Mapping ISBPairs[];
412
413 ISBMapper();
414 };
415}
416
417namespace ARM64PRFM {
418 enum PRFMValues {
419 Invalid = -1,
420 PLDL1KEEP = 0x00,
421 PLDL1STRM = 0x01,
422 PLDL2KEEP = 0x02,
423 PLDL2STRM = 0x03,
424 PLDL3KEEP = 0x04,
425 PLDL3STRM = 0x05,
426 PLIL1KEEP = 0x08,
427 PLIL1STRM = 0x09,
428 PLIL2KEEP = 0x0a,
429 PLIL2STRM = 0x0b,
430 PLIL3KEEP = 0x0c,
431 PLIL3STRM = 0x0d,
432 PSTL1KEEP = 0x10,
433 PSTL1STRM = 0x11,
434 PSTL2KEEP = 0x12,
435 PSTL2STRM = 0x13,
436 PSTL3KEEP = 0x14,
437 PSTL3STRM = 0x15
438 };
439
440 struct PRFMMapper : ARM64NamedImmMapper {
441 const static Mapping PRFMPairs[];
442
443 PRFMMapper();
444 };
445}
446
447namespace ARM64PState {
448 enum PStateValues {
449 Invalid = -1,
450 SPSel = 0x05,
451 DAIFSet = 0x1e,
452 DAIFClr = 0x1f
453 };
454
455 struct PStateMapper : ARM64NamedImmMapper {
456 const static Mapping PStatePairs[];
457
458 PStateMapper();
459 };
460
461}
462
463namespace ARM64SE {
464 enum ShiftExtSpecifiers {
465 Invalid = -1,
466 LSL,
467 MSL,
468 LSR,
469 ASR,
470 ROR,
471
472 UXTB,
473 UXTH,
474 UXTW,
475 UXTX,
476
477 SXTB,
478 SXTH,
479 SXTW,
480 SXTX
481 };
482}
483
484namespace ARM64Layout {
485 enum VectorLayout {
486 Invalid = -1,
487 VL_8B,
488 VL_4H,
489 VL_2S,
490 VL_1D,
491
492 VL_16B,
493 VL_8H,
494 VL_4S,
495 VL_2D,
496
497 // Bare layout for the 128-bit vector
498 // (only show ".b", ".h", ".s", ".d" without vector number)
499 VL_B,
500 VL_H,
501 VL_S,
502 VL_D
503 };
504}
505
506inline static const char *
507ARM64VectorLayoutToString(ARM64Layout::VectorLayout Layout) {
508 switch (Layout) {
509 case ARM64Layout::VL_8B: return ".8b";
510 case ARM64Layout::VL_4H: return ".4h";
511 case ARM64Layout::VL_2S: return ".2s";
512 case ARM64Layout::VL_1D: return ".1d";
513 case ARM64Layout::VL_16B: return ".16b";
514 case ARM64Layout::VL_8H: return ".8h";
515 case ARM64Layout::VL_4S: return ".4s";
516 case ARM64Layout::VL_2D: return ".2d";
517 case ARM64Layout::VL_B: return ".b";
518 case ARM64Layout::VL_H: return ".h";
519 case ARM64Layout::VL_S: return ".s";
520 case ARM64Layout::VL_D: return ".d";
521 default: llvm_unreachable("Unknown Vector Layout");
522 }
523}
524
525inline static ARM64Layout::VectorLayout
526ARM64StringToVectorLayout(StringRef LayoutStr) {
527 return StringSwitch<ARM64Layout::VectorLayout>(LayoutStr)
528 .Case(".8b", ARM64Layout::VL_8B)
529 .Case(".4h", ARM64Layout::VL_4H)
530 .Case(".2s", ARM64Layout::VL_2S)
531 .Case(".1d", ARM64Layout::VL_1D)
532 .Case(".16b", ARM64Layout::VL_16B)
533 .Case(".8h", ARM64Layout::VL_8H)
534 .Case(".4s", ARM64Layout::VL_4S)
535 .Case(".2d", ARM64Layout::VL_2D)
536 .Case(".b", ARM64Layout::VL_B)
537 .Case(".h", ARM64Layout::VL_H)
538 .Case(".s", ARM64Layout::VL_S)
539 .Case(".d", ARM64Layout::VL_D)
540 .Default(ARM64Layout::Invalid);
541}
542
543namespace ARM64SysReg {
544 enum SysRegROValues {
545 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
546 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
547 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
548 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
549 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
550 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
551 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
552 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
553 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
554 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
555 CTR_EL0 = 0xd801, // 11 011 0000 0000 001
556 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
557 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
558 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
559 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
560 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
561 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
562 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
563 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
564 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
565 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
566 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
567 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
568 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
569 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
570 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
571 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
572 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
573 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
574 ID_AARM64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
575 ID_AARM64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
576 ID_AARM64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
577 ID_AARM64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
578 ID_AARM64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
579 ID_AARM64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
580 ID_AARM64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
581 ID_AARM64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
582 ID_AARM64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
583 ID_AARM64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
584 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
585 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
586 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
587 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
588 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
589 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
590 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
591 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
592 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
593
594 // Trace registers
595 TRCSTATR = 0x8818, // 10 001 0000 0011 000
596 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
597 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
598 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
599 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
600 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
601 TRCIDR13 = 0x882e, // 10 001 0000 0101 110
602 TRCIDR0 = 0x8847, // 10 001 0000 1000 111
603 TRCIDR1 = 0x884f, // 10 001 0000 1001 111
604 TRCIDR2 = 0x8857, // 10 001 0000 1010 111
605 TRCIDR3 = 0x885f, // 10 001 0000 1011 111
606 TRCIDR4 = 0x8867, // 10 001 0000 1100 111
607 TRCIDR5 = 0x886f, // 10 001 0000 1101 111
608 TRCIDR6 = 0x8877, // 10 001 0000 1110 111
609 TRCIDR7 = 0x887f, // 10 001 0000 1111 111
610 TRCOSLSR = 0x888c, // 10 001 0001 0001 100
611 TRCPDSR = 0x88ac, // 10 001 0001 0101 100
612 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
613 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
614 TRCLSR = 0x8bee, // 10 001 0111 1101 110
615 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
616 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
617 TRCDEVID = 0x8b97, // 10 001 0111 0010 111
618 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
619 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
620 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
621 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
622 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
623 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
624 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
625 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
626 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
627 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
628 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
629 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
630 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
631
632 // GICv3 registers
633 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
634 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
635 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
636 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
637 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
638 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
639 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
640 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
641 };
642
643 enum SysRegWOValues {
644 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
645 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
646 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
647
648 // Trace Registers
649 TRCOSLAR = 0x8884, // 10 001 0001 0000 100
650 TRCLAR = 0x8be6, // 10 001 0111 1100 110
651
652 // GICv3 registers
653 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
654 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
655 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
656 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
657 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
658 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
659 };
660
661 enum SysRegValues {
662 Invalid = -1, // Op0 Op1 CRn CRm Op2
663 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
664 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
665 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
666 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
667 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
668 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
669 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
670 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
671 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
672 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
673 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
674 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
675 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
676 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
677 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
678 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
679 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
680 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
681 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
682 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
683 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
684 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
685 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
686 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
687 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
688 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
689 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
690 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
691 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
692 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
693 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
694 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
695 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
696 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
697 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
698 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
699 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
700 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
701 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
702 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
703 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
704 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
705 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
706 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
707 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
708 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
709 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
710 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
711 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
712 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
713 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
714 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
715 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
716 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
717 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
718 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
719 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
720 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
721 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
722 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
723 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
724 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
725 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
726 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
727 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
728 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
729 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
730 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
731 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
732 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
733 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
734 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
735 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
736 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
737 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
738 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
739 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
740 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
741 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
742 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
743 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
744 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
745 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
746 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
747 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
748 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
749 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
750 HCR_EL2 = 0xe088, // 11 100 0001 0001 000
751 SCR_EL3 = 0xf088, // 11 110 0001 0001 000
752 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
753 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
754 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
755 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
756 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
757 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
758 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
759 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
760 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
761 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
762 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
763 TCR_EL1 = 0xc102, // 11 000 0010 0000 010
764 TCR_EL2 = 0xe102, // 11 100 0010 0000 010
765 TCR_EL3 = 0xf102, // 11 110 0010 0000 010
766 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
767 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
768 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
769 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
770 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
771 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
772 ELR_EL1 = 0xc201, // 11 000 0100 0000 001
773 ELR_EL2 = 0xe201, // 11 100 0100 0000 001
774 ELR_EL3 = 0xf201, // 11 110 0100 0000 001
775 SP_EL0 = 0xc208, // 11 000 0100 0001 000
776 SP_EL1 = 0xe208, // 11 100 0100 0001 000
777 SP_EL2 = 0xf208, // 11 110 0100 0001 000
778 SPSel = 0xc210, // 11 000 0100 0010 000
779 NZCV = 0xda10, // 11 011 0100 0010 000
780 DAIF = 0xda11, // 11 011 0100 0010 001
781 CurrentEL = 0xc212, // 11 000 0100 0010 010
782 SPSR_irq = 0xe218, // 11 100 0100 0011 000
783 SPSR_abt = 0xe219, // 11 100 0100 0011 001
784 SPSR_und = 0xe21a, // 11 100 0100 0011 010
785 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
786 FPCR = 0xda20, // 11 011 0100 0100 000
787 FPSR = 0xda21, // 11 011 0100 0100 001
788 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
789 DLR_EL0 = 0xda29, // 11 011 0100 0101 001
790 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
791 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
792 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
793 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
794 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
795 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
796 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
797 ESR_EL1 = 0xc290, // 11 000 0101 0010 000
798 ESR_EL2 = 0xe290, // 11 100 0101 0010 000
799 ESR_EL3 = 0xf290, // 11 110 0101 0010 000
800 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
801 FAR_EL1 = 0xc300, // 11 000 0110 0000 000
802 FAR_EL2 = 0xe300, // 11 100 0110 0000 000
803 FAR_EL3 = 0xf300, // 11 110 0110 0000 000
804 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
805 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
806 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
807 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
808 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
809 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
810 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
811 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
812 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
813 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
814 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
815 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
816 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
817 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
818 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
819 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
820 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
821 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
822 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
823 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
824 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
825 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
826 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
827 RMR_EL1 = 0xc602, // 11 000 1100 0000 010
828 RMR_EL2 = 0xe602, // 11 100 1100 0000 010
829 RMR_EL3 = 0xf602, // 11 110 1100 0000 010
830 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
831 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
832 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
833 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
834 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
835 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
836 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
837 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
838 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
839 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
840 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
841 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
842 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
843 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
844 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
845 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
846 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
847 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
848 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
849 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
850 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
851 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
852 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
853 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
854 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
855 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
856 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
857 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
858 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
859 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
860 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
861 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
862 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
863 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
864 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
865 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
866 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
867 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
868 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
869 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
870 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
871 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
872 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
873 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
874 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
875 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
876 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
877 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
878 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
879 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
880 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
881 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
882 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
883 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
884 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
885 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
886 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
887 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
888 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
889 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
890 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
891 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
892 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
893 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
894 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
895 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
896 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
897 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
898 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
899 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
900 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
901 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
902 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
903 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
904 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
905 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
906 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
907 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
908 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
909 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
910 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
911 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
912 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
913 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
914 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
915
916 // Trace registers
917 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
918 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
919 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
920 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
921 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
922 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
923 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
924 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
925 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
926 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
927 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
928 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
929 TRCQCTLR = 0x8809, // 10 001 0000 0001 001
930 TRCVICTLR = 0x8802, // 10 001 0000 0000 010
931 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
932 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
933 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
934 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
935 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
936 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
937 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
938 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
939 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
940 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
941 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
942 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
943 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
944 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
945 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
946 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
947 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
948 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
949 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
950 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
951 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
952 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
953 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
954 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
955 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
956 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
957 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
958 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
959 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
960 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
961 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
962 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
963 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
964 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
965 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
966 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
967 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
968 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
969 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
970 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
971 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
972 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
973 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
974 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
975 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
976 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
977 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
978 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
979 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
980 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
981 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
982 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
983 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
984 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
985 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
986 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
987 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
988 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
989 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
990 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
991 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
992 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
993 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
994 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
995 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
996 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
997 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
998 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
999 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
1000 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
1001 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
1002 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
1003 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
1004 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
1005 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
1006 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
1007 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
1008 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
1009 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
1010 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
1011 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
1012 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
1013 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
1014 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
1015 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
1016 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
1017 TRCPDCR = 0x88a4, // 10 001 0001 0100 100
1018 TRCACVR0 = 0x8900, // 10 001 0010 0000 000
1019 TRCACVR1 = 0x8910, // 10 001 0010 0010 000
1020 TRCACVR2 = 0x8920, // 10 001 0010 0100 000
1021 TRCACVR3 = 0x8930, // 10 001 0010 0110 000
1022 TRCACVR4 = 0x8940, // 10 001 0010 1000 000
1023 TRCACVR5 = 0x8950, // 10 001 0010 1010 000
1024 TRCACVR6 = 0x8960, // 10 001 0010 1100 000
1025 TRCACVR7 = 0x8970, // 10 001 0010 1110 000
1026 TRCACVR8 = 0x8901, // 10 001 0010 0000 001
1027 TRCACVR9 = 0x8911, // 10 001 0010 0010 001
1028 TRCACVR10 = 0x8921, // 10 001 0010 0100 001
1029 TRCACVR11 = 0x8931, // 10 001 0010 0110 001
1030 TRCACVR12 = 0x8941, // 10 001 0010 1000 001
1031 TRCACVR13 = 0x8951, // 10 001 0010 1010 001
1032 TRCACVR14 = 0x8961, // 10 001 0010 1100 001
1033 TRCACVR15 = 0x8971, // 10 001 0010 1110 001
1034 TRCACATR0 = 0x8902, // 10 001 0010 0000 010
1035 TRCACATR1 = 0x8912, // 10 001 0010 0010 010
1036 TRCACATR2 = 0x8922, // 10 001 0010 0100 010
1037 TRCACATR3 = 0x8932, // 10 001 0010 0110 010
1038 TRCACATR4 = 0x8942, // 10 001 0010 1000 010
1039 TRCACATR5 = 0x8952, // 10 001 0010 1010 010
1040 TRCACATR6 = 0x8962, // 10 001 0010 1100 010
1041 TRCACATR7 = 0x8972, // 10 001 0010 1110 010
1042 TRCACATR8 = 0x8903, // 10 001 0010 0000 011
1043 TRCACATR9 = 0x8913, // 10 001 0010 0010 011
1044 TRCACATR10 = 0x8923, // 10 001 0010 0100 011
1045 TRCACATR11 = 0x8933, // 10 001 0010 0110 011
1046 TRCACATR12 = 0x8943, // 10 001 0010 1000 011
1047 TRCACATR13 = 0x8953, // 10 001 0010 1010 011
1048 TRCACATR14 = 0x8963, // 10 001 0010 1100 011
1049 TRCACATR15 = 0x8973, // 10 001 0010 1110 011
1050 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
1051 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
1052 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
1053 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
1054 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
1055 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
1056 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
1057 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
1058 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
1059 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
1060 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
1061 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
1062 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
1063 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
1064 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
1065 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
1066 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
1067 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
1068 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
1069 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
1070 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
1071 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
1072 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
1073 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
1074 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
1075 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
1076 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
1077 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
1078 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
1079 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
1080 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
1081 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
1082 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
1083 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
1084 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
1085 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
1086 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
1087 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
1088 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
1089
1090 // GICv3 registers
1091 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
1092 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
1093 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
1094 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
1095 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
1096 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
1097 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
1098 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
1099 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
1100 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
1101 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
1102 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
1103 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
1104 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
1105 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
1106 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
1107 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
1108 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
1109 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
1110 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
1111 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
1112 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
1113 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
1114 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
1115 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
1116 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
1117 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
1118 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
1119 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
1120 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
1121 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
1122 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
1123 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
1124 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
1125 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
1126 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
1127 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
1128 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
1129 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
1130 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
1131 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
1132 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
1133 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
1134 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
1135 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
1136 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
1137 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
Bradley Smith08c391c2014-04-09 14:42:36 +0000[diff] [blame]1138 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1139 };
Bradley Smith08c391c2014-04-09 14:42:36 +0000[diff] [blame]1140
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1141 // Cyclone specific system registers
1142 enum CycloneSysRegValues {
Bradley Smith08c391c2014-04-09 14:42:36 +0000[diff] [blame]1143 CPM_IOACC_CTL_EL3 = 0xff90
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1144 };
1145
1146 // Note that these do not inherit from ARM64NamedImmMapper. This class is
1147 // sufficiently different in its behaviour that I don't believe it's worth
1148 // burdening the common ARM64NamedImmMapper with abstractions only needed in
1149 // this one case.
1150 struct SysRegMapper {
1151 static const ARM64NamedImmMapper::Mapping SysRegPairs[];
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1152 static const ARM64NamedImmMapper::Mapping CycloneSysRegPairs[];
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1153
1154 const ARM64NamedImmMapper::Mapping *InstPairs;
1155 size_t NumInstPairs;
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1156 uint64_t FeatureBits;
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1157
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1158 SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1159 uint32_t fromString(StringRef Name, bool &Valid) const;
1160 std::string toString(uint32_t Bits, bool &Valid) const;
1161 };
1162
1163 struct MSRMapper : SysRegMapper {
1164 static const ARM64NamedImmMapper::Mapping MSRPairs[];
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1165 MSRMapper(uint64_t FeatureBits);
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1166 };
1167
1168 struct MRSMapper : SysRegMapper {
1169 static const ARM64NamedImmMapper::Mapping MRSPairs[];
Bradley Smithf57d5ca2014-05-01 10:25:36 +0000[diff] [blame]1170 MRSMapper(uint64_t FeatureBits);
Bradley Smithceeb04d2014-04-09 14:42:16 +0000[diff] [blame]1171 };
1172
1173 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
1174}
1175
1176namespace ARM64TLBI {
1177 enum TLBIValues {
1178 Invalid = -1, // Op0 Op1 CRn CRm Op2
1179 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
1180 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
1181 VMALLE1IS = 0x4418, // 01 000 1000 0011 000
1182 ALLE2IS = 0x6418, // 01 100 1000 0011 000
1183 ALLE3IS = 0x7418, // 01 110 1000 0011 000
1184 VAE1IS = 0x4419, // 01 000 1000 0011 001
1185 VAE2IS = 0x6419, // 01 100 1000 0011 001
1186 VAE3IS = 0x7419, // 01 110 1000 0011 001
1187 ASIDE1IS = 0x441a, // 01 000 1000 0011 010
1188 VAAE1IS = 0x441b, // 01 000 1000 0011 011
1189 ALLE1IS = 0x641c, // 01 100 1000 0011 100
1190 VALE1IS = 0x441d, // 01 000 1000 0011 101
1191 VALE2IS = 0x641d, // 01 100 1000 0011 101
1192 VALE3IS = 0x741d, // 01 110 1000 0011 101
1193 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
1194 VAALE1IS = 0x441f, // 01 000 1000 0011 111
1195 IPAS2E1 = 0x6421, // 01 100 1000 0100 001
1196 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
1197 VMALLE1 = 0x4438, // 01 000 1000 0111 000
1198 ALLE2 = 0x6438, // 01 100 1000 0111 000
1199 ALLE3 = 0x7438, // 01 110 1000 0111 000
1200 VAE1 = 0x4439, // 01 000 1000 0111 001
1201 VAE2 = 0x6439, // 01 100 1000 0111 001
1202 VAE3 = 0x7439, // 01 110 1000 0111 001
1203 ASIDE1 = 0x443a, // 01 000 1000 0111 010
1204 VAAE1 = 0x443b, // 01 000 1000 0111 011
1205 ALLE1 = 0x643c, // 01 100 1000 0111 100
1206 VALE1 = 0x443d, // 01 000 1000 0111 101
1207 VALE2 = 0x643d, // 01 100 1000 0111 101
1208 VALE3 = 0x743d, // 01 110 1000 0111 101
1209 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
1210 VAALE1 = 0x443f // 01 000 1000 0111 111
1211 };
1212
1213 struct TLBIMapper : ARM64NamedImmMapper {
1214 const static Mapping TLBIPairs[];
1215
1216 TLBIMapper();
1217 };
1218
1219 static inline bool NeedsRegister(TLBIValues Val) {
1220 switch (Val) {
1221 case VMALLE1IS:
1222 case ALLE2IS:
1223 case ALLE3IS:
1224 case ALLE1IS:
1225 case VMALLS12E1IS:
1226 case VMALLE1:
1227 case ALLE2:
1228 case ALLE3:
1229 case ALLE1:
1230 case VMALLS12E1:
1231 return false;
1232 default:
1233 return true;
1234 }
1235 }
1236}
1237
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame]1238namespace ARM64II {
1239 /// Target Operand Flag enum.
1240 enum TOF {
1241 //===------------------------------------------------------------------===//
1242 // ARM64 Specific MachineOperand flags.
1243
1244 MO_NO_FLAG,
1245
1246 MO_FRAGMENT = 0x7,
1247
1248 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
1249 /// offset of the 4K page containing the symbol. This is used with the
1250 /// ADRP instruction.
1251 MO_PAGE = 1,
1252
1253 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
1254 /// that symbol within a 4K page. This offset is added to the page address
1255 /// to produce the complete address.
1256 MO_PAGEOFF = 2,
1257
1258 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
1259 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
1260 MO_G3 = 3,
1261
1262 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
1263 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
1264 MO_G2 = 4,
1265
1266 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
1267 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
1268 MO_G1 = 5,
1269
1270 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
1271 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
1272 MO_G0 = 6,
1273
1274 /// MO_GOT - This flag indicates that a symbol operand represents the
1275 /// address of the GOT entry for the symbol, rather than the address of
1276 /// the symbol itself.
1277 MO_GOT = 8,
1278
1279 /// MO_NC - Indicates whether the linker is expected to check the symbol
1280 /// reference for overflow. For example in an ADRP/ADD pair of relocations
1281 /// the ADRP usually does check, but not the ADD.
1282 MO_NC = 0x10,
1283
1284 /// MO_TLS - Indicates that the operand being accessed is some kind of
1285 /// thread-local symbol. On Darwin, only one type of thread-local access
1286 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
1287 /// referee will affect interpretation.
1288 MO_TLS = 0x20
1289 };
1290} // end namespace ARM64II
1291
1292} // end namespace llvm
1293
1294#endif