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gerrit-public.fairphone.software / toolchain / llvm-project / 360a5cfcd37ff1f12bec4136787b67e82b37c56d / . / llvm / lib / Target / NVPTX / NVPTXISelLowering.cpp
blob: 9d7bfbfd3bc1a35cf67b56b5e14c68e8ca545968 [file] [log] [blame]
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1//
2// The LLVM Compiler Infrastructure
3//
4// This file is distributed under the University of Illinois Open Source
5// License. See LICENSE.TXT for details.
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that NVPTX uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]14#include "NVPTXISelLowering.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]15#include "NVPTX.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]16#include "NVPTXTargetMachine.h"
17#include "NVPTXTargetObjectFile.h"
18#include "NVPTXUtilities.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]19#include "llvm/CodeGen/Analysis.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]24#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
Chandler Carruth219b89b2014-03-04 11:01:28 +0000[diff] [blame]25#include "llvm/IR/CallSite.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/GlobalValue.h"
29#include "llvm/IR/IntrinsicInst.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/IR/Module.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]32#include "llvm/MC/MCSectionELF.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]37#include <sstream>
38
39#undef DEBUG_TYPE
40#define DEBUG_TYPE "nvptx-lower"
41
42using namespace llvm;
43
44static unsigned int uniqueCallSite = 0;
45
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]46static cl::opt<bool> sched4reg(
47 "nvptx-sched4reg",
48 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]49
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]50static bool IsPTXVectorType(MVT VT) {
51 switch (VT.SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]52 default:
53 return false;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]54 case MVT::v2i1:
55 case MVT::v4i1:
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]56 case MVT::v2i8:
57 case MVT::v4i8:
58 case MVT::v2i16:
59 case MVT::v4i16:
60 case MVT::v2i32:
61 case MVT::v4i32:
62 case MVT::v2i64:
63 case MVT::v2f32:
64 case MVT::v4f32:
65 case MVT::v2f64:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]66 return true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]67 }
68}
69
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]70/// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
71/// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
72/// into their primitive components.
73/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
74/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
75/// LowerCall, and LowerReturn.
76static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
77 SmallVectorImpl<EVT> &ValueVTs,
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]78 SmallVectorImpl<uint64_t> *Offsets = nullptr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]79 uint64_t StartingOffset = 0) {
80 SmallVector<EVT, 16> TempVTs;
81 SmallVector<uint64_t, 16> TempOffsets;
82
83 ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
84 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
85 EVT VT = TempVTs[i];
86 uint64_t Off = TempOffsets[i];
87 if (VT.isVector())
88 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
89 ValueVTs.push_back(VT.getVectorElementType());
90 if (Offsets)
91 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
92 }
93 else {
94 ValueVTs.push_back(VT);
95 if (Offsets)
96 Offsets->push_back(Off);
97 }
98 }
99}
100
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]101// NVPTXTargetLowering Constructor.
102NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]103 : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
104 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]105
106 // always lower memset, memcpy, and memmove intrinsics to load/store
107 // instructions, rather
108 // then generating calls to memset, mempcy or memmove.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]109 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
110 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
111 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]112
113 setBooleanContents(ZeroOrNegativeOneBooleanContent);
114
115 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
116 // condition branches.
117 setJumpIsExpensive(true);
118
119 // By default, use the Source scheduling
120 if (sched4reg)
121 setSchedulingPreference(Sched::RegPressure);
122 else
123 setSchedulingPreference(Sched::Source);
124
125 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]126 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
127 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
128 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
129 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
130 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
131
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]132 // Operations not directly supported by NVPTX.
Tom Stellard3787b122014-06-10 16:01:29 +0000[diff] [blame]133 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
134 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
135 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
136 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
137 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
138 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
139 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]140 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
141 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
142 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
143 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
144 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
145 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
Justin Holewinski318c6252013-07-01 12:58:56 +0000[diff] [blame]147 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
148 // For others we will expand to a SHL/SRA pair.
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
152 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]154
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame^]155 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
156 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
157 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
158 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
159 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
160 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
161
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]162 if (nvptxSubtarget.hasROT64()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]163 setOperationAction(ISD::ROTL, MVT::i64, Legal);
164 setOperationAction(ISD::ROTR, MVT::i64, Legal);
165 } else {
166 setOperationAction(ISD::ROTL, MVT::i64, Expand);
167 setOperationAction(ISD::ROTR, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]168 }
169 if (nvptxSubtarget.hasROT32()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]170 setOperationAction(ISD::ROTL, MVT::i32, Legal);
171 setOperationAction(ISD::ROTR, MVT::i32, Legal);
172 } else {
173 setOperationAction(ISD::ROTL, MVT::i32, Expand);
174 setOperationAction(ISD::ROTR, MVT::i32, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]175 }
176
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]177 setOperationAction(ISD::ROTL, MVT::i16, Expand);
178 setOperationAction(ISD::ROTR, MVT::i16, Expand);
179 setOperationAction(ISD::ROTL, MVT::i8, Expand);
180 setOperationAction(ISD::ROTR, MVT::i8, Expand);
181 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
182 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
183 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]184
185 // Indirect branch is not supported.
186 // This also disables Jump Table creation.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]187 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
188 setOperationAction(ISD::BRIND, MVT::Other, Expand);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]189
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]190 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
191 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]192
193 // We want to legalize constant related memmove and memcopy
194 // intrinsics.
195 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
196
197 // Turn FP extload into load/fextend
198 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
199 // Turn FP truncstore into trunc + store.
200 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
201
202 // PTX does not support load / store predicate registers
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]203 setOperationAction(ISD::LOAD, MVT::i1, Custom);
204 setOperationAction(ISD::STORE, MVT::i1, Custom);
205
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]206 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
207 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]208 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
209 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
210 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
211 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
212
213 // This is legal in NVPTX
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]214 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
215 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]216
217 // TRAP can be lowered to PTX trap
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]218 setOperationAction(ISD::TRAP, MVT::Other, Legal);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]219
Justin Holewinski51cb1342013-07-01 12:59:04 +0000[diff] [blame]220 setOperationAction(ISD::ADDC, MVT::i64, Expand);
221 setOperationAction(ISD::ADDE, MVT::i64, Expand);
222
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]223 // Register custom handling for vector loads/stores
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]224 for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
225 ++i) {
226 MVT VT = (MVT::SimpleValueType) i;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]227 if (IsPTXVectorType(VT)) {
228 setOperationAction(ISD::LOAD, VT, Custom);
229 setOperationAction(ISD::STORE, VT, Custom);
230 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
231 }
232 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]233
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]234 // Custom handling for i8 intrinsics
235 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
236
Justin Holewinskidc372df2013-06-28 17:58:07 +0000[diff] [blame]237 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
238 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
239 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
240 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
241 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
243 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
244 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
245 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
246 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
247 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
248 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
249 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
250 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
251 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
252
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]253 // We have some custom DAG combine patterns for these nodes
254 setTargetDAGCombine(ISD::ADD);
255 setTargetDAGCombine(ISD::AND);
256 setTargetDAGCombine(ISD::FADD);
257 setTargetDAGCombine(ISD::MUL);
258 setTargetDAGCombine(ISD::SHL);
259
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]260 // Now deduce the information based on the above mentioned
261 // actions
262 computeRegisterProperties();
263}
264
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]265const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
266 switch (Opcode) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]267 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]268 return nullptr;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]269 case NVPTXISD::CALL:
270 return "NVPTXISD::CALL";
271 case NVPTXISD::RET_FLAG:
272 return "NVPTXISD::RET_FLAG";
273 case NVPTXISD::Wrapper:
274 return "NVPTXISD::Wrapper";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]275 case NVPTXISD::DeclareParam:
276 return "NVPTXISD::DeclareParam";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]277 case NVPTXISD::DeclareScalarParam:
278 return "NVPTXISD::DeclareScalarParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]279 case NVPTXISD::DeclareRet:
280 return "NVPTXISD::DeclareRet";
281 case NVPTXISD::DeclareRetParam:
282 return "NVPTXISD::DeclareRetParam";
283 case NVPTXISD::PrintCall:
284 return "NVPTXISD::PrintCall";
285 case NVPTXISD::LoadParam:
286 return "NVPTXISD::LoadParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]287 case NVPTXISD::LoadParamV2:
288 return "NVPTXISD::LoadParamV2";
289 case NVPTXISD::LoadParamV4:
290 return "NVPTXISD::LoadParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]291 case NVPTXISD::StoreParam:
292 return "NVPTXISD::StoreParam";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]293 case NVPTXISD::StoreParamV2:
294 return "NVPTXISD::StoreParamV2";
295 case NVPTXISD::StoreParamV4:
296 return "NVPTXISD::StoreParamV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]297 case NVPTXISD::StoreParamS32:
298 return "NVPTXISD::StoreParamS32";
299 case NVPTXISD::StoreParamU32:
300 return "NVPTXISD::StoreParamU32";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]301 case NVPTXISD::CallArgBegin:
302 return "NVPTXISD::CallArgBegin";
303 case NVPTXISD::CallArg:
304 return "NVPTXISD::CallArg";
305 case NVPTXISD::LastCallArg:
306 return "NVPTXISD::LastCallArg";
307 case NVPTXISD::CallArgEnd:
308 return "NVPTXISD::CallArgEnd";
309 case NVPTXISD::CallVoid:
310 return "NVPTXISD::CallVoid";
311 case NVPTXISD::CallVal:
312 return "NVPTXISD::CallVal";
313 case NVPTXISD::CallSymbol:
314 return "NVPTXISD::CallSymbol";
315 case NVPTXISD::Prototype:
316 return "NVPTXISD::Prototype";
317 case NVPTXISD::MoveParam:
318 return "NVPTXISD::MoveParam";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]319 case NVPTXISD::StoreRetval:
320 return "NVPTXISD::StoreRetval";
Justin Holewinskife44314f2013-06-28 17:57:51 +0000[diff] [blame]321 case NVPTXISD::StoreRetvalV2:
322 return "NVPTXISD::StoreRetvalV2";
323 case NVPTXISD::StoreRetvalV4:
324 return "NVPTXISD::StoreRetvalV4";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]325 case NVPTXISD::PseudoUseParam:
326 return "NVPTXISD::PseudoUseParam";
327 case NVPTXISD::RETURN:
328 return "NVPTXISD::RETURN";
329 case NVPTXISD::CallSeqBegin:
330 return "NVPTXISD::CallSeqBegin";
331 case NVPTXISD::CallSeqEnd:
332 return "NVPTXISD::CallSeqEnd";
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]333 case NVPTXISD::CallPrototype:
334 return "NVPTXISD::CallPrototype";
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]335 case NVPTXISD::LoadV2:
336 return "NVPTXISD::LoadV2";
337 case NVPTXISD::LoadV4:
338 return "NVPTXISD::LoadV4";
339 case NVPTXISD::LDGV2:
340 return "NVPTXISD::LDGV2";
341 case NVPTXISD::LDGV4:
342 return "NVPTXISD::LDGV4";
343 case NVPTXISD::LDUV2:
344 return "NVPTXISD::LDUV2";
345 case NVPTXISD::LDUV4:
346 return "NVPTXISD::LDUV4";
347 case NVPTXISD::StoreV2:
348 return "NVPTXISD::StoreV2";
349 case NVPTXISD::StoreV4:
350 return "NVPTXISD::StoreV4";
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]351 case NVPTXISD::FUN_SHFL_CLAMP:
352 return "NVPTXISD::FUN_SHFL_CLAMP";
353 case NVPTXISD::FUN_SHFR_CLAMP:
354 return "NVPTXISD::FUN_SHFR_CLAMP";
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame^]355 case NVPTXISD::IMAD:
356 return "NVPTXISD::IMAD";
357 case NVPTXISD::MUL_WIDE_SIGNED:
358 return "NVPTXISD::MUL_WIDE_SIGNED";
359 case NVPTXISD::MUL_WIDE_UNSIGNED:
360 return "NVPTXISD::MUL_WIDE_UNSIGNED";
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]361 case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
362 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
363 case NVPTXISD::Tex1DFloatFloatLevel:
364 return "NVPTXISD::Tex1DFloatFloatLevel";
365 case NVPTXISD::Tex1DFloatFloatGrad:
366 return "NVPTXISD::Tex1DFloatFloatGrad";
367 case NVPTXISD::Tex1DI32I32: return "NVPTXISD::Tex1DI32I32";
368 case NVPTXISD::Tex1DI32Float: return "NVPTXISD::Tex1DI32Float";
369 case NVPTXISD::Tex1DI32FloatLevel:
370 return "NVPTXISD::Tex1DI32FloatLevel";
371 case NVPTXISD::Tex1DI32FloatGrad:
372 return "NVPTXISD::Tex1DI32FloatGrad";
373 case NVPTXISD::Tex1DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
374 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
375 case NVPTXISD::Tex1DArrayFloatFloatLevel:
376 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
377 case NVPTXISD::Tex1DArrayFloatFloatGrad:
378 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
379 case NVPTXISD::Tex1DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
380 case NVPTXISD::Tex1DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
381 case NVPTXISD::Tex1DArrayI32FloatLevel:
382 return "NVPTXISD::Tex2DArrayI32FloatLevel";
383 case NVPTXISD::Tex1DArrayI32FloatGrad:
384 return "NVPTXISD::Tex2DArrayI32FloatGrad";
385 case NVPTXISD::Tex2DFloatI32: return "NVPTXISD::Tex2DFloatI32";
386 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
387 case NVPTXISD::Tex2DFloatFloatLevel:
388 return "NVPTXISD::Tex2DFloatFloatLevel";
389 case NVPTXISD::Tex2DFloatFloatGrad:
390 return "NVPTXISD::Tex2DFloatFloatGrad";
391 case NVPTXISD::Tex2DI32I32: return "NVPTXISD::Tex2DI32I32";
392 case NVPTXISD::Tex2DI32Float: return "NVPTXISD::Tex2DI32Float";
393 case NVPTXISD::Tex2DI32FloatLevel:
394 return "NVPTXISD::Tex2DI32FloatLevel";
395 case NVPTXISD::Tex2DI32FloatGrad:
396 return "NVPTXISD::Tex2DI32FloatGrad";
397 case NVPTXISD::Tex2DArrayFloatI32: return "NVPTXISD::Tex2DArrayFloatI32";
398 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
399 case NVPTXISD::Tex2DArrayFloatFloatLevel:
400 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
401 case NVPTXISD::Tex2DArrayFloatFloatGrad:
402 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
403 case NVPTXISD::Tex2DArrayI32I32: return "NVPTXISD::Tex2DArrayI32I32";
404 case NVPTXISD::Tex2DArrayI32Float: return "NVPTXISD::Tex2DArrayI32Float";
405 case NVPTXISD::Tex2DArrayI32FloatLevel:
406 return "NVPTXISD::Tex2DArrayI32FloatLevel";
407 case NVPTXISD::Tex2DArrayI32FloatGrad:
408 return "NVPTXISD::Tex2DArrayI32FloatGrad";
409 case NVPTXISD::Tex3DFloatI32: return "NVPTXISD::Tex3DFloatI32";
410 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
411 case NVPTXISD::Tex3DFloatFloatLevel:
412 return "NVPTXISD::Tex3DFloatFloatLevel";
413 case NVPTXISD::Tex3DFloatFloatGrad:
414 return "NVPTXISD::Tex3DFloatFloatGrad";
415 case NVPTXISD::Tex3DI32I32: return "NVPTXISD::Tex3DI32I32";
416 case NVPTXISD::Tex3DI32Float: return "NVPTXISD::Tex3DI32Float";
417 case NVPTXISD::Tex3DI32FloatLevel:
418 return "NVPTXISD::Tex3DI32FloatLevel";
419 case NVPTXISD::Tex3DI32FloatGrad:
420 return "NVPTXISD::Tex3DI32FloatGrad";
421
422 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
423 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
424 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
425 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
426 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
427 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
428 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
429 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
430 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
431
432 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
433 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
434 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
435 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
436 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
437 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
438 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
439 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
440 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
441
442 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
443 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
444 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
445 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
446 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
447 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
448 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
449 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
450 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
451
452 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
453 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
454 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
455 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
456 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
457 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
458 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
459 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
460 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
461
462 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
463 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
464 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
465 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
466 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
467 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
468 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
469 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
470 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]471 }
472}
473
Matt Arsenaultf751d622014-03-31 20:54:58 +0000[diff] [blame]474bool NVPTXTargetLowering::shouldSplitVectorType(EVT VT) const {
475 return VT.getScalarType() == MVT::i1;
Justin Holewinskibc451192012-11-29 14:26:24 +0000[diff] [blame]476}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]477
478SDValue
479NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]480 SDLoc dl(Op);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]481 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
482 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
483 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
484}
485
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]486std::string
487NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
488 const SmallVectorImpl<ISD::OutputArg> &Outs,
489 unsigned retAlignment,
490 const ImmutableCallSite *CS) const {
491
492 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
493 assert(isABI && "Non-ABI compilation is not supported");
494 if (!isABI)
495 return "";
496
497 std::stringstream O;
498 O << "prototype_" << uniqueCallSite << " : .callprototype ";
499
500 if (retTy->getTypeID() == Type::VoidTyID) {
501 O << "()";
502 } else {
503 O << "(";
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]504 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]505 unsigned size = 0;
506 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
507 size = ITy->getBitWidth();
508 if (size < 32)
509 size = 32;
510 } else {
511 assert(retTy->isFloatingPointTy() &&
512 "Floating point type expected here");
513 size = retTy->getPrimitiveSizeInBits();
514 }
515
516 O << ".param .b" << size << " _";
517 } else if (isa<PointerType>(retTy)) {
518 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
519 } else {
520 if ((retTy->getTypeID() == Type::StructTyID) || isa<VectorType>(retTy)) {
521 SmallVector<EVT, 16> vtparts;
522 ComputeValueVTs(*this, retTy, vtparts);
523 unsigned totalsz = 0;
524 for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
525 unsigned elems = 1;
526 EVT elemtype = vtparts[i];
527 if (vtparts[i].isVector()) {
528 elems = vtparts[i].getVectorNumElements();
529 elemtype = vtparts[i].getVectorElementType();
530 }
531 // TODO: no need to loop
532 for (unsigned j = 0, je = elems; j != je; ++j) {
533 unsigned sz = elemtype.getSizeInBits();
534 if (elemtype.isInteger() && (sz < 8))
535 sz = 8;
536 totalsz += sz / 8;
537 }
538 }
539 O << ".param .align " << retAlignment << " .b8 _[" << totalsz << "]";
540 } else {
541 assert(false && "Unknown return type");
542 }
543 }
544 O << ") ";
545 }
546 O << "_ (";
547
548 bool first = true;
549 MVT thePointerTy = getPointerTy();
550
551 unsigned OIdx = 0;
552 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
553 Type *Ty = Args[i].Ty;
554 if (!first) {
555 O << ", ";
556 }
557 first = false;
558
559 if (Outs[OIdx].Flags.isByVal() == false) {
560 if (Ty->isAggregateType() || Ty->isVectorTy()) {
561 unsigned align = 0;
562 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
563 const DataLayout *TD = getDataLayout();
564 // +1 because index 0 is reserved for return type alignment
565 if (!llvm::getAlign(*CallI, i + 1, align))
566 align = TD->getABITypeAlignment(Ty);
567 unsigned sz = TD->getTypeAllocSize(Ty);
568 O << ".param .align " << align << " .b8 ";
569 O << "_";
570 O << "[" << sz << "]";
571 // update the index for Outs
572 SmallVector<EVT, 16> vtparts;
573 ComputeValueVTs(*this, Ty, vtparts);
574 if (unsigned len = vtparts.size())
575 OIdx += len - 1;
576 continue;
577 }
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]578 // i8 types in IR will be i16 types in SDAG
579 assert((getValueType(Ty) == Outs[OIdx].VT ||
580 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]581 "type mismatch between callee prototype and arguments");
582 // scalar type
583 unsigned sz = 0;
584 if (isa<IntegerType>(Ty)) {
585 sz = cast<IntegerType>(Ty)->getBitWidth();
586 if (sz < 32)
587 sz = 32;
588 } else if (isa<PointerType>(Ty))
589 sz = thePointerTy.getSizeInBits();
590 else
591 sz = Ty->getPrimitiveSizeInBits();
592 O << ".param .b" << sz << " ";
593 O << "_";
594 continue;
595 }
596 const PointerType *PTy = dyn_cast<PointerType>(Ty);
597 assert(PTy && "Param with byval attribute should be a pointer type");
598 Type *ETy = PTy->getElementType();
599
600 unsigned align = Outs[OIdx].Flags.getByValAlign();
601 unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
602 O << ".param .align " << align << " .b8 ";
603 O << "_";
604 O << "[" << sz << "]";
605 }
606 O << ");";
607 return O.str();
608}
609
610unsigned
611NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
612 const ImmutableCallSite *CS,
613 Type *Ty,
614 unsigned Idx) const {
615 const DataLayout *TD = getDataLayout();
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]616 unsigned Align = 0;
617 const Value *DirectCallee = CS->getCalledFunction();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]618
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]619 if (!DirectCallee) {
620 // We don't have a direct function symbol, but that may be because of
621 // constant cast instructions in the call.
622 const Instruction *CalleeI = CS->getInstruction();
623 assert(CalleeI && "Call target is not a function or derived value?");
624
625 // With bitcast'd call targets, the instruction will be the call
626 if (isa<CallInst>(CalleeI)) {
627 // Check if we have call alignment metadata
628 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
629 return Align;
630
631 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
632 // Ignore any bitcast instructions
633 while(isa<ConstantExpr>(CalleeV)) {
634 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
635 if (!CE->isCast())
636 break;
637 // Look through the bitcast
638 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
639 }
640
641 // We have now looked past all of the bitcasts. Do we finally have a
642 // Function?
643 if (isa<Function>(CalleeV))
644 DirectCallee = CalleeV;
645 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]646 }
647
Justin Holewinski124e93d2013-11-11 19:28:19 +0000[diff] [blame]648 // Check for function alignment information if we found that the
649 // ultimate target is a Function
650 if (DirectCallee)
651 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
652 return Align;
653
654 // Call is indirect or alignment information is not available, fall back to
655 // the ABI type alignment
656 return TD->getABITypeAlignment(Ty);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]657}
658
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]659SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
660 SmallVectorImpl<SDValue> &InVals) const {
661 SelectionDAG &DAG = CLI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]662 SDLoc dl = CLI.DL;
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]663 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
664 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
665 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]666 SDValue Chain = CLI.Chain;
667 SDValue Callee = CLI.Callee;
668 bool &isTailCall = CLI.IsTailCall;
Saleem Abdulrasool9f664c12014-05-17 21:50:01 +0000[diff] [blame]669 ArgListTy &Args = CLI.getArgs();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]670 Type *retTy = CLI.RetTy;
671 ImmutableCallSite *CS = CLI.CS;
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]672
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]673 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]674 assert(isABI && "Non-ABI compilation is not supported");
675 if (!isABI)
676 return Chain;
677 const DataLayout *TD = getDataLayout();
678 MachineFunction &MF = DAG.getMachineFunction();
679 const Function *F = MF.getFunction();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]680
681 SDValue tempChain = Chain;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]682 Chain =
683 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
684 dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]685 SDValue InFlag = Chain.getValue(1);
686
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]687 unsigned paramCount = 0;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]688 // Args.size() and Outs.size() need not match.
689 // Outs.size() will be larger
690 // * if there is an aggregate argument with multiple fields (each field
691 // showing up separately in Outs)
692 // * if there is a vector argument with more than typical vector-length
693 // elements (generally if more than 4) where each vector element is
694 // individually present in Outs.
695 // So a different index should be used for indexing into Outs/OutVals.
696 // See similar issue in LowerFormalArguments.
697 unsigned OIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]698 // Declare the .params or .reg need to pass values
699 // to the function
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]700 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
701 EVT VT = Outs[OIdx].VT;
702 Type *Ty = Args[i].Ty;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]703
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]704 if (Outs[OIdx].Flags.isByVal() == false) {
705 if (Ty->isAggregateType()) {
706 // aggregate
707 SmallVector<EVT, 16> vtparts;
708 ComputeValueVTs(*this, Ty, vtparts);
709
710 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
711 // declare .param .align <align> .b8 .param<n>[<size>];
712 unsigned sz = TD->getTypeAllocSize(Ty);
713 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
714 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
715 DAG.getConstant(paramCount, MVT::i32),
716 DAG.getConstant(sz, MVT::i32), InFlag };
717 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]718 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]719 InFlag = Chain.getValue(1);
720 unsigned curOffset = 0;
721 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
722 unsigned elems = 1;
723 EVT elemtype = vtparts[j];
724 if (vtparts[j].isVector()) {
725 elems = vtparts[j].getVectorNumElements();
726 elemtype = vtparts[j].getVectorElementType();
727 }
728 for (unsigned k = 0, ke = elems; k != ke; ++k) {
729 unsigned sz = elemtype.getSizeInBits();
730 if (elemtype.isInteger() && (sz < 8))
731 sz = 8;
732 SDValue StVal = OutVals[OIdx];
733 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]734 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]735 }
736 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
737 SDValue CopyParamOps[] = { Chain,
738 DAG.getConstant(paramCount, MVT::i32),
739 DAG.getConstant(curOffset, MVT::i32),
740 StVal, InFlag };
741 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]742 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]743 elemtype, MachinePointerInfo());
744 InFlag = Chain.getValue(1);
745 curOffset += sz / 8;
746 ++OIdx;
747 }
748 }
749 if (vtparts.size() > 0)
750 --OIdx;
751 ++paramCount;
752 continue;
753 }
754 if (Ty->isVectorTy()) {
755 EVT ObjectVT = getValueType(Ty);
756 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
757 // declare .param .align <align> .b8 .param<n>[<size>];
758 unsigned sz = TD->getTypeAllocSize(Ty);
759 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
760 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
761 DAG.getConstant(paramCount, MVT::i32),
762 DAG.getConstant(sz, MVT::i32), InFlag };
763 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]764 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]765 InFlag = Chain.getValue(1);
766 unsigned NumElts = ObjectVT.getVectorNumElements();
767 EVT EltVT = ObjectVT.getVectorElementType();
768 EVT MemVT = EltVT;
769 bool NeedExtend = false;
770 if (EltVT.getSizeInBits() < 16) {
771 NeedExtend = true;
772 EltVT = MVT::i16;
773 }
774
775 // V1 store
776 if (NumElts == 1) {
777 SDValue Elt = OutVals[OIdx++];
778 if (NeedExtend)
779 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
780
781 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
782 SDValue CopyParamOps[] = { Chain,
783 DAG.getConstant(paramCount, MVT::i32),
784 DAG.getConstant(0, MVT::i32), Elt,
785 InFlag };
786 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]787 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]788 MemVT, MachinePointerInfo());
789 InFlag = Chain.getValue(1);
790 } else if (NumElts == 2) {
791 SDValue Elt0 = OutVals[OIdx++];
792 SDValue Elt1 = OutVals[OIdx++];
793 if (NeedExtend) {
794 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
795 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
796 }
797
798 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
799 SDValue CopyParamOps[] = { Chain,
800 DAG.getConstant(paramCount, MVT::i32),
801 DAG.getConstant(0, MVT::i32), Elt0, Elt1,
802 InFlag };
803 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]804 CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]805 MemVT, MachinePointerInfo());
806 InFlag = Chain.getValue(1);
807 } else {
808 unsigned curOffset = 0;
809 // V4 stores
810 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
811 // the
812 // vector will be expanded to a power of 2 elements, so we know we can
813 // always round up to the next multiple of 4 when creating the vector
814 // stores.
815 // e.g. 4 elem => 1 st.v4
816 // 6 elem => 2 st.v4
817 // 8 elem => 2 st.v4
818 // 11 elem => 3 st.v4
819 unsigned VecSize = 4;
820 if (EltVT.getSizeInBits() == 64)
821 VecSize = 2;
822
823 // This is potentially only part of a vector, so assume all elements
824 // are packed together.
825 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
826
827 for (unsigned i = 0; i < NumElts; i += VecSize) {
828 // Get values
829 SDValue StoreVal;
830 SmallVector<SDValue, 8> Ops;
831 Ops.push_back(Chain);
832 Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
833 Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
834
835 unsigned Opc = NVPTXISD::StoreParamV2;
836
837 StoreVal = OutVals[OIdx++];
838 if (NeedExtend)
839 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
840 Ops.push_back(StoreVal);
841
842 if (i + 1 < NumElts) {
843 StoreVal = OutVals[OIdx++];
844 if (NeedExtend)
845 StoreVal =
846 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
847 } else {
848 StoreVal = DAG.getUNDEF(EltVT);
849 }
850 Ops.push_back(StoreVal);
851
852 if (VecSize == 4) {
853 Opc = NVPTXISD::StoreParamV4;
854 if (i + 2 < NumElts) {
855 StoreVal = OutVals[OIdx++];
856 if (NeedExtend)
857 StoreVal =
858 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
859 } else {
860 StoreVal = DAG.getUNDEF(EltVT);
861 }
862 Ops.push_back(StoreVal);
863
864 if (i + 3 < NumElts) {
865 StoreVal = OutVals[OIdx++];
866 if (NeedExtend)
867 StoreVal =
868 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
869 } else {
870 StoreVal = DAG.getUNDEF(EltVT);
871 }
872 Ops.push_back(StoreVal);
873 }
874
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]875 Ops.push_back(InFlag);
876
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]877 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]878 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
879 MemVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]880 InFlag = Chain.getValue(1);
881 curOffset += PerStoreOffset;
882 }
883 }
884 ++paramCount;
885 --OIdx;
886 continue;
887 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]888 // Plain scalar
889 // for ABI, declare .param .b<size> .param<n>;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]890 unsigned sz = VT.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]891 bool needExtend = false;
892 if (VT.isInteger()) {
893 if (sz < 16)
894 needExtend = true;
895 if (sz < 32)
896 sz = 32;
897 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]898 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
899 SDValue DeclareParamOps[] = { Chain,
900 DAG.getConstant(paramCount, MVT::i32),
901 DAG.getConstant(sz, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]902 DAG.getConstant(0, MVT::i32), InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]903 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]904 DeclareParamOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]905 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]906 SDValue OutV = OutVals[OIdx];
907 if (needExtend) {
908 // zext/sext i1 to i16
909 unsigned opc = ISD::ZERO_EXTEND;
910 if (Outs[OIdx].Flags.isSExt())
911 opc = ISD::SIGN_EXTEND;
912 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
913 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]914 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
915 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]916 DAG.getConstant(0, MVT::i32), OutV, InFlag };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]917
918 unsigned opcode = NVPTXISD::StoreParam;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]919 if (Outs[OIdx].Flags.isZExt())
920 opcode = NVPTXISD::StoreParamU32;
921 else if (Outs[OIdx].Flags.isSExt())
922 opcode = NVPTXISD::StoreParamS32;
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]923 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]924 VT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]925
926 InFlag = Chain.getValue(1);
927 ++paramCount;
928 continue;
929 }
930 // struct or vector
931 SmallVector<EVT, 16> vtparts;
932 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]933 assert(PTy && "Type of a byval parameter should be pointer");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]934 ComputeValueVTs(*this, PTy->getElementType(), vtparts);
935
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]936 // declare .param .align <align> .b8 .param<n>[<size>];
937 unsigned sz = Outs[OIdx].Flags.getByValSize();
938 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
939 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
940 // so we don't need to worry about natural alignment or not.
941 // See TargetLowering::LowerCallTo().
942 SDValue DeclareParamOps[] = {
943 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
944 DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
945 InFlag
946 };
947 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]948 DeclareParamOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]949 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]950 unsigned curOffset = 0;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]951 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]952 unsigned elems = 1;
953 EVT elemtype = vtparts[j];
954 if (vtparts[j].isVector()) {
955 elems = vtparts[j].getVectorNumElements();
956 elemtype = vtparts[j].getVectorElementType();
957 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]958 for (unsigned k = 0, ke = elems; k != ke; ++k) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]959 unsigned sz = elemtype.getSizeInBits();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]960 if (elemtype.isInteger() && (sz < 8))
961 sz = 8;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]962 SDValue srcAddr =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]963 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]964 DAG.getConstant(curOffset, getPointerTy()));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]965 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
966 MachinePointerInfo(), false, false, false,
967 0);
968 if (elemtype.getSizeInBits() < 16) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]969 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]970 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]971 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
972 SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]973 DAG.getConstant(curOffset, MVT::i32), theVal,
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]974 InFlag };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]975 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]976 CopyParamOps, elemtype,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]977 MachinePointerInfo());
978
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]979 InFlag = Chain.getValue(1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]980 curOffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]981 }
982 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]983 ++paramCount;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]984 }
985
986 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
987 unsigned retAlignment = 0;
988
989 // Handle Result
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]990 if (Ins.size() > 0) {
991 SmallVector<EVT, 16> resvtparts;
992 ComputeValueVTs(*this, retTy, resvtparts);
993
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]994 // Declare
995 // .param .align 16 .b8 retval0[<size-in-bytes>], or
996 // .param .b<size-in-bits> retval0
997 unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
Rafael Espindola08013342013-12-07 19:34:20 +0000[diff] [blame]998 if (retTy->isSingleValueType()) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]999 // Scalar needs to be at least 32bit wide
1000 if (resultsz < 32)
1001 resultsz = 32;
1002 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1003 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
1004 DAG.getConstant(resultsz, MVT::i32),
1005 DAG.getConstant(0, MVT::i32), InFlag };
1006 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1007 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1008 InFlag = Chain.getValue(1);
1009 } else {
1010 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1011 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1012 SDValue DeclareRetOps[] = { Chain,
1013 DAG.getConstant(retAlignment, MVT::i32),
1014 DAG.getConstant(resultsz / 8, MVT::i32),
1015 DAG.getConstant(0, MVT::i32), InFlag };
1016 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1017 DeclareRetOps);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1018 InFlag = Chain.getValue(1);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1019 }
1020 }
1021
1022 if (!Func) {
1023 // This is indirect function call case : PTX requires a prototype of the
1024 // form
1025 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1026 // to be emitted, and the label has to used as the last arg of call
1027 // instruction.
Justin Holewinski3d49e5c2013-11-15 12:30:04 +0000[diff] [blame]1028 // The prototype is embedded in a string and put as the operand for a
1029 // CallPrototype SDNode which will print out to the value of the string.
1030 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1031 std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
1032 const char *ProtoStr =
1033 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1034 SDValue ProtoOps[] = {
1035 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1036 };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1037 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1038 InFlag = Chain.getValue(1);
1039 }
1040 // Op to just print "call"
1041 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1042 SDValue PrintCallOps[] = {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1043 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1044 };
1045 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1046 dl, PrintCallVTs, PrintCallOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1047 InFlag = Chain.getValue(1);
1048
1049 // Ops to print out the function name
1050 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1051 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1052 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1053 InFlag = Chain.getValue(1);
1054
1055 // Ops to print out the param list
1056 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1057 SDValue CallArgBeginOps[] = { Chain, InFlag };
1058 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1059 CallArgBeginOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1060 InFlag = Chain.getValue(1);
1061
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1062 for (unsigned i = 0, e = paramCount; i != e; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1063 unsigned opcode;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1064 if (i == (e - 1))
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1065 opcode = NVPTXISD::LastCallArg;
1066 else
1067 opcode = NVPTXISD::CallArg;
1068 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1069 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1070 DAG.getConstant(i, MVT::i32), InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1071 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1072 InFlag = Chain.getValue(1);
1073 }
1074 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1075 SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1076 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1077 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1078 InFlag = Chain.getValue(1);
1079
1080 if (!Func) {
1081 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1082 SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1083 InFlag };
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1084 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1085 InFlag = Chain.getValue(1);
1086 }
1087
1088 // Generate loads from param memory/moves from registers for result
1089 if (Ins.size() > 0) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1090 unsigned resoffset = 0;
1091 if (retTy && retTy->isVectorTy()) {
1092 EVT ObjectVT = getValueType(retTy);
1093 unsigned NumElts = ObjectVT.getVectorNumElements();
1094 EVT EltVT = ObjectVT.getVectorElementType();
Benjamin Kramer3cc579a2013-06-29 22:51:12 +0000[diff] [blame]1095 assert(nvTM->getTargetLowering()->getNumRegisters(F->getContext(),
1096 ObjectVT) == NumElts &&
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1097 "Vector was not scalarized");
1098 unsigned sz = EltVT.getSizeInBits();
1099 bool needTruncate = sz < 16 ? true : false;
1100
1101 if (NumElts == 1) {
1102 // Just a simple load
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1103 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1104 if (needTruncate) {
1105 // If loading i1 result, generate
1106 // load i16
1107 // trunc i16 to i1
1108 LoadRetVTs.push_back(MVT::i16);
1109 } else
1110 LoadRetVTs.push_back(EltVT);
1111 LoadRetVTs.push_back(MVT::Other);
1112 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1113 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1114 LoadRetOps.push_back(Chain);
1115 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1116 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1117 LoadRetOps.push_back(InFlag);
1118 SDValue retval = DAG.getMemIntrinsicNode(
1119 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1120 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1121 Chain = retval.getValue(1);
1122 InFlag = retval.getValue(2);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1123 SDValue Ret0 = retval;
1124 if (needTruncate)
1125 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1126 InVals.push_back(Ret0);
1127 } else if (NumElts == 2) {
1128 // LoadV2
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1129 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1130 if (needTruncate) {
1131 // If loading i1 result, generate
1132 // load i16
1133 // trunc i16 to i1
1134 LoadRetVTs.push_back(MVT::i16);
1135 LoadRetVTs.push_back(MVT::i16);
1136 } else {
1137 LoadRetVTs.push_back(EltVT);
1138 LoadRetVTs.push_back(EltVT);
1139 }
1140 LoadRetVTs.push_back(MVT::Other);
1141 LoadRetVTs.push_back(MVT::Glue);
Craig Topper59f626d2014-04-26 19:29:47 +0000[diff] [blame]1142 SmallVector<SDValue, 4> LoadRetOps;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1143 LoadRetOps.push_back(Chain);
1144 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1145 LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
1146 LoadRetOps.push_back(InFlag);
1147 SDValue retval = DAG.getMemIntrinsicNode(
1148 NVPTXISD::LoadParamV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1149 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1150 Chain = retval.getValue(2);
1151 InFlag = retval.getValue(3);
1152 SDValue Ret0 = retval.getValue(0);
1153 SDValue Ret1 = retval.getValue(1);
1154 if (needTruncate) {
1155 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1156 InVals.push_back(Ret0);
1157 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1158 InVals.push_back(Ret1);
1159 } else {
1160 InVals.push_back(Ret0);
1161 InVals.push_back(Ret1);
1162 }
1163 } else {
1164 // Split into N LoadV4
1165 unsigned Ofst = 0;
1166 unsigned VecSize = 4;
1167 unsigned Opc = NVPTXISD::LoadParamV4;
1168 if (EltVT.getSizeInBits() == 64) {
1169 VecSize = 2;
1170 Opc = NVPTXISD::LoadParamV2;
1171 }
1172 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1173 for (unsigned i = 0; i < NumElts; i += VecSize) {
1174 SmallVector<EVT, 8> LoadRetVTs;
1175 if (needTruncate) {
1176 // If loading i1 result, generate
1177 // load i16
1178 // trunc i16 to i1
1179 for (unsigned j = 0; j < VecSize; ++j)
1180 LoadRetVTs.push_back(MVT::i16);
1181 } else {
1182 for (unsigned j = 0; j < VecSize; ++j)
1183 LoadRetVTs.push_back(EltVT);
1184 }
1185 LoadRetVTs.push_back(MVT::Other);
1186 LoadRetVTs.push_back(MVT::Glue);
1187 SmallVector<SDValue, 4> LoadRetOps;
1188 LoadRetOps.push_back(Chain);
1189 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1190 LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
1191 LoadRetOps.push_back(InFlag);
1192 SDValue retval = DAG.getMemIntrinsicNode(
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]1193 Opc, dl, DAG.getVTList(LoadRetVTs),
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1194 LoadRetOps, EltVT, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1195 if (VecSize == 2) {
1196 Chain = retval.getValue(2);
1197 InFlag = retval.getValue(3);
1198 } else {
1199 Chain = retval.getValue(4);
1200 InFlag = retval.getValue(5);
1201 }
1202
1203 for (unsigned j = 0; j < VecSize; ++j) {
1204 if (i + j >= NumElts)
1205 break;
1206 SDValue Elt = retval.getValue(j);
1207 if (needTruncate)
1208 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1209 InVals.push_back(Elt);
1210 }
1211 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1212 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1213 }
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1214 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1215 SmallVector<EVT, 16> VTs;
1216 ComputePTXValueVTs(*this, retTy, VTs);
1217 assert(VTs.size() == Ins.size() && "Bad value decomposition");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1218 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1219 unsigned sz = VTs[i].getSizeInBits();
1220 bool needTruncate = sz < 8 ? true : false;
1221 if (VTs[i].isInteger() && (sz < 8))
1222 sz = 8;
1223
1224 SmallVector<EVT, 4> LoadRetVTs;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1225 EVT TheLoadType = VTs[i];
1226 if (retTy->isIntegerTy() &&
1227 TD->getTypeAllocSizeInBits(retTy) < 32) {
1228 // This is for integer types only, and specifically not for
1229 // aggregates.
1230 LoadRetVTs.push_back(MVT::i32);
1231 TheLoadType = MVT::i32;
1232 } else if (sz < 16) {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1233 // If loading i1/i8 result, generate
1234 // load i8 (-> i16)
1235 // trunc i16 to i1/i8
1236 LoadRetVTs.push_back(MVT::i16);
1237 } else
1238 LoadRetVTs.push_back(Ins[i].VT);
1239 LoadRetVTs.push_back(MVT::Other);
1240 LoadRetVTs.push_back(MVT::Glue);
1241
1242 SmallVector<SDValue, 4> LoadRetOps;
1243 LoadRetOps.push_back(Chain);
1244 LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
1245 LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
1246 LoadRetOps.push_back(InFlag);
1247 SDValue retval = DAG.getMemIntrinsicNode(
1248 NVPTXISD::LoadParam, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1249 DAG.getVTList(LoadRetVTs), LoadRetOps,
1250 TheLoadType, MachinePointerInfo());
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1251 Chain = retval.getValue(1);
1252 InFlag = retval.getValue(2);
1253 SDValue Ret0 = retval.getValue(0);
1254 if (needTruncate)
1255 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1256 InVals.push_back(Ret0);
1257 resoffset += sz / 8;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1258 }
1259 }
1260 }
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1261
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1262 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
1263 DAG.getIntPtrConstant(uniqueCallSite + 1, true),
Andrew Trickad6d08a2013-05-29 22:03:55 +0000[diff] [blame]1264 InFlag, dl);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1265 uniqueCallSite++;
1266
1267 // set isTailCall to false for now, until we figure out how to express
1268 // tail call optimization in PTX
1269 isTailCall = false;
1270 return Chain;
1271}
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1272
1273// By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1274// (see LegalizeDAG.cpp). This is slow and uses local memory.
1275// We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1276SDValue
1277NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1278 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1279 SDLoc dl(Node);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1280 SmallVector<SDValue, 8> Ops;
1281 unsigned NumOperands = Node->getNumOperands();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1282 for (unsigned i = 0; i < NumOperands; ++i) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1283 SDValue SubOp = Node->getOperand(i);
1284 EVT VVT = SubOp.getNode()->getValueType(0);
1285 EVT EltVT = VVT.getVectorElementType();
1286 unsigned NumSubElem = VVT.getVectorNumElements();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1287 for (unsigned j = 0; j < NumSubElem; ++j) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1288 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1289 DAG.getIntPtrConstant(j)));
1290 }
1291 }
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1292 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1293}
1294
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame^]1295/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1296/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1297/// amount, or
1298/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1299/// amount.
1300SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1301 SelectionDAG &DAG) const {
1302 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1303 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1304
1305 EVT VT = Op.getValueType();
1306 unsigned VTBits = VT.getSizeInBits();
1307 SDLoc dl(Op);
1308 SDValue ShOpLo = Op.getOperand(0);
1309 SDValue ShOpHi = Op.getOperand(1);
1310 SDValue ShAmt = Op.getOperand(2);
1311 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1312
1313 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1314
1315 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1316 // {dHi, dLo} = {aHi, aLo} >> Amt
1317 // dHi = aHi >> Amt
1318 // dLo = shf.r.clamp aLo, aHi, Amt
1319
1320 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1321 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1322 ShAmt);
1323
1324 SDValue Ops[2] = { Lo, Hi };
1325 return DAG.getMergeValues(Ops, dl);
1326 }
1327 else {
1328
1329 // {dHi, dLo} = {aHi, aLo} >> Amt
1330 // - if (Amt>=size) then
1331 // dLo = aHi >> (Amt-size)
1332 // dHi = aHi >> Amt (this is either all 0 or all 1)
1333 // else
1334 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1335 // dHi = aHi >> Amt
1336
1337 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1338 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1339 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1340 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1341 DAG.getConstant(VTBits, MVT::i32));
1342 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1343 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1344 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1345
1346 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1347 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1348 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1349 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1350
1351 SDValue Ops[2] = { Lo, Hi };
1352 return DAG.getMergeValues(Ops, dl);
1353 }
1354}
1355
1356/// LowerShiftLeftParts - Lower SHL_PARTS, which
1357/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1358/// amount, or
1359/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1360/// amount.
1361SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1362 SelectionDAG &DAG) const {
1363 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1364 assert(Op.getOpcode() == ISD::SHL_PARTS);
1365
1366 EVT VT = Op.getValueType();
1367 unsigned VTBits = VT.getSizeInBits();
1368 SDLoc dl(Op);
1369 SDValue ShOpLo = Op.getOperand(0);
1370 SDValue ShOpHi = Op.getOperand(1);
1371 SDValue ShAmt = Op.getOperand(2);
1372
1373 if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
1374
1375 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1376 // {dHi, dLo} = {aHi, aLo} << Amt
1377 // dHi = shf.l.clamp aLo, aHi, Amt
1378 // dLo = aLo << Amt
1379
1380 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1381 ShAmt);
1382 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1383
1384 SDValue Ops[2] = { Lo, Hi };
1385 return DAG.getMergeValues(Ops, dl);
1386 }
1387 else {
1388
1389 // {dHi, dLo} = {aHi, aLo} << Amt
1390 // - if (Amt>=size) then
1391 // dLo = aLo << Amt (all 0)
1392 // dLo = aLo << (Amt-size)
1393 // else
1394 // dLo = aLo << Amt
1395 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1396
1397 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1398 DAG.getConstant(VTBits, MVT::i32), ShAmt);
1399 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1400 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1401 DAG.getConstant(VTBits, MVT::i32));
1402 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1403 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1404 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1405
1406 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1407 DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
1408 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1409 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1410
1411 SDValue Ops[2] = { Lo, Hi };
1412 return DAG.getMergeValues(Ops, dl);
1413 }
1414}
1415
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1416SDValue
1417NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1418 switch (Op.getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1419 case ISD::RETURNADDR:
1420 return SDValue();
1421 case ISD::FRAMEADDR:
1422 return SDValue();
1423 case ISD::GlobalAddress:
1424 return LowerGlobalAddress(Op, DAG);
1425 case ISD::INTRINSIC_W_CHAIN:
1426 return Op;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1427 case ISD::BUILD_VECTOR:
1428 case ISD::EXTRACT_SUBVECTOR:
1429 return Op;
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1430 case ISD::CONCAT_VECTORS:
1431 return LowerCONCAT_VECTORS(Op, DAG);
1432 case ISD::STORE:
1433 return LowerSTORE(Op, DAG);
1434 case ISD::LOAD:
1435 return LowerLOAD(Op, DAG);
Justin Holewinski360a5cf2014-06-27 18:35:40 +0000[diff] [blame^]1436 case ISD::SHL_PARTS:
1437 return LowerShiftLeftParts(Op, DAG);
1438 case ISD::SRA_PARTS:
1439 case ISD::SRL_PARTS:
1440 return LowerShiftRightParts(Op, DAG);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1441 default:
David Blaikie891d0a32012-05-04 22:34:16 +0000[diff] [blame]1442 llvm_unreachable("Custom lowering not defined for operation");
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1443 }
1444}
1445
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1446SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1447 if (Op.getValueType() == MVT::i1)
1448 return LowerLOADi1(Op, DAG);
1449 else
1450 return SDValue();
1451}
1452
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1453// v = ld i1* addr
1454// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1455// v1 = ld i8* addr (-> i16)
1456// v = trunc i16 to i1
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1457SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1458 SDNode *Node = Op.getNode();
1459 LoadSDNode *LD = cast<LoadSDNode>(Node);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1460 SDLoc dl(Node);
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1461 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1462 assert(Node->getValueType(0) == MVT::i1 &&
1463 "Custom lowering for i1 load only");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1464 SDValue newLD =
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1465 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1466 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1467 LD->isInvariant(), LD->getAlignment());
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1468 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1469 // The legalizer (the caller) is expecting two values from the legalized
1470 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1471 // in LegalizeDAG.cpp which also uses MergeValues.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1472 SDValue Ops[] = { result, LD->getChain() };
Craig Topper64941d92014-04-27 19:20:57 +0000[diff] [blame]1473 return DAG.getMergeValues(Ops, dl);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1474}
1475
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1476SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1477 EVT ValVT = Op.getOperand(1).getValueType();
1478 if (ValVT == MVT::i1)
1479 return LowerSTOREi1(Op, DAG);
1480 else if (ValVT.isVector())
1481 return LowerSTOREVector(Op, DAG);
1482 else
1483 return SDValue();
1484}
1485
1486SDValue
1487NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1488 SDNode *N = Op.getNode();
1489 SDValue Val = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1490 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1491 EVT ValVT = Val.getValueType();
1492
1493 if (ValVT.isVector()) {
1494 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1495 // legal. We can (and should) split that into 2 stores of <2 x double> here
1496 // but I'm leaving that as a TODO for now.
1497 if (!ValVT.isSimple())
1498 return SDValue();
1499 switch (ValVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1500 default:
1501 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1502 case MVT::v2i8:
1503 case MVT::v2i16:
1504 case MVT::v2i32:
1505 case MVT::v2i64:
1506 case MVT::v2f32:
1507 case MVT::v2f64:
1508 case MVT::v4i8:
1509 case MVT::v4i16:
1510 case MVT::v4i32:
1511 case MVT::v4f32:
1512 // This is a "native" vector type
1513 break;
1514 }
1515
1516 unsigned Opcode = 0;
1517 EVT EltVT = ValVT.getVectorElementType();
1518 unsigned NumElts = ValVT.getVectorNumElements();
1519
1520 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1521 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]1522 // stored type to i16 and propagate the "real" type as the memory type.
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1523 bool NeedExt = false;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1524 if (EltVT.getSizeInBits() < 16)
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1525 NeedExt = true;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1526
1527 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1528 default:
1529 return SDValue();
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1530 case 2:
1531 Opcode = NVPTXISD::StoreV2;
1532 break;
1533 case 4: {
1534 Opcode = NVPTXISD::StoreV4;
1535 break;
1536 }
1537 }
1538
1539 SmallVector<SDValue, 8> Ops;
1540
1541 // First is the chain
1542 Ops.push_back(N->getOperand(0));
1543
1544 // Then the split values
1545 for (unsigned i = 0; i < NumElts; ++i) {
1546 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1547 DAG.getIntPtrConstant(i));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1548 if (NeedExt)
1549 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1550 Ops.push_back(ExtVal);
1551 }
1552
1553 // Then any remaining arguments
1554 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1555 Ops.push_back(N->getOperand(i));
1556 }
1557
1558 MemSDNode *MemSD = cast<MemSDNode>(N);
1559
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1560 SDValue NewSt = DAG.getMemIntrinsicNode(
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1561 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1562 MemSD->getMemoryVT(), MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]1563
1564 //return DCI.CombineTo(N, NewSt, true);
1565 return NewSt;
1566 }
1567
1568 return SDValue();
1569}
1570
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1571// st i1 v, addr
1572// =>
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1573// v1 = zxt v to i16
1574// st.u8 i16, addr
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1575SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1576 SDNode *Node = Op.getNode();
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1577 SDLoc dl(Node);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1578 StoreSDNode *ST = cast<StoreSDNode>(Node);
1579 SDValue Tmp1 = ST->getChain();
1580 SDValue Tmp2 = ST->getBasePtr();
1581 SDValue Tmp3 = ST->getValue();
NAKAMURA Takumi5bbe0e12012-11-14 23:46:15 +0000[diff] [blame]1582 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1583 unsigned Alignment = ST->getAlignment();
1584 bool isVolatile = ST->isVolatile();
1585 bool isNonTemporal = ST->isNonTemporal();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1586 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
1587 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1588 ST->getPointerInfo(), MVT::i8, isNonTemporal,
1589 isVolatile, Alignment);
Justin Holewinskic6462aa2012-11-14 19:19:16 +0000[diff] [blame]1590 return Result;
1591}
1592
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1593SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
1594 int idx, EVT v) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1595 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
1596 std::stringstream suffix;
1597 suffix << idx;
1598 *name += suffix.str();
1599 return DAG.getTargetExternalSymbol(name->c_str(), v);
1600}
1601
1602SDValue
1603NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
Justin Holewinskia2a63d22013-08-06 14:13:27 +0000[diff] [blame]1604 std::string ParamSym;
1605 raw_string_ostream ParamStr(ParamSym);
1606
1607 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
1608 ParamStr.flush();
1609
1610 std::string *SavedStr =
1611 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
1612 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1613}
1614
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1615SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1616 return getExtSymb(DAG, ".HLPPARAM", idx);
1617}
1618
1619// Check to see if the kernel argument is image*_t or sampler_t
1620
1621bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1622 static const char *const specialTypes[] = { "struct._image2d_t",
1623 "struct._image3d_t",
1624 "struct._sampler_t" };
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1625
1626 const Type *Ty = arg->getType();
1627 const PointerType *PTy = dyn_cast<PointerType>(Ty);
1628
1629 if (!PTy)
1630 return false;
1631
1632 if (!context)
1633 return false;
1634
1635 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
Justin Holewinskifb711152012-12-05 20:50:28 +0000[diff] [blame]1636 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1637
Craig Toppere4260f92012-05-24 04:22:05 +0000[diff] [blame]1638 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1639 if (TypeName == specialTypes[i])
1640 return true;
1641
1642 return false;
1643}
1644
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1645SDValue NVPTXTargetLowering::LowerFormalArguments(
1646 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]1647 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1648 SmallVectorImpl<SDValue> &InVals) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1649 MachineFunction &MF = DAG.getMachineFunction();
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000[diff] [blame]1650 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1651
1652 const Function *F = MF.getFunction();
Bill Wendlinge94d8432012-12-07 23:16:57 +0000[diff] [blame]1653 const AttributeSet &PAL = F->getAttributes();
Eric Christopher2ecb77e2014-06-27 03:45:49 +0000[diff] [blame]1654 const TargetLowering *TLI = DAG.getTarget().getTargetLowering();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1655
1656 SDValue Root = DAG.getRoot();
1657 std::vector<SDValue> OutChains;
1658
1659 bool isKernel = llvm::isKernelFunction(*F);
1660 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1661 assert(isABI && "Non-ABI compilation is not supported");
1662 if (!isABI)
1663 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1664
1665 std::vector<Type *> argTypes;
1666 std::vector<const Argument *> theArgs;
1667 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1668 I != E; ++I) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1669 theArgs.push_back(I);
1670 argTypes.push_back(I->getType());
1671 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1672 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
1673 // Ins.size() will be larger
1674 // * if there is an aggregate argument with multiple fields (each field
1675 // showing up separately in Ins)
1676 // * if there is a vector argument with more than typical vector-length
1677 // elements (generally if more than 4) where each vector element is
1678 // individually present in Ins.
1679 // So a different index should be used for indexing into Ins.
1680 // See similar issue in LowerCall.
1681 unsigned InsIdx = 0;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1682
1683 int idx = 0;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1684 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1685 Type *Ty = argTypes[i];
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1686
1687 // If the kernel argument is image*_t or sampler_t, convert it to
1688 // a i32 constant holding the parameter position. This can later
1689 // matched in the AsmPrinter to output the correct mangled name.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1690 if (isImageOrSamplerVal(
1691 theArgs[i],
1692 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]1693 : nullptr))) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1694 assert(isKernel && "Only kernels can have image/sampler params");
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1695 InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1696 continue;
1697 }
1698
1699 if (theArgs[i]->use_empty()) {
1700 // argument is dead
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1701 if (Ty->isAggregateType()) {
1702 SmallVector<EVT, 16> vtparts;
1703
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1704 ComputePTXValueVTs(*this, Ty, vtparts);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1705 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1706 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1707 ++parti) {
1708 EVT partVT = vtparts[parti];
1709 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, partVT));
1710 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1711 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1712 if (vtparts.size() > 0)
1713 --InsIdx;
1714 continue;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1715 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1716 if (Ty->isVectorTy()) {
1717 EVT ObjectVT = getValueType(Ty);
1718 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
1719 for (unsigned parti = 0; parti < NumRegs; ++parti) {
1720 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1721 ++InsIdx;
1722 }
1723 if (NumRegs > 0)
1724 --InsIdx;
1725 continue;
1726 }
1727 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1728 continue;
1729 }
1730
1731 // In the following cases, assign a node order of "idx+1"
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1732 // to newly created nodes. The SDNodes for params have to
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1733 // appear in the same order as their order of appearance
1734 // in the original function. "idx+1" holds that order.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]1735 if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1736 if (Ty->isAggregateType()) {
1737 SmallVector<EVT, 16> vtparts;
1738 SmallVector<uint64_t, 16> offsets;
1739
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1740 // NOTE: Here, we lose the ability to issue vector loads for vectors
1741 // that are a part of a struct. This should be investigated in the
1742 // future.
1743 ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1744 assert(vtparts.size() > 0 && "empty aggregate type not expected");
1745 bool aggregateIsPacked = false;
1746 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
1747 aggregateIsPacked = STy->isPacked();
1748
1749 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1750 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
1751 ++parti) {
1752 EVT partVT = vtparts[parti];
1753 Value *srcValue = Constant::getNullValue(
1754 PointerType::get(partVT.getTypeForEVT(F->getContext()),
1755 llvm::ADDRESS_SPACE_PARAM));
1756 SDValue srcAddr =
1757 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1758 DAG.getConstant(offsets[parti], getPointerTy()));
1759 unsigned partAlign =
1760 aggregateIsPacked ? 1
1761 : TD->getABITypeAlignment(
1762 partVT.getTypeForEVT(F->getContext()));
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1763 SDValue p;
1764 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
1765 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1766 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1767 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1768 MachinePointerInfo(srcValue), partVT, false,
1769 false, partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1770 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1771 p = DAG.getLoad(partVT, dl, Root, srcAddr,
1772 MachinePointerInfo(srcValue), false, false, false,
1773 partAlign);
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1774 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1775 if (p.getNode())
1776 p.getNode()->setIROrder(idx + 1);
1777 InVals.push_back(p);
1778 ++InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1779 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1780 if (vtparts.size() > 0)
1781 --InsIdx;
Justin Holewinskie9884092013-03-24 21:17:47 +0000[diff] [blame]1782 continue;
1783 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1784 if (Ty->isVectorTy()) {
1785 EVT ObjectVT = getValueType(Ty);
Justin Holewinskiaaaf2892013-06-25 12:22:21 +0000[diff] [blame]1786 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1787 unsigned NumElts = ObjectVT.getVectorNumElements();
1788 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
1789 "Vector was not scalarized");
1790 unsigned Ofst = 0;
1791 EVT EltVT = ObjectVT.getVectorElementType();
1792
1793 // V1 load
1794 // f32 = load ...
1795 if (NumElts == 1) {
1796 // We only have one element, so just directly load it
1797 Value *SrcValue = Constant::getNullValue(PointerType::get(
1798 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1799 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1800 DAG.getConstant(Ofst, getPointerTy()));
1801 SDValue P = DAG.getLoad(
1802 EltVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1803 false, true,
1804 TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
1805 if (P.getNode())
1806 P.getNode()->setIROrder(idx + 1);
1807
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1808 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1809 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1810 InVals.push_back(P);
1811 Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
1812 ++InsIdx;
1813 } else if (NumElts == 2) {
1814 // V2 load
1815 // f32,f32 = load ...
1816 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
1817 Value *SrcValue = Constant::getNullValue(PointerType::get(
1818 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
1819 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1820 DAG.getConstant(Ofst, getPointerTy()));
1821 SDValue P = DAG.getLoad(
1822 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1823 false, true,
1824 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1825 if (P.getNode())
1826 P.getNode()->setIROrder(idx + 1);
1827
1828 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1829 DAG.getIntPtrConstant(0));
1830 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1831 DAG.getIntPtrConstant(1));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1832
1833 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1834 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
1835 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1836 }
1837
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1838 InVals.push_back(Elt0);
1839 InVals.push_back(Elt1);
1840 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1841 InsIdx += 2;
1842 } else {
1843 // V4 loads
1844 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1845 // the
1846 // vector will be expanded to a power of 2 elements, so we know we can
1847 // always round up to the next multiple of 4 when creating the vector
1848 // loads.
1849 // e.g. 4 elem => 1 ld.v4
1850 // 6 elem => 2 ld.v4
1851 // 8 elem => 2 ld.v4
1852 // 11 elem => 3 ld.v4
1853 unsigned VecSize = 4;
1854 if (EltVT.getSizeInBits() == 64) {
1855 VecSize = 2;
1856 }
1857 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1858 for (unsigned i = 0; i < NumElts; i += VecSize) {
1859 Value *SrcValue = Constant::getNullValue(
1860 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
1861 llvm::ADDRESS_SPACE_PARAM));
1862 SDValue SrcAddr =
1863 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
1864 DAG.getConstant(Ofst, getPointerTy()));
1865 SDValue P = DAG.getLoad(
1866 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
1867 false, true,
1868 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
1869 if (P.getNode())
1870 P.getNode()->setIROrder(idx + 1);
1871
1872 for (unsigned j = 0; j < VecSize; ++j) {
1873 if (i + j >= NumElts)
1874 break;
1875 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
1876 DAG.getIntPtrConstant(j));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1877 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1878 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1879 InVals.push_back(Elt);
1880 }
1881 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1882 }
Justin Holewinski4f5bc9b2013-11-11 19:28:16 +0000[diff] [blame]1883 InsIdx += NumElts;
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1884 }
1885
1886 if (NumElts > 0)
1887 --InsIdx;
1888 continue;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1889 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1890 // A plain scalar.
1891 EVT ObjectVT = getValueType(Ty);
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1892 // If ABI, load from the param symbol
1893 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1894 Value *srcValue = Constant::getNullValue(PointerType::get(
1895 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1896 SDValue p;
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1897 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
1898 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1899 ISD::SEXTLOAD : ISD::ZEXTLOAD;
1900 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1901 MachinePointerInfo(srcValue), ObjectVT, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1902 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1903 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1904 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
1905 MachinePointerInfo(srcValue), false, false, false,
Justin Holewinskia2911282013-07-01 12:58:58 +0000[diff] [blame]1906 TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
1907 }
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1908 if (p.getNode())
1909 p.getNode()->setIROrder(idx + 1);
1910 InVals.push_back(p);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1911 continue;
1912 }
1913
1914 // Param has ByVal attribute
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1915 // Return MoveParam(param symbol).
1916 // Ideally, the param symbol can be returned directly,
1917 // but when SDNode builder decides to use it in a CopyToReg(),
1918 // machine instruction fails because TargetExternalSymbol
1919 // (not lowered) is target dependent, and CopyToReg assumes
1920 // the source is lowered.
1921 EVT ObjectVT = getValueType(Ty);
1922 assert(ObjectVT == Ins[InsIdx].VT &&
1923 "Ins type did not match function type");
1924 SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
1925 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
1926 if (p.getNode())
1927 p.getNode()->setIROrder(idx + 1);
1928 if (isKernel)
1929 InVals.push_back(p);
1930 else {
1931 SDValue p2 = DAG.getNode(
1932 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
1933 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
1934 InVals.push_back(p2);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1935 }
1936 }
1937
1938 // Clang will check explicit VarArg and issue error if any. However, Clang
1939 // will let code with
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1940 // implicit var arg like f() pass. See bug 617733.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1941 // We treat this case as if the arg list is empty.
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1942 // if (F.isVarArg()) {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1943 // assert(0 && "VarArg not supported yet!");
1944 //}
1945
1946 if (!OutChains.empty())
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]1947 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1948
1949 return Chain;
1950}
1951
Justin Holewinski44f5c602013-06-28 17:57:53 +0000[diff] [blame]1952
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1953SDValue
1954NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1955 bool isVarArg,
1956 const SmallVectorImpl<ISD::OutputArg> &Outs,
1957 const SmallVectorImpl<SDValue> &OutVals,
1958 SDLoc dl, SelectionDAG &DAG) const {
1959 MachineFunction &MF = DAG.getMachineFunction();
1960 const Function *F = MF.getFunction();
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1961 Type *RetTy = F->getReturnType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1962 const DataLayout *TD = getDataLayout();
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1963
1964 bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1965 assert(isABI && "Non-ABI compilation is not supported");
1966 if (!isABI)
1967 return Chain;
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]1968
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1969 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1970 // If we have a vector type, the OutVals array will be the scalarized
1971 // components and we have combine them into 1 or more vector stores.
1972 unsigned NumElts = VTy->getNumElements();
1973 assert(NumElts == Outs.size() && "Bad scalarization of return value");
1974
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1975 // const_cast can be removed in later LLVM versions
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]1976 EVT EltVT = getValueType(RetTy).getVectorElementType();
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1977 bool NeedExtend = false;
1978 if (EltVT.getSizeInBits() < 16)
1979 NeedExtend = true;
1980
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1981 // V1 store
1982 if (NumElts == 1) {
1983 SDValue StoreVal = OutVals[0];
1984 // We only have one element, so just directly store it
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1985 if (NeedExtend)
1986 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1987 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
1988 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]1989 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1990 EltVT, MachinePointerInfo());
1991
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]1992 } else if (NumElts == 2) {
1993 // V2 store
1994 SDValue StoreVal0 = OutVals[0];
1995 SDValue StoreVal1 = OutVals[1];
1996
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]1997 if (NeedExtend) {
1998 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
1999 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2000 }
2001
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2002 SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
2003 StoreVal1 };
2004 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2005 DAG.getVTList(MVT::Other), Ops,
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2006 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2007 } else {
2008 // V4 stores
2009 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2010 // vector will be expanded to a power of 2 elements, so we know we can
2011 // always round up to the next multiple of 4 when creating the vector
2012 // stores.
2013 // e.g. 4 elem => 1 st.v4
2014 // 6 elem => 2 st.v4
2015 // 8 elem => 2 st.v4
2016 // 11 elem => 3 st.v4
2017
2018 unsigned VecSize = 4;
2019 if (OutVals[0].getValueType().getSizeInBits() == 64)
2020 VecSize = 2;
2021
2022 unsigned Offset = 0;
2023
2024 EVT VecVT =
2025 EVT::getVectorVT(F->getContext(), OutVals[0].getValueType(), VecSize);
2026 unsigned PerStoreOffset =
2027 TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2028
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2029 for (unsigned i = 0; i < NumElts; i += VecSize) {
2030 // Get values
2031 SDValue StoreVal;
2032 SmallVector<SDValue, 8> Ops;
2033 Ops.push_back(Chain);
2034 Ops.push_back(DAG.getConstant(Offset, MVT::i32));
2035 unsigned Opc = NVPTXISD::StoreRetvalV2;
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2036 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2037
2038 StoreVal = OutVals[i];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2039 if (NeedExtend)
2040 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2041 Ops.push_back(StoreVal);
2042
2043 if (i + 1 < NumElts) {
2044 StoreVal = OutVals[i + 1];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2045 if (NeedExtend)
2046 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2047 } else {
2048 StoreVal = DAG.getUNDEF(ExtendedVT);
2049 }
2050 Ops.push_back(StoreVal);
2051
2052 if (VecSize == 4) {
2053 Opc = NVPTXISD::StoreRetvalV4;
2054 if (i + 2 < NumElts) {
2055 StoreVal = OutVals[i + 2];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2056 if (NeedExtend)
2057 StoreVal =
2058 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2059 } else {
2060 StoreVal = DAG.getUNDEF(ExtendedVT);
2061 }
2062 Ops.push_back(StoreVal);
2063
2064 if (i + 3 < NumElts) {
2065 StoreVal = OutVals[i + 3];
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2066 if (NeedExtend)
2067 StoreVal =
2068 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2069 } else {
2070 StoreVal = DAG.getUNDEF(ExtendedVT);
2071 }
2072 Ops.push_back(StoreVal);
2073 }
2074
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2075 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2076 Chain =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2077 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2078 EltVT, MachinePointerInfo());
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2079 Offset += PerStoreOffset;
2080 }
2081 }
2082 } else {
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2083 SmallVector<EVT, 16> ValVTs;
2084 // const_cast is necessary since we are still using an LLVM version from
2085 // before the type system re-write.
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2086 ComputePTXValueVTs(*this, RetTy, ValVTs);
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2087 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2088
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2089 unsigned SizeSoFar = 0;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2090 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2091 SDValue theVal = OutVals[i];
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2092 EVT TheValType = theVal.getValueType();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2093 unsigned numElems = 1;
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2094 if (TheValType.isVector())
2095 numElems = TheValType.getVectorNumElements();
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2096 for (unsigned j = 0, je = numElems; j != je; ++j) {
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2097 SDValue TmpVal = theVal;
2098 if (TheValType.isVector())
2099 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2100 TheValType.getVectorElementType(), TmpVal,
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2101 DAG.getIntPtrConstant(j));
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2102 EVT TheStoreType = ValVTs[i];
2103 if (RetTy->isIntegerTy() &&
2104 TD->getTypeAllocSizeInBits(RetTy) < 32) {
2105 // The following zero-extension is for integer types only, and
2106 // specifically not for aggregates.
2107 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2108 TheStoreType = MVT::i32;
2109 }
2110 else if (TmpVal.getValueType().getSizeInBits() < 16)
2111 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2112
2113 SDValue Ops[] = { Chain, DAG.getConstant(SizeSoFar, MVT::i32), TmpVal };
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2114 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]2115 DAG.getVTList(MVT::Other), Ops,
2116 TheStoreType,
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2117 MachinePointerInfo());
2118 if(TheValType.isVector())
2119 SizeSoFar +=
2120 TheStoreType.getVectorElementType().getStoreSizeInBits() / 8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2121 else
Justin Holewinskie04e4bd2013-06-28 17:58:10 +0000[diff] [blame]2122 SizeSoFar += TheStoreType.getStoreSizeInBits()/8;
Justin Holewinski120baee2013-06-28 17:57:55 +0000[diff] [blame]2123 }
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2124 }
2125 }
2126
2127 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2128}
2129
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2130
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2131void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2132 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2133 SelectionDAG &DAG) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2134 if (Constraint.length() > 1)
2135 return;
2136 else
2137 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2138}
2139
2140// NVPTX suuport vector of legal types of any length in Intrinsics because the
2141// NVPTX specific type legalizer
2142// will legalize them to the PTX supported length.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2143bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2144 if (isTypeLegal(VT))
2145 return true;
2146 if (VT.isVector()) {
2147 MVT eVT = VT.getVectorElementType();
2148 if (isTypeLegal(eVT))
2149 return true;
2150 }
2151 return false;
2152}
2153
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2154static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2155 switch (Intrinsic) {
2156 default:
2157 return 0;
2158
2159 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2160 return NVPTXISD::Tex1DFloatI32;
2161 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2162 return NVPTXISD::Tex1DFloatFloat;
2163 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2164 return NVPTXISD::Tex1DFloatFloatLevel;
2165 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2166 return NVPTXISD::Tex1DFloatFloatGrad;
2167 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2168 return NVPTXISD::Tex1DI32I32;
2169 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2170 return NVPTXISD::Tex1DI32Float;
2171 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2172 return NVPTXISD::Tex1DI32FloatLevel;
2173 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2174 return NVPTXISD::Tex1DI32FloatGrad;
2175
2176 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2177 return NVPTXISD::Tex1DArrayFloatI32;
2178 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2179 return NVPTXISD::Tex1DArrayFloatFloat;
2180 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2181 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2182 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2183 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2184 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2185 return NVPTXISD::Tex1DArrayI32I32;
2186 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2187 return NVPTXISD::Tex1DArrayI32Float;
2188 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2189 return NVPTXISD::Tex1DArrayI32FloatLevel;
2190 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2191 return NVPTXISD::Tex1DArrayI32FloatGrad;
2192
2193 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2194 return NVPTXISD::Tex2DFloatI32;
2195 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2196 return NVPTXISD::Tex2DFloatFloat;
2197 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2198 return NVPTXISD::Tex2DFloatFloatLevel;
2199 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2200 return NVPTXISD::Tex2DFloatFloatGrad;
2201 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2202 return NVPTXISD::Tex2DI32I32;
2203 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2204 return NVPTXISD::Tex2DI32Float;
2205 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2206 return NVPTXISD::Tex2DI32FloatLevel;
2207 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2208 return NVPTXISD::Tex2DI32FloatGrad;
2209
2210 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2211 return NVPTXISD::Tex2DArrayFloatI32;
2212 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2213 return NVPTXISD::Tex2DArrayFloatFloat;
2214 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2215 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2216 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2217 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2218 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2219 return NVPTXISD::Tex2DArrayI32I32;
2220 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2221 return NVPTXISD::Tex2DArrayI32Float;
2222 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2223 return NVPTXISD::Tex2DArrayI32FloatLevel;
2224 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2225 return NVPTXISD::Tex2DArrayI32FloatGrad;
2226
2227 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2228 return NVPTXISD::Tex3DFloatI32;
2229 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2230 return NVPTXISD::Tex3DFloatFloat;
2231 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2232 return NVPTXISD::Tex3DFloatFloatLevel;
2233 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2234 return NVPTXISD::Tex3DFloatFloatGrad;
2235 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2236 return NVPTXISD::Tex3DI32I32;
2237 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2238 return NVPTXISD::Tex3DI32Float;
2239 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2240 return NVPTXISD::Tex3DI32FloatLevel;
2241 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32:
2242 return NVPTXISD::Tex3DI32FloatGrad;
2243 }
2244}
2245
2246static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2247 switch (Intrinsic) {
2248 default:
2249 return 0;
2250 case Intrinsic::nvvm_suld_1d_i8_trap:
2251 return NVPTXISD::Suld1DI8Trap;
2252 case Intrinsic::nvvm_suld_1d_i16_trap:
2253 return NVPTXISD::Suld1DI16Trap;
2254 case Intrinsic::nvvm_suld_1d_i32_trap:
2255 return NVPTXISD::Suld1DI32Trap;
2256 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2257 return NVPTXISD::Suld1DV2I8Trap;
2258 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2259 return NVPTXISD::Suld1DV2I16Trap;
2260 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2261 return NVPTXISD::Suld1DV2I32Trap;
2262 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2263 return NVPTXISD::Suld1DV4I8Trap;
2264 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2265 return NVPTXISD::Suld1DV4I16Trap;
2266 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2267 return NVPTXISD::Suld1DV4I32Trap;
2268 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2269 return NVPTXISD::Suld1DArrayI8Trap;
2270 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2271 return NVPTXISD::Suld1DArrayI16Trap;
2272 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2273 return NVPTXISD::Suld1DArrayI32Trap;
2274 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2275 return NVPTXISD::Suld1DArrayV2I8Trap;
2276 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2277 return NVPTXISD::Suld1DArrayV2I16Trap;
2278 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2279 return NVPTXISD::Suld1DArrayV2I32Trap;
2280 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2281 return NVPTXISD::Suld1DArrayV4I8Trap;
2282 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2283 return NVPTXISD::Suld1DArrayV4I16Trap;
2284 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2285 return NVPTXISD::Suld1DArrayV4I32Trap;
2286 case Intrinsic::nvvm_suld_2d_i8_trap:
2287 return NVPTXISD::Suld2DI8Trap;
2288 case Intrinsic::nvvm_suld_2d_i16_trap:
2289 return NVPTXISD::Suld2DI16Trap;
2290 case Intrinsic::nvvm_suld_2d_i32_trap:
2291 return NVPTXISD::Suld2DI32Trap;
2292 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2293 return NVPTXISD::Suld2DV2I8Trap;
2294 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2295 return NVPTXISD::Suld2DV2I16Trap;
2296 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2297 return NVPTXISD::Suld2DV2I32Trap;
2298 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2299 return NVPTXISD::Suld2DV4I8Trap;
2300 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2301 return NVPTXISD::Suld2DV4I16Trap;
2302 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2303 return NVPTXISD::Suld2DV4I32Trap;
2304 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2305 return NVPTXISD::Suld2DArrayI8Trap;
2306 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2307 return NVPTXISD::Suld2DArrayI16Trap;
2308 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2309 return NVPTXISD::Suld2DArrayI32Trap;
2310 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2311 return NVPTXISD::Suld2DArrayV2I8Trap;
2312 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2313 return NVPTXISD::Suld2DArrayV2I16Trap;
2314 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2315 return NVPTXISD::Suld2DArrayV2I32Trap;
2316 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2317 return NVPTXISD::Suld2DArrayV4I8Trap;
2318 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2319 return NVPTXISD::Suld2DArrayV4I16Trap;
2320 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2321 return NVPTXISD::Suld2DArrayV4I32Trap;
2322 case Intrinsic::nvvm_suld_3d_i8_trap:
2323 return NVPTXISD::Suld3DI8Trap;
2324 case Intrinsic::nvvm_suld_3d_i16_trap:
2325 return NVPTXISD::Suld3DI16Trap;
2326 case Intrinsic::nvvm_suld_3d_i32_trap:
2327 return NVPTXISD::Suld3DI32Trap;
2328 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2329 return NVPTXISD::Suld3DV2I8Trap;
2330 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2331 return NVPTXISD::Suld3DV2I16Trap;
2332 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2333 return NVPTXISD::Suld3DV2I32Trap;
2334 case Intrinsic::nvvm_suld_3d_v4i8_trap:
2335 return NVPTXISD::Suld3DV4I8Trap;
2336 case Intrinsic::nvvm_suld_3d_v4i16_trap:
2337 return NVPTXISD::Suld3DV4I16Trap;
2338 case Intrinsic::nvvm_suld_3d_v4i32_trap:
2339 return NVPTXISD::Suld3DV4I32Trap;
2340 }
2341}
2342
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2343// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
2344// TgtMemIntrinsic
2345// because we need the information that is only available in the "Value" type
2346// of destination
2347// pointer. In particular, the address space information.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2348bool NVPTXTargetLowering::getTgtMemIntrinsic(
2349 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2350 switch (Intrinsic) {
2351 default:
2352 return false;
2353
2354 case Intrinsic::nvvm_atomic_load_add_f32:
2355 Info.opc = ISD::INTRINSIC_W_CHAIN;
2356 Info.memVT = MVT::f32;
2357 Info.ptrVal = I.getArgOperand(0);
2358 Info.offset = 0;
2359 Info.vol = 0;
2360 Info.readMem = true;
2361 Info.writeMem = true;
2362 Info.align = 0;
2363 return true;
2364
2365 case Intrinsic::nvvm_atomic_load_inc_32:
2366 case Intrinsic::nvvm_atomic_load_dec_32:
2367 Info.opc = ISD::INTRINSIC_W_CHAIN;
2368 Info.memVT = MVT::i32;
2369 Info.ptrVal = I.getArgOperand(0);
2370 Info.offset = 0;
2371 Info.vol = 0;
2372 Info.readMem = true;
2373 Info.writeMem = true;
2374 Info.align = 0;
2375 return true;
2376
2377 case Intrinsic::nvvm_ldu_global_i:
2378 case Intrinsic::nvvm_ldu_global_f:
2379 case Intrinsic::nvvm_ldu_global_p:
2380
2381 Info.opc = ISD::INTRINSIC_W_CHAIN;
2382 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2383 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2384 else if (Intrinsic == Intrinsic::nvvm_ldu_global_p)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2385 Info.memVT = getValueType(I.getType());
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2386 else
2387 Info.memVT = MVT::f32;
2388 Info.ptrVal = I.getArgOperand(0);
2389 Info.offset = 0;
2390 Info.vol = 0;
2391 Info.readMem = true;
2392 Info.writeMem = false;
2393 Info.align = 0;
2394 return true;
2395
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2396 case Intrinsic::nvvm_tex_1d_v4f32_i32:
2397 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2398 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2399 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2400 case Intrinsic::nvvm_tex_1d_array_v4f32_i32:
2401 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2402 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2403 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2404 case Intrinsic::nvvm_tex_2d_v4f32_i32:
2405 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2406 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2407 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2408 case Intrinsic::nvvm_tex_2d_array_v4f32_i32:
2409 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2410 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2411 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2412 case Intrinsic::nvvm_tex_3d_v4f32_i32:
2413 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2414 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2415 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32: {
2416 Info.opc = getOpcForTextureInstr(Intrinsic);
2417 Info.memVT = MVT::f32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2418 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2419 Info.offset = 0;
2420 Info.vol = 0;
2421 Info.readMem = true;
2422 Info.writeMem = false;
2423 Info.align = 16;
2424 return true;
2425 }
2426 case Intrinsic::nvvm_tex_1d_v4i32_i32:
2427 case Intrinsic::nvvm_tex_1d_v4i32_f32:
2428 case Intrinsic::nvvm_tex_1d_level_v4i32_f32:
2429 case Intrinsic::nvvm_tex_1d_grad_v4i32_f32:
2430 case Intrinsic::nvvm_tex_1d_array_v4i32_i32:
2431 case Intrinsic::nvvm_tex_1d_array_v4i32_f32:
2432 case Intrinsic::nvvm_tex_1d_array_level_v4i32_f32:
2433 case Intrinsic::nvvm_tex_1d_array_grad_v4i32_f32:
2434 case Intrinsic::nvvm_tex_2d_v4i32_i32:
2435 case Intrinsic::nvvm_tex_2d_v4i32_f32:
2436 case Intrinsic::nvvm_tex_2d_level_v4i32_f32:
2437 case Intrinsic::nvvm_tex_2d_grad_v4i32_f32:
2438 case Intrinsic::nvvm_tex_2d_array_v4i32_i32:
2439 case Intrinsic::nvvm_tex_2d_array_v4i32_f32:
2440 case Intrinsic::nvvm_tex_2d_array_level_v4i32_f32:
2441 case Intrinsic::nvvm_tex_2d_array_grad_v4i32_f32:
2442 case Intrinsic::nvvm_tex_3d_v4i32_i32:
2443 case Intrinsic::nvvm_tex_3d_v4i32_f32:
2444 case Intrinsic::nvvm_tex_3d_level_v4i32_f32:
2445 case Intrinsic::nvvm_tex_3d_grad_v4i32_f32: {
2446 Info.opc = getOpcForTextureInstr(Intrinsic);
2447 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2448 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2449 Info.offset = 0;
2450 Info.vol = 0;
2451 Info.readMem = true;
2452 Info.writeMem = false;
2453 Info.align = 16;
2454 return true;
2455 }
2456 case Intrinsic::nvvm_suld_1d_i8_trap:
2457 case Intrinsic::nvvm_suld_1d_v2i8_trap:
2458 case Intrinsic::nvvm_suld_1d_v4i8_trap:
2459 case Intrinsic::nvvm_suld_1d_array_i8_trap:
2460 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
2461 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
2462 case Intrinsic::nvvm_suld_2d_i8_trap:
2463 case Intrinsic::nvvm_suld_2d_v2i8_trap:
2464 case Intrinsic::nvvm_suld_2d_v4i8_trap:
2465 case Intrinsic::nvvm_suld_2d_array_i8_trap:
2466 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
2467 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
2468 case Intrinsic::nvvm_suld_3d_i8_trap:
2469 case Intrinsic::nvvm_suld_3d_v2i8_trap:
2470 case Intrinsic::nvvm_suld_3d_v4i8_trap: {
2471 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2472 Info.memVT = MVT::i8;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2473 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2474 Info.offset = 0;
2475 Info.vol = 0;
2476 Info.readMem = true;
2477 Info.writeMem = false;
2478 Info.align = 16;
2479 return true;
2480 }
2481 case Intrinsic::nvvm_suld_1d_i16_trap:
2482 case Intrinsic::nvvm_suld_1d_v2i16_trap:
2483 case Intrinsic::nvvm_suld_1d_v4i16_trap:
2484 case Intrinsic::nvvm_suld_1d_array_i16_trap:
2485 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
2486 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
2487 case Intrinsic::nvvm_suld_2d_i16_trap:
2488 case Intrinsic::nvvm_suld_2d_v2i16_trap:
2489 case Intrinsic::nvvm_suld_2d_v4i16_trap:
2490 case Intrinsic::nvvm_suld_2d_array_i16_trap:
2491 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
2492 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
2493 case Intrinsic::nvvm_suld_3d_i16_trap:
2494 case Intrinsic::nvvm_suld_3d_v2i16_trap:
2495 case Intrinsic::nvvm_suld_3d_v4i16_trap: {
2496 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2497 Info.memVT = MVT::i16;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2498 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2499 Info.offset = 0;
2500 Info.vol = 0;
2501 Info.readMem = true;
2502 Info.writeMem = false;
2503 Info.align = 16;
2504 return true;
2505 }
2506 case Intrinsic::nvvm_suld_1d_i32_trap:
2507 case Intrinsic::nvvm_suld_1d_v2i32_trap:
2508 case Intrinsic::nvvm_suld_1d_v4i32_trap:
2509 case Intrinsic::nvvm_suld_1d_array_i32_trap:
2510 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
2511 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
2512 case Intrinsic::nvvm_suld_2d_i32_trap:
2513 case Intrinsic::nvvm_suld_2d_v2i32_trap:
2514 case Intrinsic::nvvm_suld_2d_v4i32_trap:
2515 case Intrinsic::nvvm_suld_2d_array_i32_trap:
2516 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
2517 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
2518 case Intrinsic::nvvm_suld_3d_i32_trap:
2519 case Intrinsic::nvvm_suld_3d_v2i32_trap:
2520 case Intrinsic::nvvm_suld_3d_v4i32_trap: {
2521 Info.opc = getOpcForSurfaceInstr(Intrinsic);
2522 Info.memVT = MVT::i32;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2523 Info.ptrVal = nullptr;
Justin Holewinski30d56a72014-04-09 15:39:15 +0000[diff] [blame]2524 Info.offset = 0;
2525 Info.vol = 0;
2526 Info.readMem = true;
2527 Info.writeMem = false;
2528 Info.align = 16;
2529 return true;
2530 }
2531
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2532 }
2533 return false;
2534}
2535
2536/// isLegalAddressingMode - Return true if the addressing mode represented
2537/// by AM is legal for this target, for a load/store of the specified type.
2538/// Used to guide target specific optimizations, like loop strength reduction
2539/// (LoopStrengthReduce.cpp) and memory optimization for address mode
2540/// (CodeGenPrepare.cpp)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2541bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2542 Type *Ty) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2543
2544 // AddrMode - This represents an addressing mode of:
2545 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2546 //
2547 // The legal address modes are
2548 // - [avar]
2549 // - [areg]
2550 // - [areg+immoff]
2551 // - [immAddr]
2552
2553 if (AM.BaseGV) {
2554 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
2555 return false;
2556 return true;
2557 }
2558
2559 switch (AM.Scale) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2560 case 0: // "r", "r+i" or "i" is allowed
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2561 break;
2562 case 1:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2563 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2564 return false;
2565 // Otherwise we have r+i.
2566 break;
2567 default:
2568 // No scale > 1 is allowed
2569 return false;
2570 }
2571 return true;
2572}
2573
2574//===----------------------------------------------------------------------===//
2575// NVPTX Inline Assembly Support
2576//===----------------------------------------------------------------------===//
2577
2578/// getConstraintType - Given a constraint letter, return the type of
2579/// constraint it is for this target.
2580NVPTXTargetLowering::ConstraintType
2581NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
2582 if (Constraint.size() == 1) {
2583 switch (Constraint[0]) {
2584 default:
2585 break;
2586 case 'r':
2587 case 'h':
2588 case 'c':
2589 case 'l':
2590 case 'f':
2591 case 'd':
2592 case '0':
2593 case 'N':
2594 return C_RegisterClass;
2595 }
2596 }
2597 return TargetLowering::getConstraintType(Constraint);
2598}
2599
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]2600std::pair<unsigned, const TargetRegisterClass *>
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2601NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Chad Rosier295bd432013-06-22 18:37:38 +0000[diff] [blame]2602 MVT VT) const {
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2603 if (Constraint.size() == 1) {
2604 switch (Constraint[0]) {
2605 case 'c':
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]2606 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2607 case 'h':
2608 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
2609 case 'r':
2610 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
2611 case 'l':
2612 case 'N':
2613 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
2614 case 'f':
2615 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
2616 case 'd':
2617 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
2618 }
2619 }
2620 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2621}
2622
Justin Holewinskiae556d32012-05-04 20:18:50 +0000[diff] [blame]2623/// getFunctionAlignment - Return the Log2 alignment of this function.
2624unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
2625 return 4;
2626}
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]2627
Justin Holewinskieafe26d2014-06-27 18:35:37 +0000[diff] [blame]2628//===----------------------------------------------------------------------===//
2629// NVPTX DAG Combining
2630//===----------------------------------------------------------------------===//
2631
2632extern unsigned FMAContractLevel;
2633
2634/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
2635/// operands N0 and N1. This is a helper for PerformADDCombine that is
2636/// called with the default operands, and if that fails, with commuted
2637/// operands.
2638static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
2639 TargetLowering::DAGCombinerInfo &DCI,
2640 const NVPTXSubtarget &Subtarget,
2641 CodeGenOpt::Level OptLevel) {
2642 SelectionDAG &DAG = DCI.DAG;
2643 // Skip non-integer, non-scalar case
2644 EVT VT=N0.getValueType();
2645 if (VT.isVector())
2646 return SDValue();
2647
2648 // fold (add (mul a, b), c) -> (mad a, b, c)
2649 //
2650 if (N0.getOpcode() == ISD::MUL) {
2651 assert (VT.isInteger());
2652 // For integer:
2653 // Since integer multiply-add costs the same as integer multiply
2654 // but is more costly than integer add, do the fusion only when
2655 // the mul is only used in the add.
2656 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
2657 !N0.getNode()->hasOneUse())
2658 return SDValue();
2659
2660 // Do the folding
2661 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
2662 N0.getOperand(0), N0.getOperand(1), N1);
2663 }
2664 else if (N0.getOpcode() == ISD::FMUL) {
2665 if (VT == MVT::f32 || VT == MVT::f64) {
2666 if (FMAContractLevel == 0)
2667 return SDValue();
2668
2669 // For floating point:
2670 // Do the fusion only when the mul has less than 5 uses and all
2671 // are add.
2672 // The heuristic is that if a use is not an add, then that use
2673 // cannot be fused into fma, therefore mul is still needed anyway.
2674 // If there are more than 4 uses, even if they are all add, fusing
2675 // them will increase register pressue.
2676 //
2677 int numUses = 0;
2678 int nonAddCount = 0;
2679 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2680 UE = N0.getNode()->use_end();
2681 UI != UE; ++UI) {
2682 numUses++;
2683 SDNode *User = *UI;
2684 if (User->getOpcode() != ISD::FADD)
2685 ++nonAddCount;
2686 }
2687 if (numUses >= 5)
2688 return SDValue();
2689 if (nonAddCount) {
2690 int orderNo = N->getIROrder();
2691 int orderNo2 = N0.getNode()->getIROrder();
2692 // simple heuristics here for considering potential register
2693 // pressure, the logics here is that the differnce are used
2694 // to measure the distance between def and use, the longer distance
2695 // more likely cause register pressure.
2696 if (orderNo - orderNo2 < 500)
2697 return SDValue();
2698
2699 // Now, check if at least one of the FMUL's operands is live beyond the node N,
2700 // which guarantees that the FMA will not increase register pressure at node N.
2701 bool opIsLive = false;
2702 const SDNode *left = N0.getOperand(0).getNode();
2703 const SDNode *right = N0.getOperand(1).getNode();
2704
2705 if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
2706 opIsLive = true;
2707
2708 if (!opIsLive)
2709 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
2710 SDNode *User = *UI;
2711 int orderNo3 = User->getIROrder();
2712 if (orderNo3 > orderNo) {
2713 opIsLive = true;
2714 break;
2715 }
2716 }
2717
2718 if (!opIsLive)
2719 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
2720 SDNode *User = *UI;
2721 int orderNo3 = User->getIROrder();
2722 if (orderNo3 > orderNo) {
2723 opIsLive = true;
2724 break;
2725 }
2726 }
2727
2728 if (!opIsLive)
2729 return SDValue();
2730 }
2731
2732 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
2733 N0.getOperand(0), N0.getOperand(1), N1);
2734 }
2735 }
2736
2737 return SDValue();
2738}
2739
2740/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2741///
2742static SDValue PerformADDCombine(SDNode *N,
2743 TargetLowering::DAGCombinerInfo &DCI,
2744 const NVPTXSubtarget &Subtarget,
2745 CodeGenOpt::Level OptLevel) {
2746 SDValue N0 = N->getOperand(0);
2747 SDValue N1 = N->getOperand(1);
2748
2749 // First try with the default operand order.
2750 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
2751 OptLevel);
2752 if (Result.getNode())
2753 return Result;
2754
2755 // If that didn't work, try again with the operands commuted.
2756 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
2757}
2758
2759static SDValue PerformANDCombine(SDNode *N,
2760 TargetLowering::DAGCombinerInfo &DCI) {
2761 // The type legalizer turns a vector load of i8 values into a zextload to i16
2762 // registers, optionally ANY_EXTENDs it (if target type is integer),
2763 // and ANDs off the high 8 bits. Since we turn this load into a
2764 // target-specific DAG node, the DAG combiner fails to eliminate these AND
2765 // nodes. Do that here.
2766 SDValue Val = N->getOperand(0);
2767 SDValue Mask = N->getOperand(1);
2768
2769 if (isa<ConstantSDNode>(Val)) {
2770 std::swap(Val, Mask);
2771 }
2772
2773 SDValue AExt;
2774 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
2775 if (Val.getOpcode() == ISD::ANY_EXTEND) {
2776 AExt = Val;
2777 Val = Val->getOperand(0);
2778 }
2779
2780 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
2781 Val = Val->getOperand(0);
2782 }
2783
2784 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
2785 Val->getOpcode() == NVPTXISD::LoadV4) {
2786 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
2787 if (!MaskCnst) {
2788 // Not an AND with a constant
2789 return SDValue();
2790 }
2791
2792 uint64_t MaskVal = MaskCnst->getZExtValue();
2793 if (MaskVal != 0xff) {
2794 // Not an AND that chops off top 8 bits
2795 return SDValue();
2796 }
2797
2798 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
2799 if (!Mem) {
2800 // Not a MemSDNode?!?
2801 return SDValue();
2802 }
2803
2804 EVT MemVT = Mem->getMemoryVT();
2805 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
2806 // We only handle the i8 case
2807 return SDValue();
2808 }
2809
2810 unsigned ExtType =
2811 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
2812 getZExtValue();
2813 if (ExtType == ISD::SEXTLOAD) {
2814 // If for some reason the load is a sextload, the and is needed to zero
2815 // out the high 8 bits
2816 return SDValue();
2817 }
2818
2819 bool AddTo = false;
2820 if (AExt.getNode() != 0) {
2821 // Re-insert the ext as a zext.
2822 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2823 AExt.getValueType(), Val);
2824 AddTo = true;
2825 }
2826
2827 // If we get here, the AND is unnecessary. Just replace it with the load
2828 DCI.CombineTo(N, Val, AddTo);
2829 }
2830
2831 return SDValue();
2832}
2833
2834enum OperandSignedness {
2835 Signed = 0,
2836 Unsigned,
2837 Unknown
2838};
2839
2840/// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
2841/// that can be demoted to \p OptSize bits without loss of information. The
2842/// signedness of the operand, if determinable, is placed in \p S.
2843static bool IsMulWideOperandDemotable(SDValue Op,
2844 unsigned OptSize,
2845 OperandSignedness &S) {
2846 S = Unknown;
2847
2848 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
2849 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2850 EVT OrigVT = Op.getOperand(0).getValueType();
2851 if (OrigVT.getSizeInBits() == OptSize) {
2852 S = Signed;
2853 return true;
2854 }
2855 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
2856 EVT OrigVT = Op.getOperand(0).getValueType();
2857 if (OrigVT.getSizeInBits() == OptSize) {
2858 S = Unsigned;
2859 return true;
2860 }
2861 }
2862
2863 return false;
2864}
2865
2866/// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
2867/// be demoted to \p OptSize bits without loss of information. If the operands
2868/// contain a constant, it should appear as the RHS operand. The signedness of
2869/// the operands is placed in \p IsSigned.
2870static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
2871 unsigned OptSize,
2872 bool &IsSigned) {
2873
2874 OperandSignedness LHSSign;
2875
2876 // The LHS operand must be a demotable op
2877 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
2878 return false;
2879
2880 // We should have been able to determine the signedness from the LHS
2881 if (LHSSign == Unknown)
2882 return false;
2883
2884 IsSigned = (LHSSign == Signed);
2885
2886 // The RHS can be a demotable op or a constant
2887 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
2888 APInt Val = CI->getAPIntValue();
2889 if (LHSSign == Unsigned) {
2890 if (Val.isIntN(OptSize)) {
2891 return true;
2892 }
2893 return false;
2894 } else {
2895 if (Val.isSignedIntN(OptSize)) {
2896 return true;
2897 }
2898 return false;
2899 }
2900 } else {
2901 OperandSignedness RHSSign;
2902 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
2903 return false;
2904
2905 if (LHSSign != RHSSign)
2906 return false;
2907
2908 return true;
2909 }
2910}
2911
2912/// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
2913/// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
2914/// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
2915/// amount.
2916static SDValue TryMULWIDECombine(SDNode *N,
2917 TargetLowering::DAGCombinerInfo &DCI) {
2918 EVT MulType = N->getValueType(0);
2919 if (MulType != MVT::i32 && MulType != MVT::i64) {
2920 return SDValue();
2921 }
2922
2923 unsigned OptSize = MulType.getSizeInBits() >> 1;
2924 SDValue LHS = N->getOperand(0);
2925 SDValue RHS = N->getOperand(1);
2926
2927 // Canonicalize the multiply so the constant (if any) is on the right
2928 if (N->getOpcode() == ISD::MUL) {
2929 if (isa<ConstantSDNode>(LHS)) {
2930 std::swap(LHS, RHS);
2931 }
2932 }
2933
2934 // If we have a SHL, determine the actual multiply amount
2935 if (N->getOpcode() == ISD::SHL) {
2936 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
2937 if (!ShlRHS) {
2938 return SDValue();
2939 }
2940
2941 APInt ShiftAmt = ShlRHS->getAPIntValue();
2942 unsigned BitWidth = MulType.getSizeInBits();
2943 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
2944 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
2945 RHS = DCI.DAG.getConstant(MulVal, MulType);
2946 } else {
2947 return SDValue();
2948 }
2949 }
2950
2951 bool Signed;
2952 // Verify that our operands are demotable
2953 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
2954 return SDValue();
2955 }
2956
2957 EVT DemotedVT;
2958 if (MulType == MVT::i32) {
2959 DemotedVT = MVT::i16;
2960 } else {
2961 DemotedVT = MVT::i32;
2962 }
2963
2964 // Truncate the operands to the correct size. Note that these are just for
2965 // type consistency and will (likely) be eliminated in later phases.
2966 SDValue TruncLHS =
2967 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
2968 SDValue TruncRHS =
2969 DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
2970
2971 unsigned Opc;
2972 if (Signed) {
2973 Opc = NVPTXISD::MUL_WIDE_SIGNED;
2974 } else {
2975 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
2976 }
2977
2978 return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
2979}
2980
2981/// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
2982static SDValue PerformMULCombine(SDNode *N,
2983 TargetLowering::DAGCombinerInfo &DCI,
2984 CodeGenOpt::Level OptLevel) {
2985 if (OptLevel > 0) {
2986 // Try mul.wide combining at OptLevel > 0
2987 SDValue Ret = TryMULWIDECombine(N, DCI);
2988 if (Ret.getNode())
2989 return Ret;
2990 }
2991
2992 return SDValue();
2993}
2994
2995/// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
2996static SDValue PerformSHLCombine(SDNode *N,
2997 TargetLowering::DAGCombinerInfo &DCI,
2998 CodeGenOpt::Level OptLevel) {
2999 if (OptLevel > 0) {
3000 // Try mul.wide combining at OptLevel > 0
3001 SDValue Ret = TryMULWIDECombine(N, DCI);
3002 if (Ret.getNode())
3003 return Ret;
3004 }
3005
3006 return SDValue();
3007}
3008
3009SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
3010 DAGCombinerInfo &DCI) const {
3011 // FIXME: Get this from the DAG somehow
3012 CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
3013 switch (N->getOpcode()) {
3014 default: break;
3015 case ISD::ADD:
3016 case ISD::FADD:
3017 return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
3018 case ISD::MUL:
3019 return PerformMULCombine(N, DCI, OptLevel);
3020 case ISD::SHL:
3021 return PerformSHLCombine(N, DCI, OptLevel);
3022 case ISD::AND:
3023 return PerformANDCombine(N, DCI);
3024 }
3025 return SDValue();
3026}
3027
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3028/// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
3029static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3030 SmallVectorImpl<SDValue> &Results) {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3031 EVT ResVT = N->getValueType(0);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]3032 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3033
3034 assert(ResVT.isVector() && "Vector load must have vector type");
3035
3036 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
3037 // legal. We can (and should) split that into 2 loads of <2 x double> here
3038 // but I'm leaving that as a TODO for now.
3039 assert(ResVT.isSimple() && "Can only handle simple types");
3040 switch (ResVT.getSimpleVT().SimpleTy) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3041 default:
3042 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3043 case MVT::v2i8:
3044 case MVT::v2i16:
3045 case MVT::v2i32:
3046 case MVT::v2i64:
3047 case MVT::v2f32:
3048 case MVT::v2f64:
3049 case MVT::v4i8:
3050 case MVT::v4i16:
3051 case MVT::v4i32:
3052 case MVT::v4f32:
3053 // This is a "native" vector type
3054 break;
3055 }
3056
3057 EVT EltVT = ResVT.getVectorElementType();
3058 unsigned NumElts = ResVT.getVectorNumElements();
3059
3060 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
3061 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]3062 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3063 bool NeedTrunc = false;
3064 if (EltVT.getSizeInBits() < 16) {
3065 EltVT = MVT::i16;
3066 NeedTrunc = true;
3067 }
3068
3069 unsigned Opcode = 0;
3070 SDVTList LdResVTs;
3071
3072 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3073 default:
3074 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3075 case 2:
3076 Opcode = NVPTXISD::LoadV2;
3077 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
3078 break;
3079 case 4: {
3080 Opcode = NVPTXISD::LoadV4;
3081 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]3082 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3083 break;
3084 }
3085 }
3086
3087 SmallVector<SDValue, 8> OtherOps;
3088
3089 // Copy regular operands
3090 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
3091 OtherOps.push_back(N->getOperand(i));
3092
3093 LoadSDNode *LD = cast<LoadSDNode>(N);
3094
3095 // The select routine does not have access to the LoadSDNode instance, so
3096 // pass along the extension information
3097 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
3098
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3099 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
3100 LD->getMemoryVT(),
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3101 LD->getMemOperand());
3102
3103 SmallVector<SDValue, 4> ScalarRes;
3104
3105 for (unsigned i = 0; i < NumElts; ++i) {
3106 SDValue Res = NewLD.getValue(i);
3107 if (NeedTrunc)
3108 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
3109 ScalarRes.push_back(Res);
3110 }
3111
3112 SDValue LoadChain = NewLD.getValue(NumElts);
3113
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]3114 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3115
3116 Results.push_back(BuildVec);
3117 Results.push_back(LoadChain);
3118}
3119
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3120static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3121 SmallVectorImpl<SDValue> &Results) {
3122 SDValue Chain = N->getOperand(0);
3123 SDValue Intrin = N->getOperand(1);
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]3124 SDLoc DL(N);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3125
3126 // Get the intrinsic ID
3127 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3128 switch (IntrinNo) {
3129 default:
3130 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3131 case Intrinsic::nvvm_ldg_global_i:
3132 case Intrinsic::nvvm_ldg_global_f:
3133 case Intrinsic::nvvm_ldg_global_p:
3134 case Intrinsic::nvvm_ldu_global_i:
3135 case Intrinsic::nvvm_ldu_global_f:
3136 case Intrinsic::nvvm_ldu_global_p: {
3137 EVT ResVT = N->getValueType(0);
3138
3139 if (ResVT.isVector()) {
3140 // Vector LDG/LDU
3141
3142 unsigned NumElts = ResVT.getVectorNumElements();
3143 EVT EltVT = ResVT.getVectorElementType();
3144
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3145 // Since LDU/LDG are target nodes, we cannot rely on DAG type
3146 // legalization.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3147 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
Alp Tokercb402912014-01-24 17:20:08 +0000[diff] [blame]3148 // loaded type to i16 and propagate the "real" type as the memory type.
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3149 bool NeedTrunc = false;
3150 if (EltVT.getSizeInBits() < 16) {
3151 EltVT = MVT::i16;
3152 NeedTrunc = true;
3153 }
3154
3155 unsigned Opcode = 0;
3156 SDVTList LdResVTs;
3157
3158 switch (NumElts) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3159 default:
3160 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3161 case 2:
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3162 switch (IntrinNo) {
3163 default:
3164 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3165 case Intrinsic::nvvm_ldg_global_i:
3166 case Intrinsic::nvvm_ldg_global_f:
3167 case Intrinsic::nvvm_ldg_global_p:
3168 Opcode = NVPTXISD::LDGV2;
3169 break;
3170 case Intrinsic::nvvm_ldu_global_i:
3171 case Intrinsic::nvvm_ldu_global_f:
3172 case Intrinsic::nvvm_ldu_global_p:
3173 Opcode = NVPTXISD::LDUV2;
3174 break;
3175 }
3176 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
3177 break;
3178 case 4: {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3179 switch (IntrinNo) {
3180 default:
3181 return;
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3182 case Intrinsic::nvvm_ldg_global_i:
3183 case Intrinsic::nvvm_ldg_global_f:
3184 case Intrinsic::nvvm_ldg_global_p:
3185 Opcode = NVPTXISD::LDGV4;
3186 break;
3187 case Intrinsic::nvvm_ldu_global_i:
3188 case Intrinsic::nvvm_ldu_global_f:
3189 case Intrinsic::nvvm_ldu_global_p:
3190 Opcode = NVPTXISD::LDUV4;
3191 break;
3192 }
3193 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
Craig Topperabb4ac72014-04-16 06:10:51 +0000[diff] [blame]3194 LdResVTs = DAG.getVTList(ListVTs);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3195 break;
3196 }
3197 }
3198
3199 SmallVector<SDValue, 8> OtherOps;
3200
3201 // Copy regular operands
3202
3203 OtherOps.push_back(Chain); // Chain
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3204 // Skip operand 1 (intrinsic ID)
Justin Holewinskif8f70912013-06-28 17:57:59 +0000[diff] [blame]3205 // Others
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3206 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
3207 OtherOps.push_back(N->getOperand(i));
3208
3209 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3210
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3211 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
3212 MemSD->getMemoryVT(),
3213 MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3214
3215 SmallVector<SDValue, 4> ScalarRes;
3216
3217 for (unsigned i = 0; i < NumElts; ++i) {
3218 SDValue Res = NewLD.getValue(i);
3219 if (NeedTrunc)
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3220 Res =
3221 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3222 ScalarRes.push_back(Res);
3223 }
3224
3225 SDValue LoadChain = NewLD.getValue(NumElts);
3226
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3227 SDValue BuildVec =
Craig Topper48d114b2014-04-26 18:35:24 +0000[diff] [blame]3228 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3229
3230 Results.push_back(BuildVec);
3231 Results.push_back(LoadChain);
3232 } else {
3233 // i8 LDG/LDU
3234 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
3235 "Custom handling of non-i8 ldu/ldg?");
3236
3237 // Just copy all operands as-is
3238 SmallVector<SDValue, 4> Ops;
3239 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
3240 Ops.push_back(N->getOperand(i));
3241
3242 // Force output to i16
3243 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
3244
3245 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
3246
3247 // We make sure the memory type is i8, which will be used during isel
3248 // to select the proper instruction.
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3249 SDValue NewLD =
Craig Topper206fcd42014-04-26 19:29:41 +0000[diff] [blame]3250 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
3251 MVT::i8, MemSD->getMemOperand());
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3252
Justin Holewinskie8c93e32013-07-01 12:58:48 +0000[diff] [blame]3253 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
3254 NewLD.getValue(0)));
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3255 Results.push_back(NewLD.getValue(1));
3256 }
3257 }
3258 }
3259}
3260
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3261void NVPTXTargetLowering::ReplaceNodeResults(
3262 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3263 switch (N->getOpcode()) {
Justin Holewinski0497ab12013-03-30 14:29:21 +0000[diff] [blame]3264 default:
3265 report_fatal_error("Unhandled custom legalization");
Justin Holewinskibe8dc642013-02-12 14:18:49 +0000[diff] [blame]3266 case ISD::LOAD:
3267 ReplaceLoadVector(N, DAG, Results);
3268 return;
3269 case ISD::INTRINSIC_W_CHAIN:
3270 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
3271 return;
3272 }
3273}
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]3274
3275// Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
3276void NVPTXSection::anchor() {}
3277
3278NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
3279 delete TextSection;
3280 delete DataSection;
3281 delete BSSSection;
3282 delete ReadOnlySection;
3283
3284 delete StaticCtorSection;
3285 delete StaticDtorSection;
3286 delete LSDASection;
3287 delete EHFrameSection;
3288 delete DwarfAbbrevSection;
3289 delete DwarfInfoSection;
3290 delete DwarfLineSection;
3291 delete DwarfFrameSection;
3292 delete DwarfPubTypesSection;
3293 delete DwarfDebugInlineSection;
3294 delete DwarfStrSection;
3295 delete DwarfLocSection;
3296 delete DwarfARangesSection;
3297 delete DwarfRangesSection;
3298 delete DwarfMacroInfoSection;
3299}