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Dan Gohmanf90d3b02008-12-08 17:50:35 +00001//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===//
Dan Gohman60cb69e2008-11-19 23:18:57 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Matthias Braunbd7d9182017-01-27 18:53:00 +000010/// \file This implements the ScheduleDAGInstrs class, which implements
11/// re-scheduling of MachineInstrs.
Dan Gohman60cb69e2008-11-19 23:18:57 +000012//
13//===----------------------------------------------------------------------===//
14
Chandler Carruth6bda14b2017-06-06 11:49:48 +000015#include "llvm/CodeGen/ScheduleDAGInstrs.h"
Matthias Braun97d0ffb2015-12-04 01:51:19 +000016#include "llvm/ADT/IntEqClasses.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000017#include "llvm/ADT/MapVector.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000018#include "llvm/ADT/SmallPtrSet.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000019#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/SparseSet.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000021#include "llvm/ADT/iterator_range.h"
Dan Gohman1ee0d412009-01-30 02:49:14 +000022#include "llvm/Analysis/AliasAnalysis.h"
Dan Gohmana4fcd242010-12-15 20:02:24 +000023#include "llvm/Analysis/ValueTracking.h"
Matthias Braund4f64092016-01-20 00:23:32 +000024#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000025#include "llvm/CodeGen/LivePhysRegs.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
Arnold Schwaighoferf54b73d2015-05-08 23:52:00 +000027#include "llvm/CodeGen/MachineFrameInfo.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000028#include "llvm/CodeGen/MachineFunction.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000029#include "llvm/CodeGen/MachineInstr.h"
30#include "llvm/CodeGen/MachineInstrBundle.h"
Dan Gohman48b185d2009-09-25 20:36:54 +000031#include "llvm/CodeGen/MachineMemOperand.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000032#include "llvm/CodeGen/MachineOperand.h"
Dan Gohmandddc1ac2008-12-16 03:25:46 +000033#include "llvm/CodeGen/MachineRegisterInfo.h"
Dan Gohman3aab10b2008-12-04 01:35:46 +000034#include "llvm/CodeGen/PseudoSourceValue.h"
Andrew Trick88517f62012-06-06 19:47:35 +000035#include "llvm/CodeGen/RegisterPressure.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000036#include "llvm/CodeGen/ScheduleDAG.h"
Andrew Trickcd1c2f92012-11-28 05:13:24 +000037#include "llvm/CodeGen/ScheduleDFS.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000038#include "llvm/CodeGen/SlotIndexes.h"
39#include "llvm/IR/Constants.h"
Jonas Paulssonac29f012016-02-03 17:52:29 +000040#include "llvm/IR/Function.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000041#include "llvm/IR/Instruction.h"
42#include "llvm/IR/Instructions.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000043#include "llvm/IR/Operator.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000044#include "llvm/IR/Type.h"
45#include "llvm/IR/Value.h"
46#include "llvm/MC/LaneBitmask.h"
47#include "llvm/MC/MCRegisterInfo.h"
48#include "llvm/Support/Casting.h"
Andrew Trickda01ba32012-05-15 18:59:41 +000049#include "llvm/Support/CommandLine.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000050#include "llvm/Support/Compiler.h"
Dan Gohman60cb69e2008-11-19 23:18:57 +000051#include "llvm/Support/Debug.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000052#include "llvm/Support/ErrorHandling.h"
Andrew Trick90f711d2012-10-15 18:02:27 +000053#include "llvm/Support/Format.h"
Dan Gohman60cb69e2008-11-19 23:18:57 +000054#include "llvm/Support/raw_ostream.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000055#include "llvm/Target/TargetRegisterInfo.h"
56#include "llvm/Target/TargetSubtargetInfo.h"
Eugene Zelenko7ea69232017-06-01 23:25:02 +000057#include <algorithm>
58#include <cassert>
59#include <iterator>
60#include <string>
61#include <utility>
62#include <vector>
Andrew Trickc01b0042013-08-23 17:48:43 +000063
Dan Gohman60cb69e2008-11-19 23:18:57 +000064using namespace llvm;
65
Evandro Menezes0cd23f562017-07-11 22:08:28 +000066#define DEBUG_TYPE "machine-scheduler"
Chandler Carruth1b9dde02014-04-22 02:02:50 +000067
Andrew Trickda01ba32012-05-15 18:59:41 +000068static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden,
69 cl::ZeroOrMore, cl::init(false),
Jonas Paulssonbf408bb2015-01-07 13:20:57 +000070 cl::desc("Enable use of AA during MI DAG construction"));
Andrew Trickda01ba32012-05-15 18:59:41 +000071
Hal Finkeldbebb522014-01-25 19:24:54 +000072static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
Jonas Paulssonbf408bb2015-01-07 13:20:57 +000073 cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
Hal Finkeldbebb522014-01-25 19:24:54 +000074
Jonas Paulssonac29f012016-02-03 17:52:29 +000075// Note: the two options below might be used in tuning compile time vs
76// output quality. Setting HugeRegion so large that it will never be
77// reached means best-effort, but may be slow.
78
79// When Stores and Loads maps (or NonAliasStores and NonAliasLoads)
80// together hold this many SUs, a reduction of maps will be done.
81static cl::opt<unsigned> HugeRegion("dag-maps-huge-region", cl::Hidden,
82 cl::init(1000), cl::desc("The limit to use while constructing the DAG "
83 "prior to scheduling, at which point a trade-off "
84 "is made to avoid excessive compile time."));
85
Mehdi Amini59ae8542016-04-16 04:58:30 +000086static cl::opt<unsigned> ReductionSize(
87 "dag-maps-reduction-size", cl::Hidden,
Jonas Paulssonac29f012016-02-03 17:52:29 +000088 cl::desc("A huge scheduling region will have maps reduced by this many "
Mehdi Amini59ae8542016-04-16 04:58:30 +000089 "nodes at a time. Defaults to HugeRegion / 2."));
90
91static unsigned getReductionSize() {
92 // Always reduce a huge region with half of the elements, except
93 // when user sets this number explicitly.
94 if (ReductionSize.getNumOccurrences() == 0)
95 return HugeRegion / 2;
96 return ReductionSize;
97}
Jonas Paulssonac29f012016-02-03 17:52:29 +000098
99static void dumpSUList(ScheduleDAGInstrs::SUList &L) {
100#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
101 dbgs() << "{ ";
Matthias Braun298e0072016-09-30 23:08:07 +0000102 for (const SUnit *su : L) {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000103 dbgs() << "SU(" << su->NodeNum << ")";
104 if (su != L.back())
105 dbgs() << ", ";
106 }
107 dbgs() << "}\n";
108#endif
109}
110
Dan Gohman619ef482009-01-15 19:20:50 +0000111ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
Alexey Samsonov8968e6d2014-08-20 19:36:05 +0000112 const MachineLoopInfo *mli,
Matthias Braun93563e72015-11-03 01:53:29 +0000113 bool RemoveKillFlags)
Matthias Braunb17e8b12015-12-04 19:54:24 +0000114 : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000115 RemoveKillFlags(RemoveKillFlags),
Jonas Paulssonac29f012016-02-03 17:52:29 +0000116 UnknownValue(UndefValue::get(
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000117 Type::getVoidTy(mf.getFunction()->getContext()))) {
Devang Patele5feef02011-06-02 20:07:12 +0000118 DbgValues.clear();
Andrew Trick9b635132012-09-18 18:20:00 +0000119
Eric Christopher2c635492015-01-27 07:54:39 +0000120 const TargetSubtargetInfo &ST = mf.getSubtarget();
Pete Cooper11759452014-09-02 17:43:54 +0000121 SchedModel.init(ST.getSchedModel(), &ST, TII);
Evan Chengf0236e02009-10-18 19:58:47 +0000122}
Dan Gohman60cb69e2008-11-19 23:18:57 +0000123
Matthias Braunbd7d9182017-01-27 18:53:00 +0000124/// If this machine instr has memory reference information and it can be tracked
125/// to a normal reference to a known object, return the Value for that object.
Hal Finkel66859ae2012-12-10 18:49:16 +0000126static void getUnderlyingObjectsForInstr(const MachineInstr *MI,
Matthias Braun941a7052016-07-28 18:40:00 +0000127 const MachineFrameInfo &MFI,
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000128 UnderlyingObjectsVector &Objects,
129 const DataLayout &DL) {
Geoff Berry63817132016-04-14 21:31:07 +0000130 auto allMMOsOkay = [&]() {
131 for (const MachineMemOperand *MMO : MI->memoperands()) {
132 if (MMO->isVolatile())
133 return false;
Hal Finkel66859ae2012-12-10 18:49:16 +0000134
Geoff Berry63817132016-04-14 21:31:07 +0000135 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
136 // Function that contain tail calls don't have unique PseudoSourceValue
137 // objects. Two PseudoSourceValues might refer to the same or
138 // overlapping locations. The client code calling this function assumes
139 // this is not the case. So return a conservative answer of no known
140 // object.
Matthias Braun941a7052016-07-28 18:40:00 +0000141 if (MFI.hasTailCall())
Geoff Berry63817132016-04-14 21:31:07 +0000142 return false;
Geoff Berryc0739d82016-04-12 15:50:19 +0000143
Geoff Berry63817132016-04-14 21:31:07 +0000144 // For now, ignore PseudoSourceValues which may alias LLVM IR values
145 // because the code that uses this function has no way to cope with
146 // such aliases.
Matthias Braun941a7052016-07-28 18:40:00 +0000147 if (PSV->isAliased(&MFI))
Geoff Berry63817132016-04-14 21:31:07 +0000148 return false;
Geoff Berryc0739d82016-04-12 15:50:19 +0000149
Matthias Braun941a7052016-07-28 18:40:00 +0000150 bool MayAlias = PSV->mayAlias(&MFI);
Geoff Berry63817132016-04-14 21:31:07 +0000151 Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias));
152 } else if (const Value *V = MMO->getValue()) {
153 SmallVector<Value *, 4> Objs;
Hiroshi Inoueb9417db2017-08-01 03:32:15 +0000154 getUnderlyingObjectsForCodeGen(V, Objs, DL);
Geoff Berryc0739d82016-04-12 15:50:19 +0000155
Geoff Berry63817132016-04-14 21:31:07 +0000156 for (Value *V : Objs) {
Hiroshi Inoueb9417db2017-08-01 03:32:15 +0000157 assert(isIdentifiedObject(V));
Geoff Berry63817132016-04-14 21:31:07 +0000158 Objects.push_back(UnderlyingObjectsVector::value_type(V, true));
Geoff Berryc0739d82016-04-12 15:50:19 +0000159 }
Geoff Berry63817132016-04-14 21:31:07 +0000160 } else
161 return false;
Geoff Berryc0739d82016-04-12 15:50:19 +0000162 }
Geoff Berry63817132016-04-14 21:31:07 +0000163 return true;
164 };
165
166 if (!allMMOsOkay())
167 Objects.clear();
Dan Gohman1ee0d412009-01-30 02:49:14 +0000168}
169
Andrew Trick7405c6d2012-04-20 20:05:21 +0000170void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) {
171 BB = bb;
Dan Gohmanb9543432009-02-10 23:27:53 +0000172}
173
Andrew Trick52226d42012-03-07 23:00:49 +0000174void ScheduleDAGInstrs::finishBlock() {
Andrew Trick51ee9362012-04-20 20:24:33 +0000175 // Subclasses should no longer refer to the old block.
Craig Topperc0196b12014-04-14 00:51:57 +0000176 BB = nullptr;
Andrew Trick60cf03e2012-03-07 05:21:52 +0000177}
178
Andrew Trick60cf03e2012-03-07 05:21:52 +0000179void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
180 MachineBasicBlock::iterator begin,
181 MachineBasicBlock::iterator end,
Andrew Tricka53e1012013-08-23 17:48:33 +0000182 unsigned regioninstrs) {
Andrew Trick7405c6d2012-04-20 20:05:21 +0000183 assert(bb == BB && "startBlock should set BB");
Andrew Trick8c207e42012-03-09 04:29:02 +0000184 RegionBegin = begin;
185 RegionEnd = end;
Andrew Tricka53e1012013-08-23 17:48:33 +0000186 NumRegionInstrs = regioninstrs;
Andrew Trick60cf03e2012-03-07 05:21:52 +0000187}
188
Andrew Trick60cf03e2012-03-07 05:21:52 +0000189void ScheduleDAGInstrs::exitRegion() {
190 // Nothing to do.
191}
192
Andrew Trick52226d42012-03-07 23:00:49 +0000193void ScheduleDAGInstrs::addSchedBarrierDeps() {
Craig Topperc0196b12014-04-14 00:51:57 +0000194 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
Evan Cheng15459b62010-10-23 02:10:46 +0000195 ExitSU.setInstr(ExitMI);
Matthias Braun325cd2c2016-11-11 01:34:21 +0000196 // Add dependencies on the defs and uses of the instruction.
197 if (ExitMI) {
Matthias Braun298e0072016-09-30 23:08:07 +0000198 for (const MachineOperand &MO : ExitMI->operands()) {
Evan Cheng15459b62010-10-23 02:10:46 +0000199 if (!MO.isReg() || MO.isDef()) continue;
200 unsigned Reg = MO.getReg();
Matthias Braun111603f2016-11-10 22:11:00 +0000201 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000202 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
Matthias Braun111603f2016-11-10 22:11:00 +0000203 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
Matthias Braun298e0072016-09-30 23:08:07 +0000204 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
Matthias Braun111603f2016-11-10 22:11:00 +0000205 }
Evan Cheng15459b62010-10-23 02:10:46 +0000206 }
Matthias Braun325cd2c2016-11-11 01:34:21 +0000207 }
208 if (!ExitMI || (!ExitMI->isCall() && !ExitMI->isBarrier())) {
Evan Cheng15459b62010-10-23 02:10:46 +0000209 // For others, e.g. fallthrough, conditional branch, assume the exit
Evan Chengcbdf7e82010-10-27 23:17:17 +0000210 // uses all the registers that are livein to the successor blocks.
Matthias Braun298e0072016-09-30 23:08:07 +0000211 for (const MachineBasicBlock *Succ : BB->successors()) {
212 for (const auto &LI : Succ->liveins()) {
Matthias Braund9da1622015-09-09 18:08:03 +0000213 if (!Uses.contains(LI.PhysReg))
214 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
Evan Chengcbdf7e82010-10-27 23:17:17 +0000215 }
Matthias Braun298e0072016-09-30 23:08:07 +0000216 }
Evan Cheng15459b62010-10-23 02:10:46 +0000217 }
218}
219
Matthias Braunbd7d9182017-01-27 18:53:00 +0000220/// MO is an operand of SU's instruction that defines a physical register. Adds
Andrew Trickd675a4c2012-02-23 01:52:38 +0000221/// data dependencies from SU to any uses of the physical register.
Andrew Trickae535612012-08-23 00:39:43 +0000222void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
223 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
Andrew Trickd675a4c2012-02-23 01:52:38 +0000224 assert(MO.isDef() && "expect physreg def");
225
226 // Ask the target if address-backscheduling is desirable, and if so how much.
Eric Christopher2c635492015-01-27 07:54:39 +0000227 const TargetSubtargetInfo &ST = MF.getSubtarget();
Andrew Trickd675a4c2012-02-23 01:52:38 +0000228
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000229 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
230 Alias.isValid(); ++Alias) {
Andrew Trick9dbbd3e2012-02-24 07:04:55 +0000231 if (!Uses.contains(*Alias))
Andrew Trickd675a4c2012-02-23 01:52:38 +0000232 continue;
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000233 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
234 SUnit *UseSU = I->SU;
Andrew Trickd675a4c2012-02-23 01:52:38 +0000235 if (UseSU == SU)
236 continue;
Andrew Trick07dced62012-10-08 18:54:00 +0000237
Andrew Trick07dced62012-10-08 18:54:00 +0000238 // Adjust the dependence latency using operand def/use information,
239 // then allow the target to perform its own adjustments.
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000240 int UseOp = I->OpIdx;
Craig Topperc0196b12014-04-14 00:51:57 +0000241 MachineInstr *RegUse = nullptr;
Andrew Trickf1ff84c2012-11-12 19:28:57 +0000242 SDep Dep;
243 if (UseOp < 0)
244 Dep = SDep(SU, SDep::Artificial);
245 else {
Andrew Tricke833e1c2013-04-13 06:07:40 +0000246 // Set the hasPhysRegDefs only for physreg defs that have a use within
247 // the scheduling region.
248 SU->hasPhysRegDefs = true;
Andrew Trickf1ff84c2012-11-12 19:28:57 +0000249 Dep = SDep(SU, SDep::Data, *Alias);
250 RegUse = UseSU->getInstr();
Andrew Trickf1ff84c2012-11-12 19:28:57 +0000251 }
252 Dep.setLatency(
Andrew Trickde2109e2013-06-15 04:49:57 +0000253 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
254 UseOp));
Andrew Trick45446062012-06-05 21:11:27 +0000255
Andrew Trickf1ff84c2012-11-12 19:28:57 +0000256 ST.adjustSchedDependency(SU, UseSU, Dep);
257 UseSU->addPred(Dep);
Andrew Trickd675a4c2012-02-23 01:52:38 +0000258 }
259 }
260}
261
Matthias Braunbd7d9182017-01-27 18:53:00 +0000262/// \brief Adds register dependencies (data, anti, and output) from this SUnit
263/// to following instructions in the same scheduling region that depend the
264/// physical register referenced at OperIdx.
Andrew Trickdbee9d82012-01-14 02:17:15 +0000265void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
Andrew Trick6b104f82013-12-28 21:56:55 +0000266 MachineInstr *MI = SU->getInstr();
267 MachineOperand &MO = MI->getOperand(OperIdx);
Matthias Braun111603f2016-11-10 22:11:00 +0000268 unsigned Reg = MO.getReg();
Matthias Braunf29b12d2016-11-10 23:46:44 +0000269 // We do not need to track any dependencies for constant registers.
270 if (MRI.isConstantPhysReg(Reg))
271 return;
Andrew Trickdbee9d82012-01-14 02:17:15 +0000272
273 // Optionally add output and anti dependencies. For anti
274 // dependencies we use a latency of 0 because for a multi-issue
275 // target we want to allow the defining instruction to issue
276 // in the same cycle as the using instruction.
277 // TODO: Using a latency of 1 here for output dependencies assumes
278 // there's no cost for reusing registers.
279 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
Matthias Braun111603f2016-11-10 22:11:00 +0000280 for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
Andrew Trick9dbbd3e2012-02-24 07:04:55 +0000281 if (!Defs.contains(*Alias))
Andrew Trickd675a4c2012-02-23 01:52:38 +0000282 continue;
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000283 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
284 SUnit *DefSU = I->SU;
Andrew Trickdbee9d82012-01-14 02:17:15 +0000285 if (DefSU == &ExitSU)
286 continue;
287 if (DefSU != SU &&
288 (Kind != SDep::Output || !MO.isDead() ||
Hal Finkel66d77912014-12-05 02:07:35 +0000289 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
Andrew Trickdbee9d82012-01-14 02:17:15 +0000290 if (Kind == SDep::Anti)
Andrew Trickbaeaabb2012-11-06 03:13:46 +0000291 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
Andrew Trickdbee9d82012-01-14 02:17:15 +0000292 else {
Andrew Trickbaeaabb2012-11-06 03:13:46 +0000293 SDep Dep(SU, Kind, /*Reg=*/*Alias);
Andrew Trickde2109e2013-06-15 04:49:57 +0000294 Dep.setLatency(
295 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
Andrew Trickbaeaabb2012-11-06 03:13:46 +0000296 DefSU->addPred(Dep);
Andrew Trickdbee9d82012-01-14 02:17:15 +0000297 }
298 }
299 }
300 }
301
Andrew Trickd675a4c2012-02-23 01:52:38 +0000302 if (!MO.isDef()) {
Andrew Tricke833e1c2013-04-13 06:07:40 +0000303 SU->hasPhysRegUses = true;
Andrew Trickd675a4c2012-02-23 01:52:38 +0000304 // Either insert a new Reg2SUnits entry with an empty SUnits list, or
305 // retrieve the existing SUnits list for this register's uses.
306 // Push this SUnit on the use list.
Matthias Braun111603f2016-11-10 22:11:00 +0000307 Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
Andrew Trick6b104f82013-12-28 21:56:55 +0000308 if (RemoveKillFlags)
309 MO.setIsKill(false);
Matthias Braun111603f2016-11-10 22:11:00 +0000310 } else {
Andrew Trickae535612012-08-23 00:39:43 +0000311 addPhysRegDataDeps(SU, OperIdx);
Andrew Trickdbee9d82012-01-14 02:17:15 +0000312
Andrew Trickd675a4c2012-02-23 01:52:38 +0000313 // clear this register's use list
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000314 if (Uses.contains(Reg))
315 Uses.eraseAll(Reg);
Andrew Trickd675a4c2012-02-23 01:52:38 +0000316
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000317 if (!MO.isDead()) {
318 Defs.eraseAll(Reg);
319 } else if (SU->isCall) {
320 // Calls will not be reordered because of chain dependencies (see
321 // below). Since call operands are dead, calls may continue to be added
322 // to the DefList making dependence checking quadratic in the size of
323 // the block. Instead, we leave only one call at the back of the
324 // DefList.
325 Reg2SUnitsMap::RangePair P = Defs.equal_range(Reg);
326 Reg2SUnitsMap::iterator B = P.first;
327 Reg2SUnitsMap::iterator I = P.second;
328 for (bool isBegin = I == B; !isBegin; /* empty */) {
329 isBegin = (--I) == B;
330 if (!I->SU->isCall)
331 break;
332 I = Defs.erase(I);
333 }
Andrew Trickdbee9d82012-01-14 02:17:15 +0000334 }
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000335
Andrew Trickd675a4c2012-02-23 01:52:38 +0000336 // Defs are pushed in the order they are visited and never reordered.
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000337 Defs.insert(PhysRegSUOper(SU, OperIdx, Reg));
Andrew Trickdbee9d82012-01-14 02:17:15 +0000338 }
339}
340
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000341LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
342{
343 unsigned Reg = MO.getReg();
344 // No point in tracking lanemasks if we don't have interesting subregisters.
345 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
346 if (!RC.HasDisjunctSubRegs)
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000347 return LaneBitmask::getAll();
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000348
349 unsigned SubReg = MO.getSubReg();
350 if (SubReg == 0)
351 return RC.getLaneMask();
352 return TRI->getSubRegIndexLaneMask(SubReg);
353}
354
Matthias Braunbd7d9182017-01-27 18:53:00 +0000355/// Adds register output and data dependencies from this SUnit to instructions
356/// that occur later in the same scheduling region if they read from or write to
357/// the virtual register defined at OperIdx.
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000358///
359/// TODO: Hoist loop induction variable increments. This has to be
360/// reevaluated. Generally, IV scheduling should be done before coalescing.
361void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000362 MachineInstr *MI = SU->getInstr();
363 MachineOperand &MO = MI->getOperand(OperIdx);
364 unsigned Reg = MO.getReg();
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000365
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000366 LaneBitmask DefLaneMask;
367 LaneBitmask KillLaneMask;
368 if (TrackLaneMasks) {
369 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
370 DefLaneMask = getLaneMaskForMO(MO);
371 // If we have a <read-undef> flag, none of the lane values comes from an
372 // earlier instruction.
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000373 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask;
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000374
375 // Clear undef flag, we'll re-add it later once we know which subregister
376 // Def is first.
377 MO.setIsUndef(false);
378 } else {
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000379 DefLaneMask = LaneBitmask::getAll();
380 KillLaneMask = LaneBitmask::getAll();
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000381 }
382
383 if (MO.isDead()) {
384 assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
385 "Dead defs should have no uses");
386 } else {
387 // Add data dependence to all uses we found so far.
388 const TargetSubtargetInfo &ST = MF.getSubtarget();
389 for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
390 E = CurrentVRegUses.end(); I != E; /*empty*/) {
391 LaneBitmask LaneMask = I->LaneMask;
392 // Ignore uses of other lanes.
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000393 if ((LaneMask & KillLaneMask).none()) {
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000394 ++I;
395 continue;
396 }
397
Krzysztof Parzyszekea9f8ce2016-12-16 19:11:56 +0000398 if ((LaneMask & DefLaneMask).any()) {
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000399 SUnit *UseSU = I->SU;
400 MachineInstr *Use = UseSU->getInstr();
401 SDep Dep(SU, SDep::Data, Reg);
402 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
403 I->OperandIndex));
404 ST.adjustSchedDependency(SU, UseSU, Dep);
405 UseSU->addPred(Dep);
406 }
407
408 LaneMask &= ~KillLaneMask;
409 // If we found a Def for all lanes of this use, remove it from the list.
Krzysztof Parzyszekea9f8ce2016-12-16 19:11:56 +0000410 if (LaneMask.any()) {
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000411 I->LaneMask = LaneMask;
412 ++I;
413 } else
414 I = CurrentVRegUses.erase(I);
415 }
416 }
417
418 // Shortcut: Singly defined vregs do not have output/anti dependencies.
Andrew Trick79795892012-07-30 23:48:17 +0000419 if (MRI.hasOneDef(Reg))
Andrew Trick94053432012-07-28 01:48:15 +0000420 return;
Andrew Trickdb42c6f2012-02-22 06:08:13 +0000421
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000422 // Add output dependence to the next nearest defs of this vreg.
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000423 //
424 // Unless this definition is dead, the output dependence should be
425 // transitively redundant with antidependencies from this definition's
426 // uses. We're conservative for now until we have a way to guarantee the uses
427 // are not eliminated sometime during scheduling. The output dependence edge
428 // is also useful if output latency exceeds def-use latency.
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000429 LaneBitmask LaneMask = DefLaneMask;
430 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
431 CurrentVRegDefs.end())) {
432 // Ignore defs for other lanes.
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000433 if ((V2SU.LaneMask & LaneMask).none())
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000434 continue;
435 // Add an output dependence.
436 SUnit *DefSU = V2SU.SU;
437 // Ignore additional defs of the same lanes in one instruction. This can
438 // happen because lanemasks are shared for targets with too many
439 // subregisters. We also use some representration tricks/hacks where we
440 // add super-register defs/uses, to imply that although we only access parts
441 // of the reg we care about the full one.
442 if (DefSU == SU)
443 continue;
444 SDep Dep(SU, SDep::Output, Reg);
445 Dep.setLatency(
446 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
447 DefSU->addPred(Dep);
448
449 // Update current definition. This can get tricky if the def was about a
450 // bigger lanemask before. We then have to shrink it and create a new
451 // VReg2SUnit for the non-overlapping part.
452 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
453 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000454 V2SU.SU = SU;
455 V2SU.LaneMask = OverlapMask;
Krzysztof Parzyszekea9f8ce2016-12-16 19:11:56 +0000456 if (NonOverlapMask.any())
Matthias Braun4c994ee2016-05-25 01:18:00 +0000457 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000458 }
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000459 // If there was no CurrentVRegDefs entry for some lanes yet, create one.
Krzysztof Parzyszekea9f8ce2016-12-16 19:11:56 +0000460 if (LaneMask.any())
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000461 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000462}
463
Matthias Braunbd7d9182017-01-27 18:53:00 +0000464/// \brief Adds a register data dependency if the instruction that defines the
465/// virtual register used at OperIdx is mapped to an SUnit. Add a register
466/// antidependency from this SUnit to instructions that occur later in the same
467/// scheduling region if they write the virtual register.
Andrew Trick46cc9a42012-02-22 06:08:11 +0000468///
469/// TODO: Handle ExitSU "uses" properly.
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000470void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000471 const MachineInstr *MI = SU->getInstr();
472 const MachineOperand &MO = MI->getOperand(OperIdx);
473 unsigned Reg = MO.getReg();
Andrew Trick46cc9a42012-02-22 06:08:11 +0000474
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000475 // Remember the use. Data dependencies will be added when we find the def.
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000476 LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO)
477 : LaneBitmask::getAll();
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000478 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
479
480 // Add antidependences to the following defs of the vreg.
481 for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
482 CurrentVRegDefs.end())) {
483 // Ignore defs for unrelated lanes.
484 LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
Krzysztof Parzyszek91b5cf82016-12-15 14:36:06 +0000485 if ((PrevDefLaneMask & LaneMask).none())
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000486 continue;
487 if (V2SU.SU == SU)
488 continue;
489
490 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
Andrew Trick2bc74c22013-08-30 04:36:57 +0000491 }
Andrew Trick46cc9a42012-02-22 06:08:11 +0000492}
Andrew Trick59ac4fb2012-01-14 02:17:18 +0000493
Matthias Braunbd7d9182017-01-27 18:53:00 +0000494/// Returns true if MI is an instruction we are unable to reason about
Andrew Trickda01ba32012-05-15 18:59:41 +0000495/// (like a call or something with unmodeled side effects).
496static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) {
Rafael Espindola84921b92015-10-24 23:11:13 +0000497 return MI->isCall() || MI->hasUnmodeledSideEffects() ||
Justin Lebard98cf002016-09-10 01:03:20 +0000498 (MI->hasOrderedMemoryRef() && !MI->isDereferenceableInvariantLoad(AA));
Andrew Trickda01ba32012-05-15 18:59:41 +0000499}
500
Jonas Paulssonac29f012016-02-03 17:52:29 +0000501void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
502 unsigned Latency) {
Eli Friedman93f47e52017-03-09 23:33:36 +0000503 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000504 SDep Dep(SUa, SDep::MayAliasMem);
505 Dep.setLatency(Latency);
Andrew Trickbaeaabb2012-11-06 03:13:46 +0000506 SUb->addPred(Dep);
507 }
Andrew Trickda01ba32012-05-15 18:59:41 +0000508}
509
Matthias Braunbd7d9182017-01-27 18:53:00 +0000510/// \brief Creates an SUnit for each real instruction, numbered in top-down
511/// topological order. The instruction order A < B, implies that no edge exists
512/// from B to A.
Andrew Trick46cc9a42012-02-22 06:08:11 +0000513///
514/// Map each real instruction to its SUnit.
515///
Andrew Trick8823dec2012-03-14 04:00:41 +0000516/// After initSUnits, the SUnits vector cannot be resized and the scheduler may
517/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
518/// instead of pointers.
519///
520/// MachineScheduler relies on initSUnits numbering the nodes by their order in
521/// the original instruction list.
Andrew Trick46cc9a42012-02-22 06:08:11 +0000522void ScheduleDAGInstrs::initSUnits() {
523 // We'll be allocating one SUnit for each real instruction in the region,
524 // which is contained within a basic block.
Andrew Tricka53e1012013-08-23 17:48:33 +0000525 SUnits.reserve(NumRegionInstrs);
Andrew Trick46cc9a42012-02-22 06:08:11 +0000526
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000527 for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000528 if (MI.isDebugValue())
Andrew Trick46cc9a42012-02-22 06:08:11 +0000529 continue;
530
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000531 SUnit *SU = newSUnit(&MI);
532 MISUnitMap[&MI] = SU;
Andrew Trick46cc9a42012-02-22 06:08:11 +0000533
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000534 SU->isCall = MI.isCall();
535 SU->isCommutable = MI.isCommutable();
Andrew Trick46cc9a42012-02-22 06:08:11 +0000536
537 // Assign the Latency field of SU using target-provided information.
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000538 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
Andrew Trick880e5732013-12-05 17:55:58 +0000539
Andrew Trick1766f932014-04-18 17:35:08 +0000540 // If this SUnit uses a reserved or unbuffered resource, mark it as such.
541 //
Alp Tokerbeaca192014-05-15 01:52:21 +0000542 // Reserved resources block an instruction from issuing and stall the
Andrew Trick1766f932014-04-18 17:35:08 +0000543 // entire pipeline. These are identified by BufferSize=0.
544 //
Alp Tokerbeaca192014-05-15 01:52:21 +0000545 // Unbuffered resources prevent execution of subsequent instructions that
Andrew Trick1766f932014-04-18 17:35:08 +0000546 // require the same resources. This is used for in-order execution pipelines
547 // within an out-of-order core. These are identified by BufferSize=1.
Andrew Trick880e5732013-12-05 17:55:58 +0000548 if (SchedModel.hasInstrSchedModel()) {
549 const MCSchedClassDesc *SC = getSchedClass(SU);
Matthias Braun298e0072016-09-30 23:08:07 +0000550 for (const MCWriteProcResEntry &PRE :
551 make_range(SchedModel.getWriteProcResBegin(SC),
552 SchedModel.getWriteProcResEnd(SC))) {
553 switch (SchedModel.getProcResource(PRE.ProcResourceIdx)->BufferSize) {
Andrew Trick5a22df42013-12-05 17:56:02 +0000554 case 0:
555 SU->hasReservedResource = true;
556 break;
557 case 1:
Andrew Trick880e5732013-12-05 17:55:58 +0000558 SU->isUnbuffered = true;
559 break;
Andrew Trick5a22df42013-12-05 17:56:02 +0000560 default:
561 break;
Andrew Trick880e5732013-12-05 17:55:58 +0000562 }
563 }
564 }
Andrew Trick46cc9a42012-02-22 06:08:11 +0000565 }
Andrew Trickdbee9d82012-01-14 02:17:15 +0000566}
567
Jonas Paulssonac29f012016-02-03 17:52:29 +0000568class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000569 /// Current total number of SUs in map.
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000570 unsigned NumNodes = 0;
Jonas Paulssonac29f012016-02-03 17:52:29 +0000571
572 /// 1 for loads, 0 for stores. (see comment in SUList)
573 unsigned TrueMemOrderLatency;
Jonas Paulssonac29f012016-02-03 17:52:29 +0000574
Matthias Braunbd7d9182017-01-27 18:53:00 +0000575public:
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000576 Value2SUsMap(unsigned lat = 0) : TrueMemOrderLatency(lat) {}
Jonas Paulssonac29f012016-02-03 17:52:29 +0000577
578 /// To keep NumNodes up to date, insert() is used instead of
579 /// this operator w/ push_back().
580 ValueType &operator[](const SUList &Key) {
581 llvm_unreachable("Don't use. Use insert() instead."); };
582
Matthias Braunbd7d9182017-01-27 18:53:00 +0000583 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
584 /// reduce().
Jonas Paulssonac29f012016-02-03 17:52:29 +0000585 void inline insert(SUnit *SU, ValueType V) {
586 MapVector::operator[](V).push_back(SU);
587 NumNodes++;
588 }
589
590 /// Clears the list of SUs mapped to V.
591 void inline clearList(ValueType V) {
592 iterator Itr = find(V);
593 if (Itr != end()) {
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000594 assert(NumNodes >= Itr->second.size());
Jonas Paulssonac29f012016-02-03 17:52:29 +0000595 NumNodes -= Itr->second.size();
596
597 Itr->second.clear();
598 }
599 }
600
601 /// Clears map from all contents.
602 void clear() {
603 MapVector<ValueType, SUList>::clear();
604 NumNodes = 0;
605 }
606
607 unsigned inline size() const { return NumNodes; }
608
Matthias Braunbd7d9182017-01-27 18:53:00 +0000609 /// Counts the number of SUs in this map after a reduction.
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000610 void reComputeSize() {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000611 NumNodes = 0;
612 for (auto &I : *this)
613 NumNodes += I.second.size();
614 }
615
616 unsigned inline getTrueMemOrderLatency() const {
617 return TrueMemOrderLatency;
618 }
619
620 void dump();
621};
622
623void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
624 Value2SUsMap &Val2SUsMap) {
625 for (auto &I : Val2SUsMap)
626 addChainDependencies(SU, I.second,
627 Val2SUsMap.getTrueMemOrderLatency());
628}
629
630void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
631 Value2SUsMap &Val2SUsMap,
632 ValueType V) {
633 Value2SUsMap::iterator Itr = Val2SUsMap.find(V);
634 if (Itr != Val2SUsMap.end())
635 addChainDependencies(SU, Itr->second,
636 Val2SUsMap.getTrueMemOrderLatency());
637}
638
639void ScheduleDAGInstrs::addBarrierChain(Value2SUsMap &map) {
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000640 assert(BarrierChain != nullptr);
Jonas Paulssonac29f012016-02-03 17:52:29 +0000641
642 for (auto &I : map) {
643 SUList &sus = I.second;
644 for (auto *SU : sus)
645 SU->addPredBarrier(BarrierChain);
646 }
647 map.clear();
648}
649
650void ScheduleDAGInstrs::insertBarrierChain(Value2SUsMap &map) {
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000651 assert(BarrierChain != nullptr);
Jonas Paulssonac29f012016-02-03 17:52:29 +0000652
653 // Go through all lists of SUs.
654 for (Value2SUsMap::iterator I = map.begin(), EE = map.end(); I != EE;) {
655 Value2SUsMap::iterator CurrItr = I++;
656 SUList &sus = CurrItr->second;
657 SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
658 for (; SUItr != SUEE; ++SUItr) {
659 // Stop on BarrierChain or any instruction above it.
660 if ((*SUItr)->NodeNum <= BarrierChain->NodeNum)
661 break;
662
663 (*SUItr)->addPredBarrier(BarrierChain);
664 }
665
666 // Remove also the BarrierChain from list if present.
NAKAMURA Takumibc46f622016-05-02 17:29:55 +0000667 if (SUItr != SUEE && *SUItr == BarrierChain)
Jonas Paulssonac29f012016-02-03 17:52:29 +0000668 SUItr++;
669
670 // Remove all SUs that are now successors of BarrierChain.
671 if (SUItr != sus.begin())
672 sus.erase(sus.begin(), SUItr);
673 }
674
675 // Remove all entries with empty su lists.
676 map.remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
677 return (mapEntry.second.empty()); });
678
679 // Recompute the size of the map (NumNodes).
680 map.reComputeSize();
681}
682
Andrew Trick88639922012-04-24 17:56:43 +0000683void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
Andrew Trick1a831342013-08-30 03:49:48 +0000684 RegPressureTracker *RPTracker,
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000685 PressureDiffs *PDiffs,
Matthias Braund4f64092016-01-20 00:23:32 +0000686 LiveIntervals *LIS,
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000687 bool TrackLaneMasks) {
Eric Christopher2c635492015-01-27 07:54:39 +0000688 const TargetSubtargetInfo &ST = MF.getSubtarget();
Hal Finkelb350ffd2013-08-29 03:25:05 +0000689 bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
690 : ST.useAA();
Jonas Paulssonac29f012016-02-03 17:52:29 +0000691 AAForDep = UseAA ? AA : nullptr;
692
693 BarrierChain = nullptr;
Hal Finkelb350ffd2013-08-29 03:25:05 +0000694
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000695 this->TrackLaneMasks = TrackLaneMasks;
Andrew Trick310190e2013-09-04 21:00:02 +0000696 MISUnitMap.clear();
697 ScheduleDAG::clearDAG();
698
Andrew Trick46cc9a42012-02-22 06:08:11 +0000699 // Create an SUnit for each real instruction.
700 initSUnits();
Dan Gohman60cb69e2008-11-19 23:18:57 +0000701
Andrew Trick1a831342013-08-30 03:49:48 +0000702 if (PDiffs)
703 PDiffs->init(SUnits.size());
704
Jonas Paulssonac29f012016-02-03 17:52:29 +0000705 // We build scheduling units by walking a block's instruction list
706 // from bottom to top.
Dan Gohman3aab10b2008-12-04 01:35:46 +0000707
Jonas Paulssonac29f012016-02-03 17:52:29 +0000708 // Each MIs' memory operand(s) is analyzed to a list of underlying
Jonas Paulsson22936852016-02-04 13:08:48 +0000709 // objects. The SU is then inserted in the SUList(s) mapped from the
710 // Value(s). Each Value thus gets mapped to lists of SUs depending
711 // on it, stores and loads kept separately. Two SUs are trivially
712 // non-aliasing if they both depend on only identified Values and do
713 // not share any common Value.
Jonas Paulssonac29f012016-02-03 17:52:29 +0000714 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/);
Dan Gohman3aab10b2008-12-04 01:35:46 +0000715
Jonas Paulssonac29f012016-02-03 17:52:29 +0000716 // Certain memory accesses are known to not alias any SU in Stores
717 // or Loads, and have therefore their own 'NonAlias'
718 // domain. E.g. spill / reload instructions never alias LLVM I/R
Jonas Paulsson22936852016-02-04 13:08:48 +0000719 // Values. It would be nice to assume that this type of memory
720 // accesses always have a proper memory operand modelling, and are
721 // therefore never unanalyzable, but this is conservatively not
722 // done.
Jonas Paulssonac29f012016-02-03 17:52:29 +0000723 Value2SUsMap NonAliasStores, NonAliasLoads(1 /*TrueMemOrderLatency*/);
724
Dale Johannesen49de0602010-03-10 22:13:47 +0000725 // Remove any stale debug info; sometimes BuildSchedGraph is called again
726 // without emitting the info from the previous call.
Devang Patele5feef02011-06-02 20:07:12 +0000727 DbgValues.clear();
Craig Topperc0196b12014-04-14 00:51:57 +0000728 FirstDbgValue = nullptr;
Dale Johannesen49de0602010-03-10 22:13:47 +0000729
Andrew Trickd675a4c2012-02-23 01:52:38 +0000730 assert(Defs.empty() && Uses.empty() &&
731 "Only BuildGraph should update Defs/Uses");
Michael Ilseman3e3194f2013-01-21 18:18:53 +0000732 Defs.setUniverse(TRI->getNumRegs());
733 Uses.setUniverse(TRI->getNumRegs());
Andrew Trick2e116a42011-05-06 21:52:52 +0000734
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000735 assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
736 assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
737 unsigned NumVirtRegs = MRI.getNumVirtRegs();
738 CurrentVRegDefs.setUniverse(NumVirtRegs);
739 CurrentVRegUses.setUniverse(NumVirtRegs);
740
Andrew Trickd675a4c2012-02-23 01:52:38 +0000741 // Model data dependencies between instructions being scheduled and the
742 // ExitSU.
Andrew Trick52226d42012-03-07 23:00:49 +0000743 addSchedBarrierDeps();
Andrew Trickd675a4c2012-02-23 01:52:38 +0000744
Dan Gohmanb9543432009-02-10 23:27:53 +0000745 // Walk the list of instructions, from bottom moving up.
Craig Topperc0196b12014-04-14 00:51:57 +0000746 MachineInstr *DbgMI = nullptr;
Andrew Trick8c207e42012-03-09 04:29:02 +0000747 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
Dan Gohman60cb69e2008-11-19 23:18:57 +0000748 MII != MIE; --MII) {
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000749 MachineInstr &MI = *std::prev(MII);
750 if (DbgMI) {
751 DbgValues.push_back(std::make_pair(DbgMI, &MI));
Craig Topperc0196b12014-04-14 00:51:57 +0000752 DbgMI = nullptr;
Devang Patele5feef02011-06-02 20:07:12 +0000753 }
754
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000755 if (MI.isDebugValue()) {
756 DbgMI = &MI;
Dale Johannesen49de0602010-03-10 22:13:47 +0000757 continue;
758 }
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000759 SUnit *SU = MISUnitMap[&MI];
Andrew Trick1a831342013-08-30 03:49:48 +0000760 assert(SU && "No SUnit mapped to this MI");
761
Andrew Trick88639922012-04-24 17:56:43 +0000762 if (RPTracker) {
Matthias Braunb505c762016-01-12 22:57:35 +0000763 RegisterOperands RegOpers;
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000764 RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
Matthias Braund4f64092016-01-20 00:23:32 +0000765 if (TrackLaneMasks) {
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000766 SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
Matthias Braund4f64092016-01-20 00:23:32 +0000767 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
768 }
Matthias Braunb505c762016-01-12 22:57:35 +0000769 if (PDiffs != nullptr)
770 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
771
772 RPTracker->recedeSkipDebugValues();
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000773 assert(&*RPTracker->getPos() == &MI && "RPTracker in sync");
Matthias Braunb505c762016-01-12 22:57:35 +0000774 RPTracker->recede(RegOpers);
Andrew Trick88639922012-04-24 17:56:43 +0000775 }
Devang Patele5feef02011-06-02 20:07:12 +0000776
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000777 assert(
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000778 (CanHandleTerminators || (!MI.isTerminator() && !MI.isPosition())) &&
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000779 "Cannot schedule terminators or labels!");
Dan Gohman60cb69e2008-11-19 23:18:57 +0000780
Dan Gohman3aab10b2008-12-04 01:35:46 +0000781 // Add register-based dependencies (data, anti, and output).
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000782 // For some instructions (calls, returns, inline-asm, etc.) there can
783 // be explicit uses and implicit defs, in which case the use will appear
784 // on the operand list before the def. Do two passes over the operand
785 // list to make sure that defs are processed before any uses.
Andrew Trickec256482012-12-18 20:53:01 +0000786 bool HasVRegDef = false;
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000787 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
788 const MachineOperand &MO = MI.getOperand(j);
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000789 if (!MO.isReg() || !MO.isDef())
790 continue;
Dan Gohman60cb69e2008-11-19 23:18:57 +0000791 unsigned Reg = MO.getReg();
Matthias Braun111603f2016-11-10 22:11:00 +0000792 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
Andrew Trickdbee9d82012-01-14 02:17:15 +0000793 addPhysRegDeps(SU, j);
Matthias Braun111603f2016-11-10 22:11:00 +0000794 } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000795 HasVRegDef = true;
796 addVRegDefDeps(SU, j);
Dan Gohman60cb69e2008-11-19 23:18:57 +0000797 }
798 }
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000799 // Now process all uses.
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000800 for (unsigned j = 0, n = MI.getNumOperands(); j != n; ++j) {
801 const MachineOperand &MO = MI.getOperand(j);
Matthias Braun8a5b4672016-05-10 20:11:58 +0000802 // Only look at use operands.
803 // We do not need to check for MO.readsReg() here because subsequent
804 // subregister defs will get output dependence edges and need no
805 // additional use dependencies.
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000806 if (!MO.isReg() || !MO.isUse())
807 continue;
808 unsigned Reg = MO.getReg();
Matthias Braun111603f2016-11-10 22:11:00 +0000809 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000810 addPhysRegDeps(SU, j);
Matthias Braun111603f2016-11-10 22:11:00 +0000811 } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000812 addVRegUseDeps(SU, j);
Matthias Braun111603f2016-11-10 22:11:00 +0000813 }
Krzysztof Parzyszeka356bb72016-05-10 16:50:30 +0000814 }
815
Andrew Trickec256482012-12-18 20:53:01 +0000816 // If we haven't seen any uses in this scheduling region, create a
817 // dependence edge to ExitSU to model the live-out latency. This is required
818 // for vreg defs with no in-region use, and prefetches with no vreg def.
819 //
820 // FIXME: NumDataSuccs would be more precise than NumSuccs here. This
821 // check currently relies on being called before adding chain deps.
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000822 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
Andrew Trickec256482012-12-18 20:53:01 +0000823 SDep Dep(SU, SDep::Artificial);
824 Dep.setLatency(SU->Latency - 1);
825 ExitSU.addPred(Dep);
826 }
Dan Gohman3aab10b2008-12-04 01:35:46 +0000827
Jonas Paulssonac29f012016-02-03 17:52:29 +0000828 // Add memory dependencies (Note: isStoreToStackSlot and
829 // isLoadFromStackSLot are not usable after stack slots are lowered to
830 // actual addresses).
831
832 // This is a barrier event that acts as a pivotal node in the DAG.
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000833 if (isGlobalMemoryObject(AA, &MI)) {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000834
835 // Become the barrier chain.
David Goodwind2f9c042009-11-09 19:22:17 +0000836 if (BarrierChain)
Jonas Paulssonac29f012016-02-03 17:52:29 +0000837 BarrierChain->addPredBarrier(SU);
David Goodwind2f9c042009-11-09 19:22:17 +0000838 BarrierChain = SU;
839
Jonas Paulssonac29f012016-02-03 17:52:29 +0000840 DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
841 << BarrierChain->NodeNum << ").\n";);
Tom Stellard3e01d472014-12-08 23:36:48 +0000842
Jonas Paulssonac29f012016-02-03 17:52:29 +0000843 // Add dependencies against everything below it and clear maps.
844 addBarrierChain(Stores);
845 addBarrierChain(Loads);
846 addBarrierChain(NonAliasStores);
847 addBarrierChain(NonAliasLoads);
Hal Finkel66859ae2012-12-10 18:49:16 +0000848
Jonas Paulssonac29f012016-02-03 17:52:29 +0000849 continue;
850 }
851
852 // If it's not a store or a variant load, we're done.
Justin Lebard98cf002016-09-10 01:03:20 +0000853 if (!MI.mayStore() &&
854 !(MI.mayLoad() && !MI.isDereferenceableInvariantLoad(AA)))
Jonas Paulssonac29f012016-02-03 17:52:29 +0000855 continue;
856
857 // Always add dependecy edge to BarrierChain if present.
858 if (BarrierChain)
859 BarrierChain->addPredBarrier(SU);
860
861 // Find the underlying objects for MI. The Objs vector is either
862 // empty, or filled with the Values of memory locations which this
863 // SU depends on. An empty vector means the memory location is
Jonas Paulsson98963fe2016-02-15 16:43:15 +0000864 // unknown, and may alias anything.
Jonas Paulssonac29f012016-02-03 17:52:29 +0000865 UnderlyingObjectsVector Objs;
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000866 getUnderlyingObjectsForInstr(&MI, MFI, Objs, MF.getDataLayout());
Jonas Paulssonac29f012016-02-03 17:52:29 +0000867
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +0000868 if (MI.mayStore()) {
Hal Finkel66859ae2012-12-10 18:49:16 +0000869 if (Objs.empty()) {
Jonas Paulssonac29f012016-02-03 17:52:29 +0000870 // An unknown store depends on all stores and loads.
871 addChainDependencies(SU, Stores);
872 addChainDependencies(SU, NonAliasStores);
873 addChainDependencies(SU, Loads);
874 addChainDependencies(SU, NonAliasLoads);
875
876 // Map this store to 'UnknownValue'.
877 Stores.insert(SU, UnknownValue);
Chandler Carruthb4728562016-03-31 21:55:58 +0000878 } else {
879 // Add precise dependencies against all previously seen memory
880 // accesses mapped to the same Value(s).
Geoff Berry63817132016-04-14 21:31:07 +0000881 for (const UnderlyingObject &UnderlObj : Objs) {
882 ValueType V = UnderlObj.getValue();
883 bool ThisMayAlias = UnderlObj.mayAlias();
Chandler Carruthb4728562016-03-31 21:55:58 +0000884
885 // Add dependencies to previous stores and loads mapped to V.
Geoff Berry63817132016-04-14 21:31:07 +0000886 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
Chandler Carruthb4728562016-03-31 21:55:58 +0000887 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
Geoff Berryc0739d82016-04-12 15:50:19 +0000888 }
889 // Update the store map after all chains have been added to avoid adding
890 // self-loop edge if multiple underlying objects are present.
Geoff Berry63817132016-04-14 21:31:07 +0000891 for (const UnderlyingObject &UnderlObj : Objs) {
892 ValueType V = UnderlObj.getValue();
893 bool ThisMayAlias = UnderlObj.mayAlias();
Chandler Carruthb4728562016-03-31 21:55:58 +0000894
895 // Map this store to V.
Geoff Berry63817132016-04-14 21:31:07 +0000896 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
Chandler Carruthb4728562016-03-31 21:55:58 +0000897 }
898 // The store may have dependencies to unanalyzable loads and
899 // stores.
900 addChainDependencies(SU, Loads, UnknownValue);
901 addChainDependencies(SU, Stores, UnknownValue);
Hal Finkel66859ae2012-12-10 18:49:16 +0000902 }
Chandler Carruthb4728562016-03-31 21:55:58 +0000903 } else { // SU is a load.
Jonas Paulssonac29f012016-02-03 17:52:29 +0000904 if (Objs.empty()) {
905 // An unknown load depends on all stores.
906 addChainDependencies(SU, Stores);
907 addChainDependencies(SU, NonAliasStores);
908
909 Loads.insert(SU, UnknownValue);
Chandler Carruthb4728562016-03-31 21:55:58 +0000910 } else {
Geoff Berry63817132016-04-14 21:31:07 +0000911 for (const UnderlyingObject &UnderlObj : Objs) {
912 ValueType V = UnderlObj.getValue();
913 bool ThisMayAlias = UnderlObj.mayAlias();
Chandler Carruthb4728562016-03-31 21:55:58 +0000914
915 // Add precise dependencies against all previously seen stores
916 // mapping to the same Value(s).
917 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
918
919 // Map this load to V.
920 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
921 }
922 // The load may have dependencies to unanalyzable stores.
923 addChainDependencies(SU, Stores, UnknownValue);
Hal Finkel66859ae2012-12-10 18:49:16 +0000924 }
Jonas Paulssonac29f012016-02-03 17:52:29 +0000925 }
926
927 // Reduce maps if they grow huge.
928 if (Stores.size() + Loads.size() >= HugeRegion) {
929 DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
Mehdi Amini59ae8542016-04-16 04:58:30 +0000930 reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
Jonas Paulssonac29f012016-02-03 17:52:29 +0000931 }
932 if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
933 DEBUG(dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
Mehdi Amini59ae8542016-04-16 04:58:30 +0000934 reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
Dan Gohman60cb69e2008-11-19 23:18:57 +0000935 }
Dan Gohman60cb69e2008-11-19 23:18:57 +0000936 }
Jonas Paulssonac29f012016-02-03 17:52:29 +0000937
Andrew Trickb767d1e2012-12-01 01:22:49 +0000938 if (DbgMI)
939 FirstDbgValue = DbgMI;
Dan Gohman619ef482009-01-15 19:20:50 +0000940
Andrew Trickd675a4c2012-02-23 01:52:38 +0000941 Defs.clear();
942 Uses.clear();
Matthias Braun97d0ffb2015-12-04 01:51:19 +0000943 CurrentVRegDefs.clear();
944 CurrentVRegUses.clear();
Jonas Paulssonac29f012016-02-03 17:52:29 +0000945}
946
947raw_ostream &llvm::operator<<(raw_ostream &OS, const PseudoSourceValue* PSV) {
948 PSV->printCustom(OS);
949 return OS;
950}
951
952void ScheduleDAGInstrs::Value2SUsMap::dump() {
953 for (auto &Itr : *this) {
954 if (Itr.first.is<const Value*>()) {
955 const Value *V = Itr.first.get<const Value*>();
956 if (isa<UndefValue>(V))
957 dbgs() << "Unknown";
958 else
959 V->printAsOperand(dbgs());
960 }
961 else if (Itr.first.is<const PseudoSourceValue*>())
962 dbgs() << Itr.first.get<const PseudoSourceValue*>();
963 else
964 llvm_unreachable("Unknown Value type.");
965
966 dbgs() << " : ";
967 dumpSUList(Itr.second);
968 }
969}
970
Jonas Paulssonac29f012016-02-03 17:52:29 +0000971void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
972 Value2SUsMap &loads, unsigned N) {
973 DEBUG(dbgs() << "Before reduction:\nStoring SUnits:\n";
974 stores.dump();
975 dbgs() << "Loading SUnits:\n";
976 loads.dump());
977
978 // Insert all SU's NodeNums into a vector and sort it.
979 std::vector<unsigned> NodeNums;
980 NodeNums.reserve(stores.size() + loads.size());
981 for (auto &I : stores)
982 for (auto *SU : I.second)
983 NodeNums.push_back(SU->NodeNum);
984 for (auto &I : loads)
985 for (auto *SU : I.second)
986 NodeNums.push_back(SU->NodeNum);
987 std::sort(NodeNums.begin(), NodeNums.end());
988
989 // The N last elements in NodeNums will be removed, and the SU with
990 // the lowest NodeNum of them will become the new BarrierChain to
991 // let the not yet seen SUs have a dependency to the removed SUs.
Eugene Zelenko7ea69232017-06-01 23:25:02 +0000992 assert(N <= NodeNums.size());
Jonas Paulssonac29f012016-02-03 17:52:29 +0000993 SUnit *newBarrierChain = &SUnits[*(NodeNums.end() - N)];
994 if (BarrierChain) {
995 // The aliasing and non-aliasing maps reduce independently of each
996 // other, but share a common BarrierChain. Check if the
997 // newBarrierChain is above the former one. If it is not, it may
998 // introduce a loop to use newBarrierChain, so keep the old one.
999 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
1000 BarrierChain->addPredBarrier(newBarrierChain);
1001 BarrierChain = newBarrierChain;
1002 DEBUG(dbgs() << "Inserting new barrier chain: SU("
1003 << BarrierChain->NodeNum << ").\n";);
1004 }
1005 else
1006 DEBUG(dbgs() << "Keeping old barrier chain: SU("
1007 << BarrierChain->NodeNum << ").\n";);
1008 }
1009 else
1010 BarrierChain = newBarrierChain;
1011
1012 insertBarrierChain(stores);
1013 insertBarrierChain(loads);
1014
1015 DEBUG(dbgs() << "After reduction:\nStoring SUnits:\n";
1016 stores.dump();
1017 dbgs() << "Loading SUnits:\n";
1018 loads.dump());
Dan Gohman60cb69e2008-11-19 23:18:57 +00001019}
1020
Matthias Braun868bbd42017-05-27 02:50:50 +00001021static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
1022 MachineInstr &MI, bool addToLiveRegs) {
1023 for (MachineOperand &MO : MI.operands()) {
1024 if (!MO.isReg() || !MO.readsReg())
1025 continue;
1026 unsigned Reg = MO.getReg();
1027 if (!Reg)
1028 continue;
Andrew Trick6b104f82013-12-28 21:56:55 +00001029
Matthias Braun868bbd42017-05-27 02:50:50 +00001030 // Things that are available after the instruction are killed by it.
1031 bool IsKill = LiveRegs.available(MRI, Reg);
1032 MO.setIsKill(IsKill);
Matthias Braune2ae0012017-06-27 00:58:48 +00001033 if (addToLiveRegs)
Matthias Braun868bbd42017-05-27 02:50:50 +00001034 LiveRegs.addReg(Reg);
Andrew Trick6b104f82013-12-28 21:56:55 +00001035 }
1036}
1037
Matthias Braun868bbd42017-05-27 02:50:50 +00001038void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
1039 DEBUG(dbgs() << "Fixup kills for BB#" << MBB.getNumber() << '\n');
Pete Cooper300069a2015-05-04 16:52:06 +00001040
Matthias Braun868bbd42017-05-27 02:50:50 +00001041 LiveRegs.init(*TRI);
1042 LiveRegs.addLiveOuts(MBB);
Andrew Trick6b104f82013-12-28 21:56:55 +00001043
1044 // Examine block from end to start...
Matthias Braun868bbd42017-05-27 02:50:50 +00001045 for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
Duncan P. N. Exon Smithb77911b2016-07-01 16:21:48 +00001046 if (MI.isDebugValue())
Andrew Trick6b104f82013-12-28 21:56:55 +00001047 continue;
1048
1049 // Update liveness. Registers that are defed but not used in this
1050 // instruction are now dead. Mark register and all subregs as they
1051 // are completely defined.
Matthias Braun868bbd42017-05-27 02:50:50 +00001052 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
1053 const MachineOperand &MO = *O;
1054 if (MO.isReg()) {
1055 if (!MO.isDef())
1056 continue;
1057 unsigned Reg = MO.getReg();
1058 if (!Reg)
1059 continue;
1060 LiveRegs.removeReg(Reg);
1061 } else if (MO.isRegMask()) {
1062 LiveRegs.removeRegsInMask(MO);
1063 }
Andrew Trick6b104f82013-12-28 21:56:55 +00001064 }
1065
Matthias Braun868bbd42017-05-27 02:50:50 +00001066 // If there is a bundle header fix it up first.
1067 if (!MI.isBundled()) {
1068 toggleKills(MRI, LiveRegs, MI, true);
1069 } else {
1070 MachineBasicBlock::instr_iterator First = MI.getIterator();
1071 if (MI.isBundle()) {
1072 toggleKills(MRI, LiveRegs, MI, false);
1073 ++First;
Andrew Trick6b104f82013-12-28 21:56:55 +00001074 }
Matthias Braun868bbd42017-05-27 02:50:50 +00001075 // Some targets make the (questionable) assumtion that the instructions
1076 // inside the bundle are ordered and consequently only the last use of
1077 // a register inside the bundle can kill it.
1078 MachineBasicBlock::instr_iterator I = std::next(First);
1079 while (I->isBundledWithSucc())
1080 ++I;
1081 do {
1082 if (!I->isDebugValue())
1083 toggleKills(MRI, LiveRegs, *I, true);
1084 --I;
1085 } while(I != First);
Andrew Trick6b104f82013-12-28 21:56:55 +00001086 }
1087 }
1088}
1089
Dan Gohman60cb69e2008-11-19 23:18:57 +00001090void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
Matthias Braun8c209aa2017-01-28 02:02:38 +00001091 // Cannot completely remove virtual function even in release mode.
Manman Ren19f49ac2012-09-11 22:23:19 +00001092#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
Dan Gohman60cb69e2008-11-19 23:18:57 +00001093 SU->getInstr()->dump();
Manman Ren742534c2012-09-06 19:06:06 +00001094#endif
Dan Gohman60cb69e2008-11-19 23:18:57 +00001095}
1096
1097std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
Alp Tokere69170a2014-06-26 22:52:05 +00001098 std::string s;
1099 raw_string_ostream oss(s);
Dan Gohmanb9543432009-02-10 23:27:53 +00001100 if (SU == &EntrySU)
1101 oss << "<entry>";
1102 else if (SU == &ExitSU)
1103 oss << "<exit>";
1104 else
Eric Christopher1cdefae2015-02-27 00:11:34 +00001105 SU->getInstr()->print(oss, /*SkipOpers=*/true);
Dan Gohman60cb69e2008-11-19 23:18:57 +00001106 return oss.str();
1107}
1108
Andrew Trick1b2324d2012-03-07 00:18:22 +00001109/// Return the basic block label. It is not necessarilly unique because a block
1110/// contains multiple scheduling regions. But it is fine for visualization.
1111std::string ScheduleDAGInstrs::getDAGName() const {
1112 return "dag." + BB->getFullName();
1113}
Andrew Trick90f711d2012-10-15 18:02:27 +00001114
Andrew Trick48d392e2012-11-28 05:13:28 +00001115//===----------------------------------------------------------------------===//
1116// SchedDFSResult Implementation
1117//===----------------------------------------------------------------------===//
1118
1119namespace llvm {
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001120
Matthias Braunbd7d9182017-01-27 18:53:00 +00001121/// Internal state used to compute SchedDFSResult.
Andrew Trick48d392e2012-11-28 05:13:28 +00001122class SchedDFSImpl {
1123 SchedDFSResult &R;
1124
1125 /// Join DAG nodes into equivalence classes by their subtree.
1126 IntEqClasses SubtreeClasses;
1127 /// List PredSU, SuccSU pairs that represent data edges between subtrees.
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001128 std::vector<std::pair<const SUnit *, const SUnit*>> ConnectionPairs;
Andrew Trick48d392e2012-11-28 05:13:28 +00001129
Andrew Trickffc80972013-01-25 06:52:27 +00001130 struct RootData {
1131 unsigned NodeID;
Matthias Braunbd7d9182017-01-27 18:53:00 +00001132 unsigned ParentNodeID; ///< Parent node (member of the parent subtree).
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001133 unsigned SubInstrCount = 0; ///< Instr count in this tree only, not
1134 /// children.
Andrew Trickffc80972013-01-25 06:52:27 +00001135
1136 RootData(unsigned id): NodeID(id),
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001137 ParentNodeID(SchedDFSResult::InvalidSubtreeID) {}
Andrew Trickffc80972013-01-25 06:52:27 +00001138
1139 unsigned getSparseSetIndex() const { return NodeID; }
1140 };
1141
1142 SparseSet<RootData> RootSet;
1143
Andrew Trick48d392e2012-11-28 05:13:28 +00001144public:
Andrew Trickffc80972013-01-25 06:52:27 +00001145 SchedDFSImpl(SchedDFSResult &r): R(r), SubtreeClasses(R.DFSNodeData.size()) {
1146 RootSet.setUniverse(R.DFSNodeData.size());
1147 }
Andrew Trick48d392e2012-11-28 05:13:28 +00001148
Matthias Braunbd7d9182017-01-27 18:53:00 +00001149 /// Returns true if this node been visited by the DFS traversal.
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001150 ///
1151 /// During visitPostorderNode the Node's SubtreeID is assigned to the Node
1152 /// ID. Later, SubtreeID is updated but remains valid.
Andrew Trick48d392e2012-11-28 05:13:28 +00001153 bool isVisited(const SUnit *SU) const {
Andrew Trickffc80972013-01-25 06:52:27 +00001154 return R.DFSNodeData[SU->NodeNum].SubtreeID
1155 != SchedDFSResult::InvalidSubtreeID;
Andrew Trick48d392e2012-11-28 05:13:28 +00001156 }
1157
Matthias Braunbd7d9182017-01-27 18:53:00 +00001158 /// Initializes this node's instruction count. We don't need to flag the node
Andrew Trick48d392e2012-11-28 05:13:28 +00001159 /// visited until visitPostorder because the DAG cannot have cycles.
1160 void visitPreorder(const SUnit *SU) {
Andrew Trickffc80972013-01-25 06:52:27 +00001161 R.DFSNodeData[SU->NodeNum].InstrCount =
1162 SU->getInstr()->isTransient() ? 0 : 1;
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001163 }
1164
1165 /// Called once for each node after all predecessors are visited. Revisit this
1166 /// node's predecessors and potentially join them now that we know the ILP of
1167 /// the other predecessors.
1168 void visitPostorderNode(const SUnit *SU) {
1169 // Mark this node as the root of a subtree. It may be joined with its
1170 // successors later.
Andrew Trickffc80972013-01-25 06:52:27 +00001171 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1172 RootData RData(SU->NodeNum);
1173 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
Andrew Trick48d392e2012-11-28 05:13:28 +00001174
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001175 // If any predecessors are still in their own subtree, they either cannot be
1176 // joined or are large enough to remain separate. If this parent node's
1177 // total instruction count is not greater than a child subtree by at least
1178 // the subtree limit, then try to join it now since splitting subtrees is
1179 // only useful if multiple high-pressure paths are possible.
Andrew Trickffc80972013-01-25 06:52:27 +00001180 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
Matthias Braun298e0072016-09-30 23:08:07 +00001181 for (const SDep &PredDep : SU->Preds) {
1182 if (PredDep.getKind() != SDep::Data)
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001183 continue;
Matthias Braun298e0072016-09-30 23:08:07 +00001184 unsigned PredNum = PredDep.getSUnit()->NodeNum;
Andrew Trickffc80972013-01-25 06:52:27 +00001185 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
Matthias Braun298e0072016-09-30 23:08:07 +00001186 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
Andrew Trickffc80972013-01-25 06:52:27 +00001187
1188 // Either link or merge the TreeData entry from the child to the parent.
Andrew Trick646eeb62013-01-25 06:52:30 +00001189 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1190 // If the predecessor's parent is invalid, this is a tree edge and the
1191 // current node is the parent.
1192 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1193 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1194 }
1195 else if (RootSet.count(PredNum)) {
1196 // The predecessor is not a root, but is still in the root set. This
1197 // must be the new parent that it was just joined to. Note that
1198 // RootSet[PredNum].ParentNodeID may either be invalid or may still be
1199 // set to the original parent.
Andrew Trickffc80972013-01-25 06:52:27 +00001200 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1201 RootSet.erase(PredNum);
1202 }
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001203 }
Andrew Trickffc80972013-01-25 06:52:27 +00001204 RootSet[SU->NodeNum] = RData;
1205 }
1206
Matthias Braunbd7d9182017-01-27 18:53:00 +00001207 /// \brief Called once for each tree edge after calling visitPostOrderNode on
1208 /// the predecessor. Increment the parent node's instruction count and
Andrew Trickffc80972013-01-25 06:52:27 +00001209 /// preemptively join this subtree to its parent's if it is small enough.
1210 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1211 R.DFSNodeData[Succ->NodeNum].InstrCount
1212 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1213 joinPredSubtree(PredDep, Succ);
Andrew Trick48d392e2012-11-28 05:13:28 +00001214 }
1215
Matthias Braunbd7d9182017-01-27 18:53:00 +00001216 /// Adds a connection for cross edges.
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001217 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
Andrew Trick48d392e2012-11-28 05:13:28 +00001218 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1219 }
1220
Matthias Braunbd7d9182017-01-27 18:53:00 +00001221 /// Sets each node's subtree ID to the representative ID and record
1222 /// connections between trees.
Andrew Trick48d392e2012-11-28 05:13:28 +00001223 void finalize() {
1224 SubtreeClasses.compress();
Andrew Trickffc80972013-01-25 06:52:27 +00001225 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1226 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1227 && "number of roots should match trees");
Matthias Braun298e0072016-09-30 23:08:07 +00001228 for (const RootData &Root : RootSet) {
1229 unsigned TreeID = SubtreeClasses[Root.NodeID];
1230 if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1231 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
1232 R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
Andrew Trick646eeb62013-01-25 06:52:30 +00001233 // Note that SubInstrCount may be greater than InstrCount if we joined
1234 // subtrees across a cross edge. InstrCount will be attributed to the
1235 // original parent, while SubInstrCount will be attributed to the joined
1236 // parent.
Andrew Trickffc80972013-01-25 06:52:27 +00001237 }
Andrew Trick48d392e2012-11-28 05:13:28 +00001238 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1239 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1240 DEBUG(dbgs() << R.getNumSubtrees() << " subtrees:\n");
Andrew Trickffc80972013-01-25 06:52:27 +00001241 for (unsigned Idx = 0, End = R.DFSNodeData.size(); Idx != End; ++Idx) {
1242 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
Andrew Trick48d392e2012-11-28 05:13:28 +00001243 DEBUG(dbgs() << " SU(" << Idx << ") in tree "
Andrew Trickffc80972013-01-25 06:52:27 +00001244 << R.DFSNodeData[Idx].SubtreeID << '\n');
Andrew Trick48d392e2012-11-28 05:13:28 +00001245 }
Matthias Braun298e0072016-09-30 23:08:07 +00001246 for (const std::pair<const SUnit*, const SUnit*> &P : ConnectionPairs) {
1247 unsigned PredTree = SubtreeClasses[P.first->NodeNum];
1248 unsigned SuccTree = SubtreeClasses[P.second->NodeNum];
Andrew Trick48d392e2012-11-28 05:13:28 +00001249 if (PredTree == SuccTree)
1250 continue;
Matthias Braun298e0072016-09-30 23:08:07 +00001251 unsigned Depth = P.first->getDepth();
Andrew Trick48d392e2012-11-28 05:13:28 +00001252 addConnection(PredTree, SuccTree, Depth);
1253 addConnection(SuccTree, PredTree, Depth);
1254 }
1255 }
1256
1257protected:
Matthias Braunbd7d9182017-01-27 18:53:00 +00001258 /// Joins the predecessor subtree with the successor that is its DFS parent.
1259 /// Applies some heuristics before joining.
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001260 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1261 bool CheckLimit = true) {
1262 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
1263
1264 // Check if the predecessor is already joined.
1265 const SUnit *PredSU = PredDep.getSUnit();
1266 unsigned PredNum = PredSU->NodeNum;
Andrew Trickffc80972013-01-25 06:52:27 +00001267 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001268 return false;
Andrew Trickb52a8562013-01-25 00:12:57 +00001269
1270 // Four is the magic number of successors before a node is considered a
1271 // pinch point.
1272 unsigned NumDataSucs = 0;
Matthias Braun298e0072016-09-30 23:08:07 +00001273 for (const SDep &SuccDep : PredSU->Succs) {
1274 if (SuccDep.getKind() == SDep::Data) {
Andrew Trickb52a8562013-01-25 00:12:57 +00001275 if (++NumDataSucs >= 4)
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001276 return false;
Andrew Trickb52a8562013-01-25 00:12:57 +00001277 }
1278 }
Andrew Trickffc80972013-01-25 06:52:27 +00001279 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001280 return false;
Andrew Trickffc80972013-01-25 06:52:27 +00001281 R.DFSNodeData[PredNum].SubtreeID = Succ->NodeNum;
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001282 SubtreeClasses.join(Succ->NodeNum, PredNum);
1283 return true;
Andrew Trickb52a8562013-01-25 00:12:57 +00001284 }
1285
Andrew Trick48d392e2012-11-28 05:13:28 +00001286 /// Called by finalize() to record a connection between trees.
1287 void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth) {
1288 if (!Depth)
1289 return;
1290
Andrew Trickffc80972013-01-25 06:52:27 +00001291 do {
1292 SmallVectorImpl<SchedDFSResult::Connection> &Connections =
1293 R.SubtreeConnections[FromTree];
Matthias Braun298e0072016-09-30 23:08:07 +00001294 for (SchedDFSResult::Connection &C : Connections) {
1295 if (C.TreeID == ToTree) {
1296 C.Level = std::max(C.Level, Depth);
Andrew Trickffc80972013-01-25 06:52:27 +00001297 return;
1298 }
Andrew Trick48d392e2012-11-28 05:13:28 +00001299 }
Andrew Trickffc80972013-01-25 06:52:27 +00001300 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1301 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1302 } while (FromTree != SchedDFSResult::InvalidSubtreeID);
Andrew Trick48d392e2012-11-28 05:13:28 +00001303 }
1304};
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001305
Matthias Braunbd7d9182017-01-27 18:53:00 +00001306} // end namespace llvm
Andrew Trick48d392e2012-11-28 05:13:28 +00001307
Andrew Trick90f711d2012-10-15 18:02:27 +00001308namespace {
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001309
Matthias Braunbd7d9182017-01-27 18:53:00 +00001310/// Manage the stack used by a reverse depth-first search over the DAG.
Andrew Trick90f711d2012-10-15 18:02:27 +00001311class SchedDAGReverseDFS {
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001312 std::vector<std::pair<const SUnit *, SUnit::const_pred_iterator>> DFSStack;
1313
Andrew Trick90f711d2012-10-15 18:02:27 +00001314public:
1315 bool isComplete() const { return DFSStack.empty(); }
1316
1317 void follow(const SUnit *SU) {
1318 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin()));
1319 }
1320 void advance() { ++DFSStack.back().second; }
1321
Andrew Trick48d392e2012-11-28 05:13:28 +00001322 const SDep *backtrack() {
1323 DFSStack.pop_back();
Craig Topperc0196b12014-04-14 00:51:57 +00001324 return DFSStack.empty() ? nullptr : std::prev(DFSStack.back().second);
Andrew Trick48d392e2012-11-28 05:13:28 +00001325 }
Andrew Trick90f711d2012-10-15 18:02:27 +00001326
1327 const SUnit *getCurr() const { return DFSStack.back().first; }
1328
1329 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1330
1331 SUnit::const_pred_iterator getPredEnd() const {
1332 return getCurr()->Preds.end();
1333 }
1334};
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001335
1336} // end anonymous namespace
Andrew Trick90f711d2012-10-15 18:02:27 +00001337
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001338static bool hasDataSucc(const SUnit *SU) {
Matthias Braun298e0072016-09-30 23:08:07 +00001339 for (const SDep &SuccDep : SU->Succs) {
1340 if (SuccDep.getKind() == SDep::Data &&
1341 !SuccDep.getSUnit()->isBoundaryNode())
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001342 return true;
1343 }
1344 return false;
1345}
1346
Matthias Braunbd7d9182017-01-27 18:53:00 +00001347/// Computes an ILP metric for all nodes in the subDAG reachable via depth-first
Andrew Trick90f711d2012-10-15 18:02:27 +00001348/// search from this root.
Andrew Tricke2c3f5c2013-01-25 06:33:57 +00001349void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
Andrew Trick90f711d2012-10-15 18:02:27 +00001350 if (!IsBottomUp)
Eric Christopher52854dc2017-08-03 22:41:12 +00001351 llvm_unreachable("Top-down ILP metric is unimplemented");
Andrew Trick90f711d2012-10-15 18:02:27 +00001352
Andrew Trick48d392e2012-11-28 05:13:28 +00001353 SchedDFSImpl Impl(*this);
Matthias Braun298e0072016-09-30 23:08:07 +00001354 for (const SUnit &SU : SUnits) {
1355 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
Andrew Tricke2c3f5c2013-01-25 06:33:57 +00001356 continue;
1357
Andrew Trick48d392e2012-11-28 05:13:28 +00001358 SchedDAGReverseDFS DFS;
Matthias Braun298e0072016-09-30 23:08:07 +00001359 Impl.visitPreorder(&SU);
1360 DFS.follow(&SU);
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001361 while (true) {
Andrew Trick48d392e2012-11-28 05:13:28 +00001362 // Traverse the leftmost path as far as possible.
1363 while (DFS.getPred() != DFS.getPredEnd()) {
1364 const SDep &PredDep = *DFS.getPred();
1365 DFS.advance();
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001366 // Ignore non-data edges.
Andrew Trick646eeb62013-01-25 06:52:30 +00001367 if (PredDep.getKind() != SDep::Data
1368 || PredDep.getSUnit()->isBoundaryNode()) {
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001369 continue;
Andrew Trick646eeb62013-01-25 06:52:30 +00001370 }
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001371 // An already visited edge is a cross edge, assuming an acyclic DAG.
Andrew Trick48d392e2012-11-28 05:13:28 +00001372 if (Impl.isVisited(PredDep.getSUnit())) {
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001373 Impl.visitCrossEdge(PredDep, DFS.getCurr());
Andrew Trick48d392e2012-11-28 05:13:28 +00001374 continue;
1375 }
1376 Impl.visitPreorder(PredDep.getSUnit());
1377 DFS.follow(PredDep.getSUnit());
1378 }
1379 // Visit the top of the stack in postorder and backtrack.
1380 const SUnit *Child = DFS.getCurr();
1381 const SDep *PredDep = DFS.backtrack();
Andrew Trick5b07eeb2013-01-25 06:02:44 +00001382 Impl.visitPostorderNode(Child);
1383 if (PredDep)
1384 Impl.visitPostorderEdge(*PredDep, DFS.getCurr());
Andrew Trick48d392e2012-11-28 05:13:28 +00001385 if (DFS.isComplete())
1386 break;
Andrew Trick90f711d2012-10-15 18:02:27 +00001387 }
Andrew Trick48d392e2012-11-28 05:13:28 +00001388 }
1389 Impl.finalize();
1390}
1391
1392/// The root of the given SubtreeID was just scheduled. For all subtrees
1393/// connected to this tree, record the depth of the connection so that the
1394/// nearest connected subtrees can be prioritized.
1395void SchedDFSResult::scheduleTree(unsigned SubtreeID) {
Matthias Braun298e0072016-09-30 23:08:07 +00001396 for (const Connection &C : SubtreeConnections[SubtreeID]) {
1397 SubtreeConnectLevels[C.TreeID] =
1398 std::max(SubtreeConnectLevels[C.TreeID], C.Level);
1399 DEBUG(dbgs() << " Tree: " << C.TreeID
1400 << " @" << SubtreeConnectLevels[C.TreeID] << '\n');
Andrew Trick90f711d2012-10-15 18:02:27 +00001401 }
1402}
1403
Matthias Braun8c209aa2017-01-28 02:02:38 +00001404#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1405LLVM_DUMP_METHOD void ILPValue::print(raw_ostream &OS) const {
Andrew Trick48d392e2012-11-28 05:13:28 +00001406 OS << InstrCount << " / " << Length << " = ";
1407 if (!Length)
Andrew Trick90f711d2012-10-15 18:02:27 +00001408 OS << "BADILP";
Andrew Trick48d392e2012-11-28 05:13:28 +00001409 else
1410 OS << format("%g", ((double)InstrCount / Length));
Andrew Trick90f711d2012-10-15 18:02:27 +00001411}
1412
Matthias Braun8c209aa2017-01-28 02:02:38 +00001413LLVM_DUMP_METHOD void ILPValue::dump() const {
Andrew Trick90f711d2012-10-15 18:02:27 +00001414 dbgs() << *this << '\n';
1415}
1416
1417namespace llvm {
1418
Alp Tokerd8d510a2014-07-01 21:19:13 +00001419LLVM_DUMP_METHOD
Andrew Trick90f711d2012-10-15 18:02:27 +00001420raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) {
1421 Val.print(OS);
1422 return OS;
1423}
1424
Matthias Braunbd7d9182017-01-27 18:53:00 +00001425} // end namespace llvm
Eugene Zelenko7ea69232017-06-01 23:25:02 +00001426
Matthias Braun8c209aa2017-01-28 02:02:38 +00001427#endif