Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / dd69ef38dba72b08bee83f262fd443743940d2bc / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: f7686506c231672aeb9ca1a2ab90c6eaa6a63b76 [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
41/// InitLibcallNames - Set default libcall names.
42///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]43static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]44 Names[RTLIB::SHL_I16] = "__ashlhi3";
45 Names[RTLIB::SHL_I32] = "__ashlsi3";
46 Names[RTLIB::SHL_I64] = "__ashldi3";
47 Names[RTLIB::SHL_I128] = "__ashlti3";
48 Names[RTLIB::SRL_I16] = "__lshrhi3";
49 Names[RTLIB::SRL_I32] = "__lshrsi3";
50 Names[RTLIB::SRL_I64] = "__lshrdi3";
51 Names[RTLIB::SRL_I128] = "__lshrti3";
52 Names[RTLIB::SRA_I16] = "__ashrhi3";
53 Names[RTLIB::SRA_I32] = "__ashrsi3";
54 Names[RTLIB::SRA_I64] = "__ashrdi3";
55 Names[RTLIB::SRA_I128] = "__ashrti3";
56 Names[RTLIB::MUL_I8] = "__mulqi3";
57 Names[RTLIB::MUL_I16] = "__mulhi3";
58 Names[RTLIB::MUL_I32] = "__mulsi3";
59 Names[RTLIB::MUL_I64] = "__muldi3";
60 Names[RTLIB::MUL_I128] = "__multi3";
61 Names[RTLIB::MULO_I32] = "__mulosi4";
62 Names[RTLIB::MULO_I64] = "__mulodi4";
63 Names[RTLIB::MULO_I128] = "__muloti4";
64 Names[RTLIB::SDIV_I8] = "__divqi3";
65 Names[RTLIB::SDIV_I16] = "__divhi3";
66 Names[RTLIB::SDIV_I32] = "__divsi3";
67 Names[RTLIB::SDIV_I64] = "__divdi3";
68 Names[RTLIB::SDIV_I128] = "__divti3";
69 Names[RTLIB::UDIV_I8] = "__udivqi3";
70 Names[RTLIB::UDIV_I16] = "__udivhi3";
71 Names[RTLIB::UDIV_I32] = "__udivsi3";
72 Names[RTLIB::UDIV_I64] = "__udivdi3";
73 Names[RTLIB::UDIV_I128] = "__udivti3";
74 Names[RTLIB::SREM_I8] = "__modqi3";
75 Names[RTLIB::SREM_I16] = "__modhi3";
76 Names[RTLIB::SREM_I32] = "__modsi3";
77 Names[RTLIB::SREM_I64] = "__moddi3";
78 Names[RTLIB::SREM_I128] = "__modti3";
79 Names[RTLIB::UREM_I8] = "__umodqi3";
80 Names[RTLIB::UREM_I16] = "__umodhi3";
81 Names[RTLIB::UREM_I32] = "__umodsi3";
82 Names[RTLIB::UREM_I64] = "__umoddi3";
83 Names[RTLIB::UREM_I128] = "__umodti3";
84
85 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]86 Names[RTLIB::SDIVREM_I8] = nullptr;
87 Names[RTLIB::SDIVREM_I16] = nullptr;
88 Names[RTLIB::SDIVREM_I32] = nullptr;
89 Names[RTLIB::SDIVREM_I64] = nullptr;
90 Names[RTLIB::SDIVREM_I128] = nullptr;
91 Names[RTLIB::UDIVREM_I8] = nullptr;
92 Names[RTLIB::UDIVREM_I16] = nullptr;
93 Names[RTLIB::UDIVREM_I32] = nullptr;
94 Names[RTLIB::UDIVREM_I64] = nullptr;
95 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]96
97 Names[RTLIB::NEG_I32] = "__negsi2";
98 Names[RTLIB::NEG_I64] = "__negdi2";
99 Names[RTLIB::ADD_F32] = "__addsf3";
100 Names[RTLIB::ADD_F64] = "__adddf3";
101 Names[RTLIB::ADD_F80] = "__addxf3";
102 Names[RTLIB::ADD_F128] = "__addtf3";
103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
104 Names[RTLIB::SUB_F32] = "__subsf3";
105 Names[RTLIB::SUB_F64] = "__subdf3";
106 Names[RTLIB::SUB_F80] = "__subxf3";
107 Names[RTLIB::SUB_F128] = "__subtf3";
108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
109 Names[RTLIB::MUL_F32] = "__mulsf3";
110 Names[RTLIB::MUL_F64] = "__muldf3";
111 Names[RTLIB::MUL_F80] = "__mulxf3";
112 Names[RTLIB::MUL_F128] = "__multf3";
113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
114 Names[RTLIB::DIV_F32] = "__divsf3";
115 Names[RTLIB::DIV_F64] = "__divdf3";
116 Names[RTLIB::DIV_F80] = "__divxf3";
117 Names[RTLIB::DIV_F128] = "__divtf3";
118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
119 Names[RTLIB::REM_F32] = "fmodf";
120 Names[RTLIB::REM_F64] = "fmod";
121 Names[RTLIB::REM_F80] = "fmodl";
122 Names[RTLIB::REM_F128] = "fmodl";
123 Names[RTLIB::REM_PPCF128] = "fmodl";
124 Names[RTLIB::FMA_F32] = "fmaf";
125 Names[RTLIB::FMA_F64] = "fma";
126 Names[RTLIB::FMA_F80] = "fmal";
127 Names[RTLIB::FMA_F128] = "fmal";
128 Names[RTLIB::FMA_PPCF128] = "fmal";
129 Names[RTLIB::POWI_F32] = "__powisf2";
130 Names[RTLIB::POWI_F64] = "__powidf2";
131 Names[RTLIB::POWI_F80] = "__powixf2";
132 Names[RTLIB::POWI_F128] = "__powitf2";
133 Names[RTLIB::POWI_PPCF128] = "__powitf2";
134 Names[RTLIB::SQRT_F32] = "sqrtf";
135 Names[RTLIB::SQRT_F64] = "sqrt";
136 Names[RTLIB::SQRT_F80] = "sqrtl";
137 Names[RTLIB::SQRT_F128] = "sqrtl";
138 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
139 Names[RTLIB::LOG_F32] = "logf";
140 Names[RTLIB::LOG_F64] = "log";
141 Names[RTLIB::LOG_F80] = "logl";
142 Names[RTLIB::LOG_F128] = "logl";
143 Names[RTLIB::LOG_PPCF128] = "logl";
144 Names[RTLIB::LOG2_F32] = "log2f";
145 Names[RTLIB::LOG2_F64] = "log2";
146 Names[RTLIB::LOG2_F80] = "log2l";
147 Names[RTLIB::LOG2_F128] = "log2l";
148 Names[RTLIB::LOG2_PPCF128] = "log2l";
149 Names[RTLIB::LOG10_F32] = "log10f";
150 Names[RTLIB::LOG10_F64] = "log10";
151 Names[RTLIB::LOG10_F80] = "log10l";
152 Names[RTLIB::LOG10_F128] = "log10l";
153 Names[RTLIB::LOG10_PPCF128] = "log10l";
154 Names[RTLIB::EXP_F32] = "expf";
155 Names[RTLIB::EXP_F64] = "exp";
156 Names[RTLIB::EXP_F80] = "expl";
157 Names[RTLIB::EXP_F128] = "expl";
158 Names[RTLIB::EXP_PPCF128] = "expl";
159 Names[RTLIB::EXP2_F32] = "exp2f";
160 Names[RTLIB::EXP2_F64] = "exp2";
161 Names[RTLIB::EXP2_F80] = "exp2l";
162 Names[RTLIB::EXP2_F128] = "exp2l";
163 Names[RTLIB::EXP2_PPCF128] = "exp2l";
164 Names[RTLIB::SIN_F32] = "sinf";
165 Names[RTLIB::SIN_F64] = "sin";
166 Names[RTLIB::SIN_F80] = "sinl";
167 Names[RTLIB::SIN_F128] = "sinl";
168 Names[RTLIB::SIN_PPCF128] = "sinl";
169 Names[RTLIB::COS_F32] = "cosf";
170 Names[RTLIB::COS_F64] = "cos";
171 Names[RTLIB::COS_F80] = "cosl";
172 Names[RTLIB::COS_F128] = "cosl";
173 Names[RTLIB::COS_PPCF128] = "cosl";
174 Names[RTLIB::POW_F32] = "powf";
175 Names[RTLIB::POW_F64] = "pow";
176 Names[RTLIB::POW_F80] = "powl";
177 Names[RTLIB::POW_F128] = "powl";
178 Names[RTLIB::POW_PPCF128] = "powl";
179 Names[RTLIB::CEIL_F32] = "ceilf";
180 Names[RTLIB::CEIL_F64] = "ceil";
181 Names[RTLIB::CEIL_F80] = "ceill";
182 Names[RTLIB::CEIL_F128] = "ceill";
183 Names[RTLIB::CEIL_PPCF128] = "ceill";
184 Names[RTLIB::TRUNC_F32] = "truncf";
185 Names[RTLIB::TRUNC_F64] = "trunc";
186 Names[RTLIB::TRUNC_F80] = "truncl";
187 Names[RTLIB::TRUNC_F128] = "truncl";
188 Names[RTLIB::TRUNC_PPCF128] = "truncl";
189 Names[RTLIB::RINT_F32] = "rintf";
190 Names[RTLIB::RINT_F64] = "rint";
191 Names[RTLIB::RINT_F80] = "rintl";
192 Names[RTLIB::RINT_F128] = "rintl";
193 Names[RTLIB::RINT_PPCF128] = "rintl";
194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
195 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]199 Names[RTLIB::ROUND_F32] = "roundf";
200 Names[RTLIB::ROUND_F64] = "round";
201 Names[RTLIB::ROUND_F80] = "roundl";
202 Names[RTLIB::ROUND_F128] = "roundl";
203 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]204 Names[RTLIB::FLOOR_F32] = "floorf";
205 Names[RTLIB::FLOOR_F64] = "floor";
206 Names[RTLIB::FLOOR_F80] = "floorl";
207 Names[RTLIB::FLOOR_F128] = "floorl";
208 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]209 Names[RTLIB::ROUND_F32] = "roundf";
210 Names[RTLIB::ROUND_F64] = "round";
211 Names[RTLIB::ROUND_F80] = "roundl";
212 Names[RTLIB::ROUND_F128] = "roundl";
213 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]214 Names[RTLIB::COPYSIGN_F32] = "copysignf";
215 Names[RTLIB::COPYSIGN_F64] = "copysign";
216 Names[RTLIB::COPYSIGN_F80] = "copysignl";
217 Names[RTLIB::COPYSIGN_F128] = "copysignl";
218 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
219 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
220 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
221 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
222 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
223 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]224 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
225 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
226 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
227 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]228 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
229 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
230 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
231 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
232 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
233 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
234 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
235 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
236 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
237 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
238 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
239 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
240 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
241 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
242 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
243 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
244 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
245 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
246 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
247 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
248 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
249 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
250 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
251 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
252 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
253 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
254 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
255 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
256 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
257 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
258 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
259 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
260 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
261 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
262 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
263 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
264 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
265 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
266 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
267 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
268 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
269 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
270 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
271 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
272 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
273 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
274 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
275 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
276 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
277 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
278 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
279 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
280 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
281 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
282 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
283 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
284 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
285 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
286 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
287 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
288 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
289 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
290 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
291 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
292 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
293 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
294 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
295 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
296 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
297 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
298 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
299 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
300 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
301 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
302 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
303 Names[RTLIB::OEQ_F32] = "__eqsf2";
304 Names[RTLIB::OEQ_F64] = "__eqdf2";
305 Names[RTLIB::OEQ_F128] = "__eqtf2";
306 Names[RTLIB::UNE_F32] = "__nesf2";
307 Names[RTLIB::UNE_F64] = "__nedf2";
308 Names[RTLIB::UNE_F128] = "__netf2";
309 Names[RTLIB::OGE_F32] = "__gesf2";
310 Names[RTLIB::OGE_F64] = "__gedf2";
311 Names[RTLIB::OGE_F128] = "__getf2";
312 Names[RTLIB::OLT_F32] = "__ltsf2";
313 Names[RTLIB::OLT_F64] = "__ltdf2";
314 Names[RTLIB::OLT_F128] = "__lttf2";
315 Names[RTLIB::OLE_F32] = "__lesf2";
316 Names[RTLIB::OLE_F64] = "__ledf2";
317 Names[RTLIB::OLE_F128] = "__letf2";
318 Names[RTLIB::OGT_F32] = "__gtsf2";
319 Names[RTLIB::OGT_F64] = "__gtdf2";
320 Names[RTLIB::OGT_F128] = "__gttf2";
321 Names[RTLIB::UO_F32] = "__unordsf2";
322 Names[RTLIB::UO_F64] = "__unorddf2";
323 Names[RTLIB::UO_F128] = "__unordtf2";
324 Names[RTLIB::O_F32] = "__unordsf2";
325 Names[RTLIB::O_F64] = "__unorddf2";
326 Names[RTLIB::O_F128] = "__unordtf2";
327 Names[RTLIB::MEMCPY] = "memcpy";
328 Names[RTLIB::MEMMOVE] = "memmove";
329 Names[RTLIB::MEMSET] = "memset";
330 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
331 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
332 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
333 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
334 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]335 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]336 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
337 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
338 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
339 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]340 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]341 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
342 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
343 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
344 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]345 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
347 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
348 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
349 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]350 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]351 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
352 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
353 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
354 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]355 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]356 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
357 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
358 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
359 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
362 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
363 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
364 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
367 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
368 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
369 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]371 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
372 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
373 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
374 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
375 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
376 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
377 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
378 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
379 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
380 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
381 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
382 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
383 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
384 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
385 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
386 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
387 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
388 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
389 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
390 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]391
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]392 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]393 Names[RTLIB::SINCOS_F32] = "sincosf";
394 Names[RTLIB::SINCOS_F64] = "sincos";
395 Names[RTLIB::SINCOS_F80] = "sincosl";
396 Names[RTLIB::SINCOS_F128] = "sincosl";
397 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
398 } else {
399 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]400 Names[RTLIB::SINCOS_F32] = nullptr;
401 Names[RTLIB::SINCOS_F64] = nullptr;
402 Names[RTLIB::SINCOS_F80] = nullptr;
403 Names[RTLIB::SINCOS_F128] = nullptr;
404 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]405 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]406
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]407 if (TT.getOS() != Triple::OpenBSD) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]408 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
409 } else {
410 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]411 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]412 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]413}
414
415/// InitLibcallCallingConvs - Set default libcall CallingConvs.
416///
417static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
418 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
419 CCs[i] = CallingConv::C;
420 }
421}
422
423/// getFPEXT - Return the FPEXT_*_* value for the given types, or
424/// UNKNOWN_LIBCALL if there is none.
425RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]426 if (OpVT == MVT::f16) {
427 if (RetVT == MVT::f32)
428 return FPEXT_F16_F32;
429 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]430 if (RetVT == MVT::f64)
431 return FPEXT_F32_F64;
432 if (RetVT == MVT::f128)
433 return FPEXT_F32_F128;
434 } else if (OpVT == MVT::f64) {
435 if (RetVT == MVT::f128)
436 return FPEXT_F64_F128;
437 }
438
439 return UNKNOWN_LIBCALL;
440}
441
442/// getFPROUND - Return the FPROUND_*_* value for the given types, or
443/// UNKNOWN_LIBCALL if there is none.
444RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]445 if (RetVT == MVT::f16) {
446 if (OpVT == MVT::f32)
447 return FPROUND_F32_F16;
448 if (OpVT == MVT::f64)
449 return FPROUND_F64_F16;
450 if (OpVT == MVT::f80)
451 return FPROUND_F80_F16;
452 if (OpVT == MVT::f128)
453 return FPROUND_F128_F16;
454 if (OpVT == MVT::ppcf128)
455 return FPROUND_PPCF128_F16;
456 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]457 if (OpVT == MVT::f64)
458 return FPROUND_F64_F32;
459 if (OpVT == MVT::f80)
460 return FPROUND_F80_F32;
461 if (OpVT == MVT::f128)
462 return FPROUND_F128_F32;
463 if (OpVT == MVT::ppcf128)
464 return FPROUND_PPCF128_F32;
465 } else if (RetVT == MVT::f64) {
466 if (OpVT == MVT::f80)
467 return FPROUND_F80_F64;
468 if (OpVT == MVT::f128)
469 return FPROUND_F128_F64;
470 if (OpVT == MVT::ppcf128)
471 return FPROUND_PPCF128_F64;
472 }
473
474 return UNKNOWN_LIBCALL;
475}
476
477/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
478/// UNKNOWN_LIBCALL if there is none.
479RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
480 if (OpVT == MVT::f32) {
481 if (RetVT == MVT::i8)
482 return FPTOSINT_F32_I8;
483 if (RetVT == MVT::i16)
484 return FPTOSINT_F32_I16;
485 if (RetVT == MVT::i32)
486 return FPTOSINT_F32_I32;
487 if (RetVT == MVT::i64)
488 return FPTOSINT_F32_I64;
489 if (RetVT == MVT::i128)
490 return FPTOSINT_F32_I128;
491 } else if (OpVT == MVT::f64) {
492 if (RetVT == MVT::i8)
493 return FPTOSINT_F64_I8;
494 if (RetVT == MVT::i16)
495 return FPTOSINT_F64_I16;
496 if (RetVT == MVT::i32)
497 return FPTOSINT_F64_I32;
498 if (RetVT == MVT::i64)
499 return FPTOSINT_F64_I64;
500 if (RetVT == MVT::i128)
501 return FPTOSINT_F64_I128;
502 } else if (OpVT == MVT::f80) {
503 if (RetVT == MVT::i32)
504 return FPTOSINT_F80_I32;
505 if (RetVT == MVT::i64)
506 return FPTOSINT_F80_I64;
507 if (RetVT == MVT::i128)
508 return FPTOSINT_F80_I128;
509 } else if (OpVT == MVT::f128) {
510 if (RetVT == MVT::i32)
511 return FPTOSINT_F128_I32;
512 if (RetVT == MVT::i64)
513 return FPTOSINT_F128_I64;
514 if (RetVT == MVT::i128)
515 return FPTOSINT_F128_I128;
516 } else if (OpVT == MVT::ppcf128) {
517 if (RetVT == MVT::i32)
518 return FPTOSINT_PPCF128_I32;
519 if (RetVT == MVT::i64)
520 return FPTOSINT_PPCF128_I64;
521 if (RetVT == MVT::i128)
522 return FPTOSINT_PPCF128_I128;
523 }
524 return UNKNOWN_LIBCALL;
525}
526
527/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
528/// UNKNOWN_LIBCALL if there is none.
529RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
530 if (OpVT == MVT::f32) {
531 if (RetVT == MVT::i8)
532 return FPTOUINT_F32_I8;
533 if (RetVT == MVT::i16)
534 return FPTOUINT_F32_I16;
535 if (RetVT == MVT::i32)
536 return FPTOUINT_F32_I32;
537 if (RetVT == MVT::i64)
538 return FPTOUINT_F32_I64;
539 if (RetVT == MVT::i128)
540 return FPTOUINT_F32_I128;
541 } else if (OpVT == MVT::f64) {
542 if (RetVT == MVT::i8)
543 return FPTOUINT_F64_I8;
544 if (RetVT == MVT::i16)
545 return FPTOUINT_F64_I16;
546 if (RetVT == MVT::i32)
547 return FPTOUINT_F64_I32;
548 if (RetVT == MVT::i64)
549 return FPTOUINT_F64_I64;
550 if (RetVT == MVT::i128)
551 return FPTOUINT_F64_I128;
552 } else if (OpVT == MVT::f80) {
553 if (RetVT == MVT::i32)
554 return FPTOUINT_F80_I32;
555 if (RetVT == MVT::i64)
556 return FPTOUINT_F80_I64;
557 if (RetVT == MVT::i128)
558 return FPTOUINT_F80_I128;
559 } else if (OpVT == MVT::f128) {
560 if (RetVT == MVT::i32)
561 return FPTOUINT_F128_I32;
562 if (RetVT == MVT::i64)
563 return FPTOUINT_F128_I64;
564 if (RetVT == MVT::i128)
565 return FPTOUINT_F128_I128;
566 } else if (OpVT == MVT::ppcf128) {
567 if (RetVT == MVT::i32)
568 return FPTOUINT_PPCF128_I32;
569 if (RetVT == MVT::i64)
570 return FPTOUINT_PPCF128_I64;
571 if (RetVT == MVT::i128)
572 return FPTOUINT_PPCF128_I128;
573 }
574 return UNKNOWN_LIBCALL;
575}
576
577/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
578/// UNKNOWN_LIBCALL if there is none.
579RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
580 if (OpVT == MVT::i32) {
581 if (RetVT == MVT::f32)
582 return SINTTOFP_I32_F32;
583 if (RetVT == MVT::f64)
584 return SINTTOFP_I32_F64;
585 if (RetVT == MVT::f80)
586 return SINTTOFP_I32_F80;
587 if (RetVT == MVT::f128)
588 return SINTTOFP_I32_F128;
589 if (RetVT == MVT::ppcf128)
590 return SINTTOFP_I32_PPCF128;
591 } else if (OpVT == MVT::i64) {
592 if (RetVT == MVT::f32)
593 return SINTTOFP_I64_F32;
594 if (RetVT == MVT::f64)
595 return SINTTOFP_I64_F64;
596 if (RetVT == MVT::f80)
597 return SINTTOFP_I64_F80;
598 if (RetVT == MVT::f128)
599 return SINTTOFP_I64_F128;
600 if (RetVT == MVT::ppcf128)
601 return SINTTOFP_I64_PPCF128;
602 } else if (OpVT == MVT::i128) {
603 if (RetVT == MVT::f32)
604 return SINTTOFP_I128_F32;
605 if (RetVT == MVT::f64)
606 return SINTTOFP_I128_F64;
607 if (RetVT == MVT::f80)
608 return SINTTOFP_I128_F80;
609 if (RetVT == MVT::f128)
610 return SINTTOFP_I128_F128;
611 if (RetVT == MVT::ppcf128)
612 return SINTTOFP_I128_PPCF128;
613 }
614 return UNKNOWN_LIBCALL;
615}
616
617/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
618/// UNKNOWN_LIBCALL if there is none.
619RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
620 if (OpVT == MVT::i32) {
621 if (RetVT == MVT::f32)
622 return UINTTOFP_I32_F32;
623 if (RetVT == MVT::f64)
624 return UINTTOFP_I32_F64;
625 if (RetVT == MVT::f80)
626 return UINTTOFP_I32_F80;
627 if (RetVT == MVT::f128)
628 return UINTTOFP_I32_F128;
629 if (RetVT == MVT::ppcf128)
630 return UINTTOFP_I32_PPCF128;
631 } else if (OpVT == MVT::i64) {
632 if (RetVT == MVT::f32)
633 return UINTTOFP_I64_F32;
634 if (RetVT == MVT::f64)
635 return UINTTOFP_I64_F64;
636 if (RetVT == MVT::f80)
637 return UINTTOFP_I64_F80;
638 if (RetVT == MVT::f128)
639 return UINTTOFP_I64_F128;
640 if (RetVT == MVT::ppcf128)
641 return UINTTOFP_I64_PPCF128;
642 } else if (OpVT == MVT::i128) {
643 if (RetVT == MVT::f32)
644 return UINTTOFP_I128_F32;
645 if (RetVT == MVT::f64)
646 return UINTTOFP_I128_F64;
647 if (RetVT == MVT::f80)
648 return UINTTOFP_I128_F80;
649 if (RetVT == MVT::f128)
650 return UINTTOFP_I128_F128;
651 if (RetVT == MVT::ppcf128)
652 return UINTTOFP_I128_PPCF128;
653 }
654 return UNKNOWN_LIBCALL;
655}
656
657/// InitCmpLibcallCCs - Set default comparison libcall CC.
658///
659static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
660 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
661 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
662 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
663 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
664 CCs[RTLIB::UNE_F32] = ISD::SETNE;
665 CCs[RTLIB::UNE_F64] = ISD::SETNE;
666 CCs[RTLIB::UNE_F128] = ISD::SETNE;
667 CCs[RTLIB::OGE_F32] = ISD::SETGE;
668 CCs[RTLIB::OGE_F64] = ISD::SETGE;
669 CCs[RTLIB::OGE_F128] = ISD::SETGE;
670 CCs[RTLIB::OLT_F32] = ISD::SETLT;
671 CCs[RTLIB::OLT_F64] = ISD::SETLT;
672 CCs[RTLIB::OLT_F128] = ISD::SETLT;
673 CCs[RTLIB::OLE_F32] = ISD::SETLE;
674 CCs[RTLIB::OLE_F64] = ISD::SETLE;
675 CCs[RTLIB::OLE_F128] = ISD::SETLE;
676 CCs[RTLIB::OGT_F32] = ISD::SETGT;
677 CCs[RTLIB::OGT_F64] = ISD::SETGT;
678 CCs[RTLIB::OGT_F128] = ISD::SETGT;
679 CCs[RTLIB::UO_F32] = ISD::SETNE;
680 CCs[RTLIB::UO_F64] = ISD::SETNE;
681 CCs[RTLIB::UO_F128] = ISD::SETNE;
682 CCs[RTLIB::O_F32] = ISD::SETEQ;
683 CCs[RTLIB::O_F64] = ISD::SETEQ;
684 CCs[RTLIB::O_F128] = ISD::SETEQ;
685}
686
687/// NOTE: The constructor takes ownership of TLOF.
688TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
689 const TargetLoweringObjectFile *tlof)
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]690 : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()), TLOF(*tlof) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]691 initActions();
692
693 // Perform these initializations only once.
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]694 IsLittleEndian = DL->isLittleEndian();
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]695 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
696 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
697 = MaxStoresPerMemmoveOptSize = 4;
698 UseUnderscoreSetJmp = false;
699 UseUnderscoreLongJmp = false;
700 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]701 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]702 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]703 IntDivIsCheap = false;
704 Pow2DivIsCheap = false;
705 JumpIsExpensive = false;
706 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]707 MaskAndBranchFoldingIsLegal = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]708 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]709 StackPointerRegisterToSaveRestore = 0;
710 ExceptionPointerRegister = 0;
711 ExceptionSelectorRegister = 0;
712 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]713 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]714 BooleanVectorContents = UndefinedBooleanContent;
715 SchedPreferenceInfo = Sched::ILP;
716 JumpBufSize = 0;
717 JumpBufAlignment = 0;
718 MinFunctionAlignment = 0;
719 PrefFunctionAlignment = 0;
720 PrefLoopAlignment = 0;
721 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]722 InsertFencesForAtomic = false;
Eric Christopherb9fd9ed2014-08-07 22:02:54 +0000[diff] [blame]723 SupportJumpTables = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]724 MinimumJumpTableEntries = 4;
725
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]726 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]727 InitCmpLibcallCCs(CmpLibcallCCs);
728 InitLibcallCallingConvs(LibcallCallingConvs);
729}
730
731TargetLoweringBase::~TargetLoweringBase() {
732 delete &TLOF;
733}
734
735void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]736 // All operations default to being supported.
737 memset(OpActions, 0, sizeof(OpActions));
738 memset(LoadExtActions, 0, sizeof(LoadExtActions));
739 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
740 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
741 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]742 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
743 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]744
745 // Set default actions for various operations.
746 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
747 // Default all indexed load / store to expand.
748 for (unsigned IM = (unsigned)ISD::PRE_INC;
749 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
750 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
751 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
752 }
753
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]754 // Most backends expect to see the node which just returns the value loaded.
755 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
756 (MVT::SimpleValueType)VT, Expand);
757
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]758 // These operations default to expand.
759 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]761
762 // These library functions default to expand.
763 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]764
765 // These operations default to expand for vector types.
766 if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]767 VT <= MVT::LAST_VECTOR_VALUETYPE) {
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]768 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
Chandler Carruth0b666e02014-07-10 12:32:32 +0000[diff] [blame]769 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,
770 (MVT::SimpleValueType)VT, Expand);
771 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG,
772 (MVT::SimpleValueType)VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]773 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG,
774 (MVT::SimpleValueType)VT, Expand);
775 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]776 }
777
778 // Most targets ignore the @llvm.prefetch intrinsic.
779 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
780
781 // ConstantFP nodes default to expand. Targets can either change this to
782 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
783 // to optimize expansions for certain constants.
784 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
785 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
786 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
787 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
788 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
789
790 // These library functions default to expand.
791 setOperationAction(ISD::FLOG , MVT::f16, Expand);
792 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
793 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
794 setOperationAction(ISD::FEXP , MVT::f16, Expand);
795 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
798 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
799 setOperationAction(ISD::FRINT, MVT::f16, Expand);
800 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]801 setOperationAction(ISD::FROUND, MVT::f16, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]802 setOperationAction(ISD::FLOG , MVT::f32, Expand);
803 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
804 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
805 setOperationAction(ISD::FEXP , MVT::f32, Expand);
806 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
807 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
808 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
809 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
810 setOperationAction(ISD::FRINT, MVT::f32, Expand);
811 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]812 setOperationAction(ISD::FROUND, MVT::f32, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]813 setOperationAction(ISD::FLOG , MVT::f64, Expand);
814 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
815 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
816 setOperationAction(ISD::FEXP , MVT::f64, Expand);
817 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
818 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
819 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
820 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
821 setOperationAction(ISD::FRINT, MVT::f64, Expand);
822 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]823 setOperationAction(ISD::FROUND, MVT::f64, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]824 setOperationAction(ISD::FLOG , MVT::f128, Expand);
825 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
826 setOperationAction(ISD::FLOG10, MVT::f128, Expand);
827 setOperationAction(ISD::FEXP , MVT::f128, Expand);
828 setOperationAction(ISD::FEXP2, MVT::f128, Expand);
829 setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
830 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
831 setOperationAction(ISD::FCEIL, MVT::f128, Expand);
832 setOperationAction(ISD::FRINT, MVT::f128, Expand);
833 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]834 setOperationAction(ISD::FROUND, MVT::f128, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]835
836 // Default ISD::TRAP to expand (which turns it into abort).
837 setOperationAction(ISD::TRAP, MVT::Other, Expand);
838
839 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
840 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
841 //
842 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]843}
844
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]845MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
846 return MVT::getIntegerVT(getPointerSizeInBits(AS));
847}
848
849unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]850 return DL->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]851}
852
853unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
854 assert(Ty->isPointerTy());
855 return getPointerSizeInBits(Ty->getPointerAddressSpace());
856}
857
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]858MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]859 return MVT::getIntegerVT(8*DL->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]860}
861
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]862EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
863 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
864 if (LHSTy.isVector())
865 return LHSTy;
866 return getScalarShiftAmountTy(LHSTy);
867}
868
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]869/// canOpTrap - Returns true if the operation can trap for the value type.
870/// VT must be a legal type.
871bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
872 assert(isTypeLegal(VT));
873 switch (Op) {
874 default:
875 return false;
876 case ISD::FDIV:
877 case ISD::FREM:
878 case ISD::SDIV:
879 case ISD::UDIV:
880 case ISD::SREM:
881 case ISD::UREM:
882 return true;
883 }
884}
885
886
887static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
888 unsigned &NumIntermediates,
889 MVT &RegisterVT,
890 TargetLoweringBase *TLI) {
891 // Figure out the right, legal destination reg to copy into.
892 unsigned NumElts = VT.getVectorNumElements();
893 MVT EltTy = VT.getVectorElementType();
894
895 unsigned NumVectorRegs = 1;
896
897 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
898 // could break down into LHS/RHS like LegalizeDAG does.
899 if (!isPowerOf2_32(NumElts)) {
900 NumVectorRegs = NumElts;
901 NumElts = 1;
902 }
903
904 // Divide the input until we get to a supported size. This will always
905 // end with a scalar if the target doesn't support vectors.
906 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
907 NumElts >>= 1;
908 NumVectorRegs <<= 1;
909 }
910
911 NumIntermediates = NumVectorRegs;
912
913 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
914 if (!TLI->isTypeLegal(NewVT))
915 NewVT = EltTy;
916 IntermediateVT = NewVT;
917
918 unsigned NewVTSize = NewVT.getSizeInBits();
919
920 // Convert sizes such as i33 to i64.
921 if (!isPowerOf2_32(NewVTSize))
922 NewVTSize = NextPowerOf2(NewVTSize);
923
924 MVT DestVT = TLI->getRegisterType(NewVT);
925 RegisterVT = DestVT;
926 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
927 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
928
929 // Otherwise, promotion or legal types use the same number of registers as
930 // the vector decimated to the appropriate level.
931 return NumVectorRegs;
932}
933
934/// isLegalRC - Return true if the value types that can be represented by the
935/// specified register class are all legal.
936bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
937 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
938 I != E; ++I) {
939 if (isTypeLegal(*I))
940 return true;
941 }
942 return false;
943}
944
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]945/// Replace/modify any TargetFrameIndex operands with a targte-dependent
946/// sequence of memory operands that is recognized by PrologEpilogInserter.
947MachineBasicBlock*
948TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
949 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]950 MachineFunction &MF = *MI->getParent()->getParent();
951
952 // MI changes inside this loop as we grow operands.
953 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
954 MachineOperand &MO = MI->getOperand(OperIdx);
955 if (!MO.isFI())
956 continue;
957
958 // foldMemoryOperand builds a new MI after replacing a single FI operand
959 // with the canonical set of five x86 addressing-mode operands.
960 int FI = MO.getIndex();
961 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
962
963 // Copy operands before the frame-index.
964 for (unsigned i = 0; i < OperIdx; ++i)
965 MIB.addOperand(MI->getOperand(i));
966 // Add frame index operands: direct-mem-ref tag, #FI, offset.
967 MIB.addImm(StackMaps::DirectMemRefOp);
968 MIB.addOperand(MI->getOperand(OperIdx));
969 MIB.addImm(0);
970 // Copy the operands after the frame index.
971 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
972 MIB.addOperand(MI->getOperand(i));
973
974 // Inherit previous memory operands.
975 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
976 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
977
978 // Add a new memory operand for this FI.
979 const MachineFrameInfo &MFI = *MF.getFrameInfo();
980 assert(MFI.getObjectOffset(FI) != -1);
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]981 MachineMemOperand *MMO = MF.getMachineMemOperand(
982 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
983 TM.getSubtargetImpl()->getDataLayout()->getPointerSize(),
984 MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]985 MIB->addMemOperand(MF, MMO);
986
987 // Replace the instruction and update the operand index.
988 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
989 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
990 MI->eraseFromParent();
991 MI = MIB;
992 }
993 return MBB;
994}
995
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]996/// findRepresentativeClass - Return the largest legal super-reg register class
997/// of the register class for the specified type and its associated "cost".
998std::pair<const TargetRegisterClass*, uint8_t>
999TargetLoweringBase::findRepresentativeClass(MVT VT) const {
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1000 const TargetRegisterInfo *TRI =
1001 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1002 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1003 if (!RC)
1004 return std::make_pair(RC, 0);
1005
1006 // Compute the set of all super-register classes.
1007 BitVector SuperRegRC(TRI->getNumRegClasses());
1008 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1009 SuperRegRC.setBitsInMask(RCI.getMask());
1010
1011 // Find the first legal register class with the largest spill size.
1012 const TargetRegisterClass *BestRC = RC;
1013 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1014 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1015 // We want the largest possible spill size.
1016 if (SuperRC->getSize() <= BestRC->getSize())
1017 continue;
1018 if (!isLegalRC(SuperRC))
1019 continue;
1020 BestRC = SuperRC;
1021 }
1022 return std::make_pair(BestRC, 1);
1023}
1024
1025/// computeRegisterProperties - Once all of the register classes are added,
1026/// this allows us to compute derived properties we expose.
1027void TargetLoweringBase::computeRegisterProperties() {
1028 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1029 "Too many value types for ValueTypeActions to hold!");
1030
1031 // Everything defaults to needing one register.
1032 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1033 NumRegistersForVT[i] = 1;
1034 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1035 }
1036 // ...except isVoid, which doesn't need any registers.
1037 NumRegistersForVT[MVT::isVoid] = 0;
1038
1039 // Find the largest integer register class.
1040 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1041 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1042 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1043
1044 // Every integer value type larger than this largest register takes twice as
1045 // many registers to represent as the previous ValueType.
1046 for (unsigned ExpandedReg = LargestIntReg + 1;
1047 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1048 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1049 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1050 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1051 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1052 TypeExpandInteger);
1053 }
1054
1055 // Inspect all of the ValueType's smaller than the largest integer
1056 // register to see which ones need promotion.
1057 unsigned LegalIntReg = LargestIntReg;
1058 for (unsigned IntReg = LargestIntReg - 1;
1059 IntReg >= (unsigned)MVT::i1; --IntReg) {
1060 MVT IVT = (MVT::SimpleValueType)IntReg;
1061 if (isTypeLegal(IVT)) {
1062 LegalIntReg = IntReg;
1063 } else {
1064 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1065 (const MVT::SimpleValueType)LegalIntReg;
1066 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1067 }
1068 }
1069
1070 // ppcf128 type is really two f64's.
1071 if (!isTypeLegal(MVT::ppcf128)) {
1072 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1073 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1074 TransformToType[MVT::ppcf128] = MVT::f64;
1075 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1076 }
1077
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1078 // Decide how to handle f128. If the target does not have native f128 support,
1079 // expand it to i128 and we will be generating soft float library calls.
1080 if (!isTypeLegal(MVT::f128)) {
1081 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1082 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1083 TransformToType[MVT::f128] = MVT::i128;
1084 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1085 }
1086
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1087 // Decide how to handle f64. If the target does not have native f64 support,
1088 // expand it to i64 and we will be generating soft float library calls.
1089 if (!isTypeLegal(MVT::f64)) {
1090 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1091 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1092 TransformToType[MVT::f64] = MVT::i64;
1093 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1094 }
1095
1096 // Decide how to handle f32. If the target does not have native support for
1097 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1098 if (!isTypeLegal(MVT::f32)) {
1099 if (isTypeLegal(MVT::f64)) {
1100 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1101 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1102 TransformToType[MVT::f32] = MVT::f64;
1103 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1104 } else {
1105 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1106 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1107 TransformToType[MVT::f32] = MVT::i32;
1108 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1109 }
1110 }
1111
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1112 if (!isTypeLegal(MVT::f16)) {
1113 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1114 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1115 TransformToType[MVT::f16] = MVT::i16;
1116 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1117 }
1118
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1119 // Loop over all of the vector value types to see which need transformations.
1120 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1122 MVT VT = (MVT::SimpleValueType) i;
1123 if (isTypeLegal(VT))
1124 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1125
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1126 MVT EltVT = VT.getVectorElementType();
1127 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1128 bool IsLegalWiderType = false;
1129 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1130 switch (PreferredAction) {
1131 case TypePromoteInteger: {
1132 // Try to promote the elements of integer vectors. If no legal
1133 // promotion was found, fall through to the widen-vector method.
1134 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1135 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1136 // Promote vectors of integers to vectors with the same number
1137 // of elements, with a wider element type.
1138 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1139 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1140 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1141 TransformToType[i] = SVT;
1142 RegisterTypeForVT[i] = SVT;
1143 NumRegistersForVT[i] = 1;
1144 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1145 IsLegalWiderType = true;
1146 break;
1147 }
1148 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1149 if (IsLegalWiderType)
1150 break;
1151 }
1152 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1153 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1154 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1155 MVT SVT = (MVT::SimpleValueType) nVT;
1156 if (SVT.getVectorElementType() == EltVT
1157 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1158 TransformToType[i] = SVT;
1159 RegisterTypeForVT[i] = SVT;
1160 NumRegistersForVT[i] = 1;
1161 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1162 IsLegalWiderType = true;
1163 break;
1164 }
1165 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1166 if (IsLegalWiderType)
1167 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1168 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1169 case TypeSplitVector:
1170 case TypeScalarizeVector: {
1171 MVT IntermediateVT;
1172 MVT RegisterVT;
1173 unsigned NumIntermediates;
1174 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1175 NumIntermediates, RegisterVT, this);
1176 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1177
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1178 MVT NVT = VT.getPow2VectorType();
1179 if (NVT == VT) {
1180 // Type is already a power of 2. The default action is to split.
1181 TransformToType[i] = MVT::Other;
1182 if (PreferredAction == TypeScalarizeVector)
1183 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1184 else
1185 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1186 } else {
1187 TransformToType[i] = NVT;
1188 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1189 }
1190 break;
1191 }
1192 default:
1193 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1194 }
1195 }
1196
1197 // Determine the 'representative' register class for each value type.
1198 // An representative register class is the largest (meaning one which is
1199 // not a sub-register class / subreg register class) legal register class for
1200 // a group of value types. For example, on i386, i8, i16, and i32
1201 // representative would be GR32; while on x86_64 it's GR64.
1202 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1203 const TargetRegisterClass* RRC;
1204 uint8_t Cost;
Benjamin Kramerd6f1f842014-03-02 13:30:33 +0000[diff] [blame]1205 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1206 RepRegClassForVT[i] = RRC;
1207 RepRegClassCostForVT[i] = Cost;
1208 }
1209}
1210
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1211EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1212 assert(!VT.isVector() && "No default SetCC type for vectors!");
1213 return getPointerTy(0).SimpleTy;
1214}
1215
1216MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1217 return MVT::i32; // return the default value
1218}
1219
1220/// getVectorTypeBreakdown - Vector types are broken down into some number of
1221/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1222/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1223/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1224///
1225/// This method returns the number of registers needed, and the VT for each
1226/// register. It also returns the VT and quantity of the intermediate values
1227/// before they are promoted/expanded.
1228///
1229unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1230 EVT &IntermediateVT,
1231 unsigned &NumIntermediates,
1232 MVT &RegisterVT) const {
1233 unsigned NumElts = VT.getVectorNumElements();
1234
1235 // If there is a wider vector type with the same element type as this one,
1236 // or a promoted vector type that has the same number of elements which
1237 // are wider, then we should convert to that legal vector type.
1238 // This handles things like <2 x float> -> <4 x float> and
1239 // <4 x i1> -> <4 x i32>.
1240 LegalizeTypeAction TA = getTypeAction(Context, VT);
1241 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1242 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1243 if (isTypeLegal(RegisterEVT)) {
1244 IntermediateVT = RegisterEVT;
1245 RegisterVT = RegisterEVT.getSimpleVT();
1246 NumIntermediates = 1;
1247 return 1;
1248 }
1249 }
1250
1251 // Figure out the right, legal destination reg to copy into.
1252 EVT EltTy = VT.getVectorElementType();
1253
1254 unsigned NumVectorRegs = 1;
1255
1256 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1257 // could break down into LHS/RHS like LegalizeDAG does.
1258 if (!isPowerOf2_32(NumElts)) {
1259 NumVectorRegs = NumElts;
1260 NumElts = 1;
1261 }
1262
1263 // Divide the input until we get to a supported size. This will always
1264 // end with a scalar if the target doesn't support vectors.
1265 while (NumElts > 1 && !isTypeLegal(
1266 EVT::getVectorVT(Context, EltTy, NumElts))) {
1267 NumElts >>= 1;
1268 NumVectorRegs <<= 1;
1269 }
1270
1271 NumIntermediates = NumVectorRegs;
1272
1273 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1274 if (!isTypeLegal(NewVT))
1275 NewVT = EltTy;
1276 IntermediateVT = NewVT;
1277
1278 MVT DestVT = getRegisterType(Context, NewVT);
1279 RegisterVT = DestVT;
1280 unsigned NewVTSize = NewVT.getSizeInBits();
1281
1282 // Convert sizes such as i33 to i64.
1283 if (!isPowerOf2_32(NewVTSize))
1284 NewVTSize = NextPowerOf2(NewVTSize);
1285
1286 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1287 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1288
1289 // Otherwise, promotion or legal types use the same number of registers as
1290 // the vector decimated to the appropriate level.
1291 return NumVectorRegs;
1292}
1293
1294/// Get the EVTs and ArgFlags collections that represent the legalized return
1295/// type of the given function. This does not require a DAG or a return value,
1296/// and is suitable for use before any DAGs for the function are constructed.
1297/// TODO: Move this out of TargetLowering.cpp.
1298void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1299 SmallVectorImpl<ISD::OutputArg> &Outs,
1300 const TargetLowering &TLI) {
1301 SmallVector<EVT, 4> ValueVTs;
1302 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1303 unsigned NumValues = ValueVTs.size();
1304 if (NumValues == 0) return;
1305
1306 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1307 EVT VT = ValueVTs[j];
1308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1309
1310 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1311 ExtendKind = ISD::SIGN_EXTEND;
1312 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1313 ExtendKind = ISD::ZERO_EXTEND;
1314
1315 // FIXME: C calling convention requires the return type to be promoted to
1316 // at least 32-bit. But this is not necessary for non-C calling
1317 // conventions. The frontend should mark functions whose return values
1318 // require promoting with signext or zeroext attributes.
1319 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1320 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1321 if (VT.bitsLT(MinVT))
1322 VT = MinVT;
1323 }
1324
1325 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1326 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1327
1328 // 'inreg' on function refers to return value
1329 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1330 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1331 Flags.setInReg();
1332
1333 // Propagate extension type if any
1334 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1335 Flags.setSExt();
1336 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1337 Flags.setZExt();
1338
1339 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1340 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1341 }
1342}
1343
1344/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1345/// function arguments in the caller parameter area. This is the actual
1346/// alignment, not its logarithm.
1347unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Rafael Espindola7c68beb2014-02-18 15:33:12 +0000[diff] [blame]1348 return DL->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1349}
1350
1351//===----------------------------------------------------------------------===//
1352// TargetTransformInfo Helpers
1353//===----------------------------------------------------------------------===//
1354
1355int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1356 enum InstructionOpcodes {
1357#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1358#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1359#include "llvm/IR/Instruction.def"
1360 };
1361 switch (static_cast<InstructionOpcodes>(Opcode)) {
1362 case Ret: return 0;
1363 case Br: return 0;
1364 case Switch: return 0;
1365 case IndirectBr: return 0;
1366 case Invoke: return 0;
1367 case Resume: return 0;
1368 case Unreachable: return 0;
1369 case Add: return ISD::ADD;
1370 case FAdd: return ISD::FADD;
1371 case Sub: return ISD::SUB;
1372 case FSub: return ISD::FSUB;
1373 case Mul: return ISD::MUL;
1374 case FMul: return ISD::FMUL;
1375 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1376 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1377 case FDiv: return ISD::FDIV;
1378 case URem: return ISD::UREM;
1379 case SRem: return ISD::SREM;
1380 case FRem: return ISD::FREM;
1381 case Shl: return ISD::SHL;
1382 case LShr: return ISD::SRL;
1383 case AShr: return ISD::SRA;
1384 case And: return ISD::AND;
1385 case Or: return ISD::OR;
1386 case Xor: return ISD::XOR;
1387 case Alloca: return 0;
1388 case Load: return ISD::LOAD;
1389 case Store: return ISD::STORE;
1390 case GetElementPtr: return 0;
1391 case Fence: return 0;
1392 case AtomicCmpXchg: return 0;
1393 case AtomicRMW: return 0;
1394 case Trunc: return ISD::TRUNCATE;
1395 case ZExt: return ISD::ZERO_EXTEND;
1396 case SExt: return ISD::SIGN_EXTEND;
1397 case FPToUI: return ISD::FP_TO_UINT;
1398 case FPToSI: return ISD::FP_TO_SINT;
1399 case UIToFP: return ISD::UINT_TO_FP;
1400 case SIToFP: return ISD::SINT_TO_FP;
1401 case FPTrunc: return ISD::FP_ROUND;
1402 case FPExt: return ISD::FP_EXTEND;
1403 case PtrToInt: return ISD::BITCAST;
1404 case IntToPtr: return ISD::BITCAST;
1405 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1406 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1407 case ICmp: return ISD::SETCC;
1408 case FCmp: return ISD::SETCC;
1409 case PHI: return 0;
1410 case Call: return 0;
1411 case Select: return ISD::SELECT;
1412 case UserOp1: return 0;
1413 case UserOp2: return 0;
1414 case VAArg: return 0;
1415 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1416 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1417 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1418 case ExtractValue: return ISD::MERGE_VALUES;
1419 case InsertValue: return ISD::MERGE_VALUES;
1420 case LandingPad: return 0;
1421 }
1422
1423 llvm_unreachable("Unknown instruction type encountered!");
1424}
1425
1426std::pair<unsigned, MVT>
1427TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1428 LLVMContext &C = Ty->getContext();
1429 EVT MTy = getValueType(Ty);
1430
1431 unsigned Cost = 1;
1432 // We keep legalizing the type until we find a legal kind. We assume that
1433 // the only operation that costs anything is the split. After splitting
1434 // we need to handle two types.
1435 while (true) {
1436 LegalizeKind LK = getTypeConversion(C, MTy);
1437
1438 if (LK.first == TypeLegal)
1439 return std::make_pair(Cost, MTy.getSimpleVT());
1440
1441 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1442 Cost *= 2;
1443
1444 // Keep legalizing the type.
1445 MTy = LK.second;
1446 }
1447}
1448
1449//===----------------------------------------------------------------------===//
1450// Loop Strength Reduction hooks
1451//===----------------------------------------------------------------------===//
1452
1453/// isLegalAddressingMode - Return true if the addressing mode represented
1454/// by AM is legal for this target, for a load/store of the specified type.
1455bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1456 Type *Ty) const {
1457 // The default implementation of this implements a conservative RISCy, r+r and
1458 // r+i addr mode.
1459
1460 // Allows a sign-extended 16-bit immediate field.
1461 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1462 return false;
1463
1464 // No global is ever allowed as a base.
1465 if (AM.BaseGV)
1466 return false;
1467
1468 // Only support r+r,
1469 switch (AM.Scale) {
1470 case 0: // "r+i" or just "i", depending on HasBaseReg.
1471 break;
1472 case 1:
1473 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1474 return false;
1475 // Otherwise we have r+r or r+i.
1476 break;
1477 case 2:
1478 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1479 return false;
1480 // Allow 2*r as r+r.
1481 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1482 default: // Don't allow n * r
1483 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1484 }
1485
1486 return true;
1487}