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gerrit-public.fairphone.software / toolchain / llvm-project / e33c95d39b4a315be12c79f710cb1550650cb457 / . / llvm / lib / Target / ARM / ARMScheduleA9.td
blob: 49fedf63f8bca209b925b0ac6d908deb31dad507 [file] [log] [blame]
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1//=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]2//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]7//
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM Cortex A9 processors.
11//
12//===----------------------------------------------------------------------===//
13
14//
15// Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
16// Reference Manual".
17//
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]18// Functional units
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]19def A9_Issue0 : FuncUnit; // Issue 0
20def A9_Issue1 : FuncUnit; // Issue 1
21def A9_Branch : FuncUnit; // Branch
22def A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0
23def A9_ALU1 : FuncUnit; // ALU pipeline 1
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]24def A9_AGU : FuncUnit; // Address generation unit for ld / st
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]25def A9_NPipe : FuncUnit; // NEON pipeline
26def A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]27def A9_LSUnit : FuncUnit; // L/S Unit
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]28def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
29def A9_DRegsN : FuncUnit; // FP register set, NEON side
30
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]31// Bypasses
32def A9_LdBypass : Bypass;
33
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]34def CortexA9Itineraries : ProcessorItineraries<
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]35 [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]36 A9_LSUnit, A9_DRegsVFP, A9_DRegsN],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]37 [A9_LdBypass], [
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]38 // Two fully-pipelined integer ALU pipelines
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]39
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]40 //
41 // Move instructions, unconditional
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]42 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
43 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
44 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
45 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
48 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
49 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
50 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
51 InstrStage<1, [A9_ALU0, A9_ALU1]>,
52 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Evan Chengb8b0ad82011-01-20 08:34:58 +0000[diff] [blame]53 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
54 InstrStage<1, [A9_ALU0, A9_ALU1]>,
55 InstrStage<1, [A9_ALU0, A9_ALU1]>,
56 InstrStage<1, [A9_ALU0, A9_ALU1]>], [3]>,
57 InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
58 InstrStage<1, [A9_ALU0, A9_ALU1]>,
59 InstrStage<1, [A9_ALU0, A9_ALU1]>,
60 InstrStage<1, [A9_MUX0], 0>,
61 InstrStage<1, [A9_AGU], 0>,
62 InstrStage<1, [A9_LSUnit]>], [5]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]63 //
64 // MVN instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]65 InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
66 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]67 [1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]68 InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
69 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]70 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]71 InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
72 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]73 [2, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]74 InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
75 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]76 [3, 1, 1]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]77 //
78 // No operand cycles
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]79 InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
80 InstrStage<1, [A9_ALU0, A9_ALU1]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]81 //
82 // Binary Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]83 InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
84 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]85 [1, 1], [NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]86 InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
87 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]88 [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]89 InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
90 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]91 [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]92 InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
93 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]94 [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]95 InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
96 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]97 [3, 1, 1, 1],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]98 [NoBypass, A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]99 //
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]100 // Bitwise Instructions that produce a result
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]101 InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
102 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
103 InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
104 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
105 InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
106 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
107 InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
108 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Chengc35d7bb2010-09-29 00:27:46 +0000[diff] [blame]109 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]110 // Unary Instructions that produce a result
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]111
112 // CLZ, RBIT, etc.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]113 InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
114 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]115
116 // BFC, BFI, UBFX, SBFX
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]117 InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
118 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]119
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]120 //
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]121 // Zero and sign extension instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]122 InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
123 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>,
124 InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
125 InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>,
126 InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
127 InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>,
Evan Cheng62d626c2010-09-25 00:49:35 +0000[diff] [blame]128 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]129 // Compare instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]130 InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
131 InstrStage<1, [A9_ALU0, A9_ALU1]>],
132 [1], [A9_LdBypass]>,
133 InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
134 InstrStage<1, [A9_ALU0, A9_ALU1]>],
135 [1, 1], [A9_LdBypass, A9_LdBypass]>,
Andrew Trick163a2442011-01-04 00:32:57 +0000[diff] [blame]136 InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
137 InstrStage<2, [A9_ALU0, A9_ALU1]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]138 [1, 1], [A9_LdBypass, NoBypass]>,
139 InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
140 InstrStage<3, [A9_ALU0, A9_ALU1]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]141 [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]142 //
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]143 // Test instructions
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]144 InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
145 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
146 InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
147 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
148 InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
149 InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>,
150 InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
151 InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>,
Evan Cheng2259d672010-09-29 00:49:25 +0000[diff] [blame]152 //
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]153 // Move instructions, conditional
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]154 // FIXME: Correctly model the extra input dep on the destination.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]155 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
156 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>,
157 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
158 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
159 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
160 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>,
161 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
162 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>,
Evan Cheng79ff5232010-11-13 05:14:20 +0000[diff] [blame]163 InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
164 InstrStage<1, [A9_ALU0, A9_ALU1]>,
165 InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
166 InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]167
168 // Integer multiply pipeline
169 //
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]170 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
171 InstrStage<2, [A9_ALU0]>], [3, 1, 1]>,
172 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
173 InstrStage<2, [A9_ALU0]>],
174 [3, 1, 1, 1]>,
175 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
176 InstrStage<2, [A9_ALU0]>], [4, 1, 1]>,
177 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
178 InstrStage<2, [A9_ALU0]>],
179 [4, 1, 1, 1]>,
180 InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
181 InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>,
182 InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
183 InstrStage<3, [A9_ALU0]>],
184 [4, 5, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]185 // Integer load pipeline
186 // FIXME: The timings are some rough approximations
187 //
188 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]189 InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]190 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]191 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]192 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]193 [3, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]194 InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]195 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]196 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]197 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]198 [4, 1], [A9_LdBypass]>,
199 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]200 InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]201 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]202 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]203 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]204 [3, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]205 //
206 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]207 InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]208 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]209 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]210 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]211 [3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]212 InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]213 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]214 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]215 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]216 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]217 InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]218 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]219 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]220 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]221 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]222 //
223 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]224 InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]225 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]226 InstrStage<1, [A9_AGU], 0>,
227 InstrStage<1, [A9_LSUnit], 0>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]228 [4, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]229 InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]230 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]231 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]232 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]233 [5, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]234 //
235 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]236 InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]237 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]238 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]239 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]240 [3, 2, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]241 InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]242 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]243 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]244 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]245 [4, 3, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]246 //
247 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]248 InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]249 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]250 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]251 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]252 [3, 2, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]253 InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]254 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]255 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]256 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]257 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]258 InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]259 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]260 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]261 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]262 [3, 3, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]263 //
264 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]265 InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]266 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]267 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]268 InstrStage<1, [A9_LSUnit]>],
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]269 [4, 3, 1, 1], [A9_LdBypass]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]270 InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]271 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]272 InstrStage<2, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]273 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]274 [5, 4, 1, 1], [A9_LdBypass]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]275 //
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]276 // Load multiple, def is the 5th operand.
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]277 // FIXME: This assumes 3 to 4 registers.
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]278 InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]279 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]280 InstrStage<2, [A9_AGU], 1>,
281 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]282 [1, 1, 1, 1, 3],
283 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
284 //
285 // Load multiple + update, defs are the 1st and 5th operands.
286 InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
287 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]288 InstrStage<2, [A9_AGU], 1>,
289 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]290 [2, 1, 1, 1, 3],
291 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng722cd122010-09-08 22:57:08 +0000[diff] [blame]292 //
293 // Load multiple plus branch
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]294 InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]295 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]296 InstrStage<1, [A9_AGU], 1>,
297 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]298 InstrStage<1, [A9_Branch]>],
299 [1, 2, 1, 1, 3],
300 [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass]>,
301 //
302 // Pop, def is the 3rd operand.
303 InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
304 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]305 InstrStage<2, [A9_AGU], 1>,
306 InstrStage<2, [A9_LSUnit]>],
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]307 [1, 1, 3],
308 [NoBypass, NoBypass, A9_LdBypass]>,
309 //
310 // Pop + branch, def is the 3rd operand.
311 InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
312 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]313 InstrStage<2, [A9_AGU], 1>,
314 InstrStage<2, [A9_LSUnit]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]315 InstrStage<1, [A9_Branch]>],
316 [1, 1, 3],
317 [NoBypass, NoBypass, A9_LdBypass]>,
Evan Cheng722cd122010-09-08 22:57:08 +0000[diff] [blame]318
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]319 //
320 // iLoadi + iALUr for t2LDRpci_pic.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]321 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]322 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]323 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]324 InstrStage<1, [A9_LSUnit]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]325 InstrStage<1, [A9_ALU0, A9_ALU1]>],
Evan Cheng4a010fd2010-09-29 22:42:35 +0000[diff] [blame]326 [2, 1]>,
Evan Chenge37da032010-09-24 22:41:41 +0000[diff] [blame]327
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]328 // Integer store pipeline
329 ///
330 // Immediate offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]331 InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]332 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]333 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]334 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]335 InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]336 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]337 InstrStage<2, [A9_AGU], 1>,
338 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Evan Cheng2fb20b12010-09-30 01:08:25 +0000[diff] [blame]339 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]340 InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]341 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]342 InstrStage<2, [A9_AGU], 1>,
343 InstrStage<1, [A9_LSUnit]>], [1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]344 //
345 // Register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]346 InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]347 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]348 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]349 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]350 InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]351 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]352 InstrStage<2, [A9_AGU], 1>,
353 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]354 InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]355 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]356 InstrStage<2, [A9_AGU], 1>,
357 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]358 //
359 // Scaled register offset
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]360 InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
361 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]362 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]363 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]364 InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]365 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]366 InstrStage<2, [A9_AGU], 1>,
367 InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]368 //
369 // Immediate offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]370 InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
371 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]372 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]373 InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]374 InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]375 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]376 InstrStage<2, [A9_AGU], 1>,
377 InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]378 //
379 // Register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]380 InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
381 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]382 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]383 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]384 [2, 1, 1, 1]>,
385 InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]386 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]387 InstrStage<2, [A9_AGU], 1>,
388 InstrStage<1, [A9_LSUnit]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]389 [3, 1, 1, 1]>,
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]390 InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
391 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]392 InstrStage<2, [A9_AGU], 1>,
393 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]394 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]395 //
396 // Scaled register offset with update
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]397 InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
398 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]399 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]400 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]401 [2, 1, 1, 1]>,
402 InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
403 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]404 InstrStage<2, [A9_AGU], 1>,
405 InstrStage<1, [A9_LSUnit]>],
Evan Cheng73eac2a2010-10-03 02:03:59 +0000[diff] [blame]406 [3, 1, 1, 1]>,
Anton Korobeynikov2a21aef2010-05-29 19:25:34 +0000[diff] [blame]407 //
408 // Store multiple
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]409 InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]410 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]411 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]412 InstrStage<2, [A9_LSUnit]>]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]413 //
414 // Store multiple + update
415 InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
416 InstrStage<1, [A9_MUX0], 0>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]417 InstrStage<1, [A9_AGU], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]418 InstrStage<2, [A9_LSUnit]>], [2]>,
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]419
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]420 //
421 // Preload
422 InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>,
423
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]424 // Branch
425 //
426 // no delay slots, so the latency of a branch is unimportant
Evan Cheng49d4c0b2010-10-06 06:27:31 +0000[diff] [blame]427 InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>,
428 InstrStage<1, [A9_Issue1], 0>,
429 InstrStage<1, [A9_Branch]>]>,
Anton Korobeynikov94d7fd82010-05-29 19:25:17 +0000[diff] [blame]430
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]431 // VFP and NEON shares the same register file. This means that every VFP
432 // instruction should wait for full completion of the consecutive NEON
433 // instruction and vice-versa. We model this behavior with two artificial FUs:
434 // DRegsVFP and DRegsVFP.
435 //
436 // Every VFP instruction:
437 // - Acquires DRegsVFP resource for 1 cycle
438 // - Reserves DRegsN resource for the whole duration (including time to
439 // register file writeback!).
440 // Every NEON instruction does the same but with FUs swapped.
441 //
Jim Grosbach7ea5fc02010-06-28 04:27:01 +0000[diff] [blame]442 // Since the reserved FU cannot be acquired, this models precisely
443 // "cross-domain" stalls.
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]444
445 // VFP
446 // Issue through integer pipeline, and execute in NEON unit.
447
448 // FP Special Register to Integer Register File Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]449 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]450 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]451 InstrStage<1, [A9_DRegsVFP], 0, Required>,
452 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng99cce362010-10-29 23:16:55 +0000[diff] [blame]453 InstrStage<1, [A9_NPipe]>],
454 [1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]455 //
456 // Single-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]457 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
458 InstrStage<1, [A9_MUX0], 0>,
459 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]460 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]461 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]462 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]463 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]464 //
465 // Double-precision FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]466 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
467 InstrStage<1, [A9_MUX0], 0>,
468 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]469 // Extra latency cycles since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]470 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]471 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]472 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]473
474 //
475 // Single-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]476 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
477 InstrStage<1, [A9_MUX0], 0>,
478 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]479 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]480 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]481 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]482 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]483 //
484 // Double-precision FP Compare
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]485 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
486 InstrStage<1, [A9_MUX0], 0>,
487 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]488 // Extra latency cycles since wbck is 4 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]489 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]490 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]491 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]492 //
493 // Single to Double FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]494 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]495 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]496 InstrStage<1, [A9_DRegsVFP], 0, Required>,
497 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]498 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]499 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]500 //
501 // Double to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]502 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]503 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]504 InstrStage<1, [A9_DRegsVFP], 0, Required>,
505 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]506 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]507 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]508
509 //
510 // Single to Half FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]511 InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]512 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]513 InstrStage<1, [A9_DRegsVFP], 0, Required>,
514 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]515 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]516 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]517 //
518 // Half to Single FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]519 InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]520 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]521 InstrStage<1, [A9_DRegsVFP], 0, Required>,
522 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]523 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]524 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]525
526 //
527 // Single-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]528 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]529 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]530 InstrStage<1, [A9_DRegsVFP], 0, Required>,
531 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]532 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]533 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]534 //
535 // Double-Precision FP to Integer Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]536 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]537 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]538 InstrStage<1, [A9_DRegsVFP], 0, Required>,
539 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]540 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]541 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]542 //
543 // Integer to Single-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]544 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]545 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]546 InstrStage<1, [A9_DRegsVFP], 0, Required>,
547 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]548 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]549 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]550 //
551 // Integer to Double-Precision FP Convert
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]552 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]553 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]554 InstrStage<1, [A9_DRegsVFP], 0, Required>,
555 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]556 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]557 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]558 //
559 // Single-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]560 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]561 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]562 InstrStage<1, [A9_DRegsVFP], 0, Required>,
563 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]564 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]565 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]566 //
567 // Double-precision FP ALU
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]568 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]569 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]570 InstrStage<1, [A9_DRegsVFP], 0, Required>,
571 InstrStage<5, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]572 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]573 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]574 //
575 // Single-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]576 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]577 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]578 InstrStage<1, [A9_DRegsVFP], 0, Required>,
579 InstrStage<6, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]580 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]581 [5, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]582 //
583 // Double-precision FP Multiply
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]584 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]585 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]586 InstrStage<1, [A9_DRegsVFP], 0, Required>,
587 InstrStage<7, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]588 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]589 [6, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]590 //
591 // Single-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]592 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]593 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]594 InstrStage<1, [A9_DRegsVFP], 0, Required>,
595 InstrStage<9, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]596 InstrStage<1, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]597 [8, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]598 //
599 // Double-precision FP MAC
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]600 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]601 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]602 InstrStage<1, [A9_DRegsVFP], 0, Required>,
603 InstrStage<10, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]604 InstrStage<2, [A9_NPipe]>],
Evan Chengff310732010-10-28 06:47:08 +0000[diff] [blame]605 [9, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]606 //
607 // Single-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]608 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]609 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]610 InstrStage<1, [A9_DRegsVFP], 0, Required>,
611 InstrStage<16, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]612 InstrStage<10, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]613 [15, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]614 //
615 // Double-precision FP DIV
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]616 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]617 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]618 InstrStage<1, [A9_DRegsVFP], 0, Required>,
619 InstrStage<26, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]620 InstrStage<20, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]621 [25, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]622 //
623 // Single-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]624 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]625 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]626 InstrStage<1, [A9_DRegsVFP], 0, Required>,
627 InstrStage<18, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]628 InstrStage<13, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]629 [17, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]630 //
631 // Double-precision FP SQRT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]632 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]633 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]634 InstrStage<1, [A9_DRegsVFP], 0, Required>,
635 InstrStage<33, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]636 InstrStage<28, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]637 [32, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]638
639 //
640 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]641 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
642 InstrStage<1, [A9_MUX0], 0>,
643 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]644 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]645 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]646 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]647 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]648 //
649 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]650 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
651 InstrStage<1, [A9_MUX0], 0>,
652 InstrStage<1, [A9_DRegsVFP], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]653 // Extra 1 latency cycle since wbck is 2 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]654 InstrStage<3, [A9_DRegsN], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]655 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]656 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]657 //
658 // Single-precision to Integer Move
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]659 //
660 // On A9 move-from-VFP is free to issue with no stall if other VFP
661 // operations are in flight. I assume it still can't dual-issue though.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]662 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]663 InstrStage<1, [A9_MUX0], 0>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]664 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]665 //
666 // Double-precision to Integer Move
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]667 //
668 // On A9 move-from-VFP is free to issue with no stall if other VFP
669 // operations are in flight. I assume it still can't dual-issue though.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]670 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]671 InstrStage<1, [A9_MUX0], 0>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]672 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]673 //
674 // Single-precision FP Load
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]675 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]676 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]677 InstrStage<1, [A9_DRegsVFP], 0, Required>,
678 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]679 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]680 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]681 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]682 //
683 // Double-precision FP Load
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]684 // FIXME: Result latency is 1 if address is 64-bit aligned.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]685 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]686 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]687 InstrStage<1, [A9_DRegsVFP], 0, Required>,
688 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]689 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]690 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]691 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]692 //
693 // FP Load Multiple
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]694 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]695 InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]696 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]697 InstrStage<1, [A9_DRegsVFP], 0, Required>,
698 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]699 InstrStage<1, [A9_NPipe], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]700 InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]701 //
702 // FP Load Multiple + update
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]703 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]704 InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]705 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]706 InstrStage<1, [A9_DRegsVFP], 0, Required>,
707 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]708 InstrStage<1, [A9_NPipe], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]709 InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]710 //
711 // Single-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]712 InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]713 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]714 InstrStage<1, [A9_DRegsVFP], 0, Required>,
715 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]716 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]717 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]718 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]719 //
720 // Double-precision FP Store
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]721 InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]722 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]723 InstrStage<1, [A9_DRegsVFP], 0, Required>,
724 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]725 InstrStage<1, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]726 InstrStage<1, [A9_LSUnit]>],
Evan Chengf3179562010-10-01 21:40:30 +0000[diff] [blame]727 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]728 //
729 // FP Store Multiple
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]730 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]731 InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]732 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]733 InstrStage<1, [A9_DRegsVFP], 0, Required>,
734 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]735 InstrStage<1, [A9_NPipe], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]736 InstrStage<2, [A9_LSUnit]>], [1, 1, 1, 1]>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]737 //
738 // FP Store Multiple + update
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]739 // FIXME: assumes 2 doubles which requires 2 LS cycles.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]740 InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng1958cef2010-10-07 01:50:48 +0000[diff] [blame]741 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]742 InstrStage<1, [A9_DRegsVFP], 0, Required>,
743 InstrStage<2, [A9_DRegsN], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]744 InstrStage<1, [A9_NPipe], 0>,
Bob Wilsonf33715e2011-04-19 18:11:36 +0000[diff] [blame]745 InstrStage<2, [A9_LSUnit]>], [2, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]746 // NEON
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]747 // VLD1
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]748 InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]749 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]750 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]751 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
752 InstrStage<1, [A9_NPipe], 0>,
753 InstrStage<1, [A9_LSUnit]>],
754 [1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]755 // VLD1x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]756 InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]757 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]758 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]759 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
760 InstrStage<1, [A9_NPipe], 0>,
761 InstrStage<1, [A9_LSUnit]>],
762 [1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]763 // VLD1x3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]764 InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]765 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]766 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]767 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
768 InstrStage<2, [A9_NPipe], 0>,
769 InstrStage<2, [A9_LSUnit]>],
770 [1, 1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]771 // VLD1x4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]772 InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]773 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]774 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]775 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
776 InstrStage<2, [A9_NPipe], 0>,
777 InstrStage<2, [A9_LSUnit]>],
778 [1, 1, 2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]779 // VLD1u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]780 InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]781 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]782 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]783 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
784 InstrStage<1, [A9_NPipe], 0>,
785 InstrStage<1, [A9_LSUnit]>],
786 [1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]787 // VLD1x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]788 InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]789 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]790 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]791 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
792 InstrStage<1, [A9_NPipe], 0>,
793 InstrStage<1, [A9_LSUnit]>],
794 [1, 1, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]795 // VLD1x3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]796 InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]797 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]798 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]799 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
800 InstrStage<2, [A9_NPipe], 0>,
801 InstrStage<2, [A9_LSUnit]>],
802 [1, 1, 2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]803 // VLD1x4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]804 InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]805 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]806 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]807 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
808 InstrStage<2, [A9_NPipe], 0>,
809 InstrStage<2, [A9_LSUnit]>],
810 [1, 1, 2, 2, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]811 //
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]812 // VLD1ln
813 InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
814 InstrStage<1, [A9_MUX0], 0>,
815 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]816 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
817 InstrStage<2, [A9_NPipe], 0>,
818 InstrStage<2, [A9_LSUnit]>],
819 [3, 1, 1, 1]>,
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]820 //
821 // VLD1lnu
822 InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
823 InstrStage<1, [A9_MUX0], 0>,
824 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]825 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
826 InstrStage<2, [A9_NPipe], 0>,
827 InstrStage<2, [A9_LSUnit]>],
828 [3, 2, 1, 1, 1, 1]>,
Bob Wilsondc449902010-11-01 22:04:05 +0000[diff] [blame]829 //
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]830 // VLD1dup
831 InstrItinData<IIC_VLD1dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
832 InstrStage<1, [A9_MUX0], 0>,
833 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]834 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
835 InstrStage<1, [A9_NPipe], 0>,
836 InstrStage<1, [A9_LSUnit]>],
837 [2, 1]>,
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]838 //
839 // VLD1dupu
840 InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
841 InstrStage<1, [A9_MUX0], 0>,
842 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]843 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
844 InstrStage<1, [A9_NPipe], 0>,
845 InstrStage<1, [A9_LSUnit]>],
846 [2, 2, 1, 1]>,
Bob Wilsonc92eea02010-11-27 06:35:16 +0000[diff] [blame]847 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]848 // VLD2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]849 InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
850 InstrStage<1, [A9_MUX0], 0>,
851 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]852 // Extra latency cycles since wbck is 7 cycles
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]853 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
854 InstrStage<1, [A9_NPipe], 0>,
855 InstrStage<1, [A9_LSUnit]>],
856 [2, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]857 //
858 // VLD2x2
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]859 InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]860 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]861 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]862 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
863 InstrStage<2, [A9_NPipe], 0>,
864 InstrStage<2, [A9_LSUnit]>],
865 [2, 3, 2, 3, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]866 //
867 // VLD2ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]868 InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]869 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]870 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]871 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
872 InstrStage<2, [A9_NPipe], 0>,
873 InstrStage<2, [A9_LSUnit]>],
874 [3, 3, 1, 1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]875 //
876 // VLD2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]877 InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
878 InstrStage<1, [A9_MUX0], 0>,
879 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]880 // Extra latency cycles since wbck is 7 cycles
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]881 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
882 InstrStage<1, [A9_NPipe], 0>,
883 InstrStage<1, [A9_LSUnit]>],
884 [2, 2, 2, 1, 1, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]885 //
886 // VLD2x2u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]887 InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]888 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]889 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]890 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
891 InstrStage<2, [A9_NPipe], 0>,
892 InstrStage<2, [A9_LSUnit]>],
893 [2, 3, 2, 3, 2, 1]>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]894 //
895 // VLD2lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]896 InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Cheng05f13e92010-10-09 01:03:04 +0000[diff] [blame]897 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]898 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]899 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
900 InstrStage<2, [A9_NPipe], 0>,
901 InstrStage<2, [A9_LSUnit]>],
902 [3, 3, 2, 1, 1, 1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]903 //
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]904 // VLD2dup
905 InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
906 InstrStage<1, [A9_MUX0], 0>,
907 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]908 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
909 InstrStage<1, [A9_NPipe], 0>,
910 InstrStage<1, [A9_LSUnit]>],
911 [2, 2, 1]>,
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]912 //
913 // VLD2dupu
914 InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
915 InstrStage<1, [A9_MUX0], 0>,
916 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]917 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
918 InstrStage<1, [A9_NPipe], 0>,
919 InstrStage<1, [A9_LSUnit]>],
920 [2, 2, 2, 1, 1]>,
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]921 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]922 // VLD3
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]923 InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]924 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]925 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]926 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
927 InstrStage<3, [A9_NPipe], 0>,
928 InstrStage<3, [A9_LSUnit]>],
929 [3, 3, 4, 1]>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]930 //
931 // VLD3ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]932 InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]933 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]934 InstrStage<1, [A9_DRegsN], 0, Required>,
935 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]936 InstrStage<5, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]937 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]938 [5, 5, 6, 1, 1, 1, 1, 2]>,
939 //
940 // VLD3u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]941 InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]942 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]943 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]944 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
945 InstrStage<3, [A9_NPipe], 0>,
946 InstrStage<3, [A9_LSUnit]>],
947 [3, 3, 4, 2, 1]>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]948 //
949 // VLD3lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]950 InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]951 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]952 InstrStage<1, [A9_DRegsN], 0, Required>,
953 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]954 InstrStage<5, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]955 InstrStage<5, [A9_LSUnit]>],
Evan Chenga7624002010-10-09 01:45:34 +0000[diff] [blame]956 [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]957 //
Bob Wilson77ab1652010-11-29 19:35:29 +0000[diff] [blame]958 // VLD3dup
959 InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
960 InstrStage<1, [A9_MUX0], 0>,
961 InstrStage<1, [A9_DRegsN], 0, Required>,
962 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
963 InstrStage<3, [A9_NPipe], 0>,
964 InstrStage<3, [A9_LSUnit]>],
965 [3, 3, 4, 1]>,
966 //
967 // VLD3dupu
968 InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
969 InstrStage<1, [A9_MUX0], 0>,
970 InstrStage<1, [A9_DRegsN], 0, Required>,
971 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
972 InstrStage<3, [A9_NPipe], 0>,
973 InstrStage<3, [A9_LSUnit]>],
974 [3, 3, 4, 2, 1, 1]>,
975 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]976 // VLD4
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]977 InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]978 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]979 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]980 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
981 InstrStage<3, [A9_NPipe], 0>,
982 InstrStage<3, [A9_LSUnit]>],
983 [3, 3, 4, 4, 1]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]984 //
985 // VLD4ln
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]986 InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]987 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]988 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]989 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
990 InstrStage<4, [A9_NPipe], 0>,
991 InstrStage<4, [A9_LSUnit]>],
992 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]993 //
994 // VLD4u
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]995 InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]996 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]997 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]998 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
999 InstrStage<3, [A9_NPipe], 0>,
1000 InstrStage<3, [A9_LSUnit]>],
1001 [3, 3, 4, 4, 2, 1]>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1002 //
1003 // VLD4lnu
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1004 InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chengd7a404d2010-10-09 04:07:58 +0000[diff] [blame]1005 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1006 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1007 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
1008 InstrStage<4, [A9_NPipe], 0>,
1009 InstrStage<4, [A9_LSUnit]>],
1010 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1011 //
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1012 // VLD4dup
1013 InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1014 InstrStage<1, [A9_MUX0], 0>,
1015 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1016 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1017 InstrStage<2, [A9_NPipe], 0>,
1018 InstrStage<2, [A9_LSUnit]>],
1019 [2, 2, 3, 3, 1]>,
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1020 //
1021 // VLD4dupu
1022 InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1023 InstrStage<1, [A9_MUX0], 0>,
1024 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1025 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1026 InstrStage<2, [A9_NPipe], 0>,
1027 InstrStage<2, [A9_LSUnit]>],
1028 [2, 2, 3, 3, 2, 1, 1]>,
Bob Wilson431ac4ef2010-11-30 00:00:35 +0000[diff] [blame]1029 //
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1030 // VST1
1031 InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1032 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1033 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1034 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1035 InstrStage<1, [A9_NPipe], 0>,
1036 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1037 [1, 1, 1]>,
1038 //
1039 // VST1x2
1040 InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1041 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1042 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1043 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1044 InstrStage<1, [A9_NPipe], 0>,
1045 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1046 [1, 1, 1, 1]>,
1047 //
1048 // VST1x3
1049 InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1050 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1051 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1052 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1053 InstrStage<2, [A9_NPipe], 0>,
1054 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1055 [1, 1, 1, 1, 2]>,
1056 //
1057 // VST1x4
1058 InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1059 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1060 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1061 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1062 InstrStage<2, [A9_NPipe], 0>,
1063 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1064 [1, 1, 1, 1, 2, 2]>,
1065 //
1066 // VST1u
1067 InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1068 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1069 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1070 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1071 InstrStage<1, [A9_NPipe], 0>,
1072 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1073 [2, 1, 1, 1, 1]>,
1074 //
1075 // VST1x2u
1076 InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1077 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1078 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1079 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1080 InstrStage<1, [A9_NPipe], 0>,
1081 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1082 [2, 1, 1, 1, 1, 1]>,
1083 //
1084 // VST1x3u
1085 InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1086 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1087 InstrStage<1, [A9_DRegsN], 0, Required>,
1088 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1089 InstrStage<2, [A9_NPipe], 0>,
1090 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1091 [2, 1, 1, 1, 1, 1, 2]>,
1092 //
1093 // VST1x4u
1094 InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1095 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1096 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1097 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1098 InstrStage<2, [A9_NPipe], 0>,
1099 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1100 [2, 1, 1, 1, 1, 1, 2, 2]>,
1101 //
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1102 // VST1ln
1103 InstrItinData<IIC_VST1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1104 InstrStage<1, [A9_MUX0], 0>,
1105 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1106 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1107 InstrStage<1, [A9_NPipe], 0>,
1108 InstrStage<1, [A9_LSUnit]>],
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1109 [1, 1, 1]>,
1110 //
1111 // VST1lnu
1112 InstrItinData<IIC_VST1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1113 InstrStage<1, [A9_MUX0], 0>,
1114 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1115 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1116 InstrStage<1, [A9_NPipe], 0>,
1117 InstrStage<1, [A9_LSUnit]>],
Bob Wilsond80b29d2010-11-02 21:18:25 +0000[diff] [blame]1118 [2, 1, 1, 1, 1]>,
1119 //
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1120 // VST2
1121 InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1122 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1123 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1124 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1125 InstrStage<1, [A9_NPipe], 0>,
1126 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1127 [1, 1, 1, 1]>,
1128 //
1129 // VST2x2
1130 InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1131 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1132 InstrStage<1, [A9_DRegsN], 0, Required>,
1133 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1134 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1135 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1136 [1, 1, 1, 1, 2, 2]>,
1137 //
1138 // VST2u
1139 InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1140 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1141 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1142 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1143 InstrStage<1, [A9_NPipe], 0>,
1144 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1145 [2, 1, 1, 1, 1, 1]>,
1146 //
1147 // VST2x2u
1148 InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1149 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1150 InstrStage<1, [A9_DRegsN], 0, Required>,
1151 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1152 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1153 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1154 [2, 1, 1, 1, 1, 1, 2, 2]>,
1155 //
1156 // VST2ln
1157 InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1158 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1159 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1160 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1161 InstrStage<1, [A9_NPipe], 0>,
1162 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1163 [1, 1, 1, 1]>,
1164 //
1165 // VST2lnu
1166 InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1167 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1168 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1169 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1170 InstrStage<1, [A9_NPipe], 0>,
1171 InstrStage<1, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1172 [2, 1, 1, 1, 1, 1]>,
1173 //
1174 // VST3
1175 InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1176 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1177 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1178 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1179 InstrStage<2, [A9_NPipe], 0>,
1180 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1181 [1, 1, 1, 1, 2]>,
1182 //
1183 // VST3u
1184 InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1185 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1186 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1187 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1188 InstrStage<2, [A9_NPipe], 0>,
1189 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1190 [2, 1, 1, 1, 1, 1, 2]>,
1191 //
1192 // VST3ln
1193 InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1194 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1195 InstrStage<1, [A9_DRegsN], 0, Required>,
1196 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1197 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1198 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1199 [1, 1, 1, 1, 2]>,
1200 //
1201 // VST3lnu
1202 InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1203 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1204 InstrStage<1, [A9_DRegsN], 0, Required>,
1205 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Cheng634ab6c2010-11-03 00:40:22 +0000[diff] [blame]1206 InstrStage<3, [A9_NPipe], 0>,
Evan Cheng39121582010-10-13 01:54:21 +0000[diff] [blame]1207 InstrStage<3, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1208 [2, 1, 1, 1, 1, 1, 2]>,
1209 //
1210 // VST4
1211 InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1212 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1213 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1214 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1215 InstrStage<2, [A9_NPipe], 0>,
1216 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1217 [1, 1, 1, 1, 2, 2]>,
1218 //
1219 // VST4u
1220 InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1221 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1222 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1223 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1224 InstrStage<2, [A9_NPipe], 0>,
1225 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1226 [2, 1, 1, 1, 1, 1, 2, 2]>,
1227 //
1228 // VST4ln
1229 InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1230 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1231 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1232 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1233 InstrStage<2, [A9_NPipe], 0>,
1234 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1235 [1, 1, 1, 1, 2, 2]>,
1236 //
1237 // VST4lnu
1238 InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1239 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1240 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng7d6cd4902011-04-19 01:21:49 +0000[diff] [blame]1241 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1242 InstrStage<2, [A9_NPipe], 0>,
1243 InstrStage<2, [A9_LSUnit]>],
Evan Cheng94ad0082010-10-11 22:03:18 +0000[diff] [blame]1244 [2, 1, 1, 1, 1, 1, 2, 2]>,
1245
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1246 //
1247 // Double-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1248 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1249 InstrStage<1, [A9_MUX0], 0>,
1250 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1251 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1252 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1253 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1254 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1255 //
1256 // Quad-register Integer Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1257 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1258 InstrStage<1, [A9_MUX0], 0>,
1259 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1260 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1261 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1262 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1263 [4, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1264 //
1265 // Double-register Integer Q-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1266 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1267 InstrStage<1, [A9_MUX0], 0>,
1268 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1269 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1270 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1271 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1272 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1273 //
1274 // Quad-register Integer CountQ-Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1275 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1276 InstrStage<1, [A9_MUX0], 0>,
1277 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1278 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1279 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1280 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1281 [4, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1282 //
1283 // Double-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1284 InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1285 InstrStage<1, [A9_MUX0], 0>,
1286 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1287 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1288 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1289 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1290 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1291 //
1292 // Quad-register Integer Binary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1293 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1294 InstrStage<1, [A9_MUX0], 0>,
1295 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1296 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1297 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1298 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1299 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1300 //
1301 // Double-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1302 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1303 InstrStage<1, [A9_MUX0], 0>,
1304 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1305 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1306 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1307 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1308 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1309 //
1310 // Quad-register Integer Subtract
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1311 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1312 InstrStage<1, [A9_MUX0], 0>,
1313 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1314 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1315 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1316 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1317 [3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1318 //
1319 // Double-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1320 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1321 InstrStage<1, [A9_MUX0], 0>,
1322 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1323 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1324 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1325 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1326 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1327 //
1328 // Quad-register Integer Shift
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1329 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1330 InstrStage<1, [A9_MUX0], 0>,
1331 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1332 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1333 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1334 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1335 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1336 //
1337 // Double-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1338 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1339 InstrStage<1, [A9_MUX0], 0>,
1340 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1341 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1342 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1343 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1344 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1345 //
1346 // Quad-register Integer Shift (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1347 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1348 InstrStage<1, [A9_MUX0], 0>,
1349 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1350 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1351 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1352 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1353 [4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1354 //
1355 // Double-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1356 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1357 InstrStage<1, [A9_MUX0], 0>,
1358 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1359 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1360 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1361 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1362 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1363 //
1364 // Quad-register Integer Binary (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1365 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1366 InstrStage<1, [A9_MUX0], 0>,
1367 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1368 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1369 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1370 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1371 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1372 //
1373 // Double-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1374 InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1375 InstrStage<1, [A9_MUX0], 0>,
1376 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1377 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1378 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1379 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1380 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1381 //
1382 // Quad-register Integer Subtract (4 cycle)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1383 InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1384 InstrStage<1, [A9_MUX0], 0>,
1385 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1386 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1387 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1388 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1389 [4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1390
1391 //
1392 // Double-register Integer Count
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1393 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1394 InstrStage<1, [A9_MUX0], 0>,
1395 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1396 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1397 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1398 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1399 [3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1400 //
1401 // Quad-register Integer Count
1402 // Result written in N3, but that is relative to the last cycle of multicycle,
1403 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1404 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1405 InstrStage<1, [A9_MUX0], 0>,
1406 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1407 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1408 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1409 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1410 [4, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1411 //
1412 // Double-register Absolute Difference and Accumulate
Evan Cheng7f3e9152010-12-08 23:01:18 +0000[diff] [blame]1413 InstrItinData<IIC_VABAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1414 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1415 InstrStage<1, [A9_DRegsN], 0, Required>,
1416 // Extra latency cycles since wbck is 6 cycles
Evan Cheng7f3e9152010-12-08 23:01:18 +0000[diff] [blame]1417 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1418 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1419 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1420 //
1421 // Quad-register Absolute Difference and Accumulate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1422 InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1423 InstrStage<1, [A9_MUX0], 0>,
1424 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1425 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1426 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1427 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1428 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1429 //
1430 // Double-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1431 InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1432 InstrStage<1, [A9_MUX0], 0>,
1433 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1434 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1435 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1436 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1437 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1438 //
1439 // Quad-register Integer Pair Add Long
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1440 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1441 InstrStage<1, [A9_MUX0], 0>,
1442 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1443 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1444 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1445 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1446 [6, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1447
1448 //
1449 // Double-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1450 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1451 InstrStage<1, [A9_MUX0], 0>,
1452 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1453 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1454 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1455 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1456 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1457 //
1458 // Quad-register Integer Multiply (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1459 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1460 InstrStage<1, [A9_MUX0], 0>,
1461 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1462 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1463 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1464 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1465 [7, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1466
1467 //
1468 // Double-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1469 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1470 InstrStage<1, [A9_MUX0], 0>,
1471 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1472 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1473 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1474 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1475 [7, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1476 //
1477 // Quad-register Integer Multiply (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1478 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1479 InstrStage<1, [A9_MUX0], 0>,
1480 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1481 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1482 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1483 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1484 [9, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1485 //
1486 // Double-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1487 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1488 InstrStage<1, [A9_MUX0], 0>,
1489 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1490 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1491 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1492 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1493 [6, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1494 //
1495 // Double-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1496 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1497 InstrStage<1, [A9_MUX0], 0>,
1498 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1499 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1500 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1501 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1502 [7, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1503 //
1504 // Quad-register Integer Multiply-Accumulate (.8, .16)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1505 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1506 InstrStage<1, [A9_MUX0], 0>,
1507 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1508 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1509 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1510 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1511 [7, 3, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1512 //
1513 // Quad-register Integer Multiply-Accumulate (.32)
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1514 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1515 InstrStage<1, [A9_MUX0], 0>,
1516 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1517 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1518 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1519 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1520 [9, 3, 2, 1]>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1521
1522 //
1523 // Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1524 InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1525 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1526 InstrStage<1, [A9_DRegsN], 0, Required>,
1527 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1528 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1529 [1,1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1530 //
1531 // Move Immediate
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1532 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1533 InstrStage<1, [A9_MUX0], 0>,
1534 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1535 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1536 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1537 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1538 [3]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1539 //
1540 // Double-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1541 InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1542 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1543 InstrStage<1, [A9_DRegsN], 0, Required>,
1544 // Extra latency cycles since wbck is 6 cycles
1545 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1546 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1547 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1548 //
1549 // Quad-register Permute Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1550 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1551 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1552 InstrStage<1, [A9_DRegsN], 0, Required>,
1553 // Extra latency cycles since wbck is 6 cycles
1554 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1555 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1556 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1557 //
1558 // Integer to Single-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1559 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1560 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1561 InstrStage<1, [A9_DRegsN], 0, Required>,
1562 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1563 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1564 [1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1565 //
1566 // Integer to Double-precision Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1567 InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1568 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1569 InstrStage<1, [A9_DRegsN], 0, Required>,
1570 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1571 InstrStage<1, [A9_NPipe]>],
Andrew Trickf4ebec02010-10-21 03:40:16 +0000[diff] [blame]1572 [1, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1573 //
1574 // Single-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1575 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1576 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1577 InstrStage<1, [A9_DRegsN], 0, Required>,
1578 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1579 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1580 [2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1581 //
1582 // Double-precision to Integer Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1583 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1584 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1585 InstrStage<1, [A9_DRegsN], 0, Required>,
1586 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1587 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1588 [2, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1589 //
1590 // Integer to Lane Move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1591 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1592 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1593 InstrStage<1, [A9_DRegsN], 0, Required>,
1594 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1595 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1596 [3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1597
1598 //
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1599 // Vector narrow move
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1600 InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1601 InstrStage<1, [A9_MUX0], 0>,
1602 InstrStage<1, [A9_DRegsN], 0, Required>,
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1603 // Extra latency cycles since wbck is 6 cycles
1604 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1605 InstrStage<1, [A9_NPipe]>],
Evan Cheng2a5d7642010-10-01 20:50:58 +0000[diff] [blame]1606 [3, 1]>,
1607 //
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1608 // Double-register FP Unary
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1609 InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1610 InstrStage<1, [A9_MUX0], 0>,
1611 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1612 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1613 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1614 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1615 [5, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1616 //
1617 // Quad-register FP Unary
1618 // Result written in N5, but that is relative to the last cycle of multicycle,
1619 // so we use 6 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1620 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1621 InstrStage<1, [A9_MUX0], 0>,
1622 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1623 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1624 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1625 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1626 [6, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1627 //
1628 // Double-register FP Binary
1629 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1630 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1631 InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1632 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1633 InstrStage<1, [A9_DRegsN], 0, Required>,
1634 // Extra latency cycles since wbck is 6 cycles
1635 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1636 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1637 [5, 2, 2]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1638
1639 //
1640 // VPADD, etc.
1641 InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1642 InstrStage<1, [A9_MUX0], 0>,
1643 InstrStage<1, [A9_DRegsN], 0, Required>,
1644 // Extra latency cycles since wbck is 6 cycles
1645 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1646 InstrStage<1, [A9_NPipe]>],
1647 [5, 1, 1]>,
1648 //
1649 // Double-register FP VMUL
1650 InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1651 InstrStage<1, [A9_MUX0], 0>,
1652 InstrStage<1, [A9_DRegsN], 0, Required>,
1653 // Extra latency cycles since wbck is 6 cycles
1654 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
1655 InstrStage<1, [A9_NPipe]>],
1656 [5, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1657 //
1658 // Quad-register FP Binary
1659 // Result written in N5, but that is relative to the last cycle of multicycle,
1660 // so we use 6 for those cases
1661 // FIXME: We're using this itin for many instructions and [2, 2] here is too
1662 // optimistic.
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1663 InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1664 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1665 InstrStage<1, [A9_DRegsN], 0, Required>,
1666 // Extra latency cycles since wbck is 7 cycles
1667 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1668 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1669 [6, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1670 //
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1671 // Quad-register FP VMUL
1672 InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1673 InstrStage<1, [A9_MUX0], 0>,
1674 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1675 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1676 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1677 InstrStage<1, [A9_NPipe]>],
1678 [6, 2, 1]>,
1679 //
1680 // Double-register FP Multiple-Accumulate
1681 InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1682 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1683 InstrStage<1, [A9_DRegsN], 0, Required>,
1684 // Extra latency cycles since wbck is 7 cycles
1685 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1686 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1687 [6, 3, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1688 //
1689 // Quad-register FP Multiple-Accumulate
1690 // Result written in N9, but that is relative to the last cycle of multicycle,
1691 // so we use 10 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1692 InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1693 InstrStage<1, [A9_MUX0], 0>,
1694 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1695 // Extra latency cycles since wbck is 9 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1696 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1697 InstrStage<4, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1698 [8, 4, 2, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1699 //
1700 // Double-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1701 InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1702 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1703 InstrStage<1, [A9_DRegsN], 0, Required>,
1704 // Extra latency cycles since wbck is 10 cycles
1705 InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
1706 InstrStage<1, [A9_NPipe]>],
1707 [9, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1708 //
1709 // Quad-register Reciprical Step
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1710 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1711 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1712 InstrStage<1, [A9_DRegsN], 0, Required>,
1713 // Extra latency cycles since wbck is 11 cycles
1714 InstrStage<12, [A9_DRegsVFP], 0, Reserved>,
1715 InstrStage<2, [A9_NPipe]>],
1716 [10, 2, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1717 //
1718 // Double-register Permute
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1719 InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1720 InstrStage<1, [A9_MUX0], 0>,
1721 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1722 // Extra latency cycles since wbck is 6 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1723 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1724 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1725 [2, 2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1726 //
1727 // Quad-register Permute
1728 // Result written in N2, but that is relative to the last cycle of multicycle,
1729 // so we use 3 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1730 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1731 InstrStage<1, [A9_MUX0], 0>,
1732 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1733 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1734 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1735 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1736 [3, 3, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1737 //
1738 // Quad-register Permute (3 cycle issue)
1739 // Result written in N2, but that is relative to the last cycle of multicycle,
1740 // so we use 4 for those cases
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1741 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1742 InstrStage<1, [A9_MUX0], 0>,
1743 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1744 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1745 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1746 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1747 [4, 4, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1748
1749 //
1750 // Double-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1751 InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1752 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1753 InstrStage<1, [A9_DRegsN], 0, Required>,
1754 // Extra latency cycles since wbck is 6 cycles
1755 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1756 InstrStage<1, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1757 [2, 1, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1758 //
1759 // Quad-register VEXT
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1760 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1761 InstrStage<1, [A9_MUX0], 0>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1762 InstrStage<1, [A9_DRegsN], 0, Required>,
1763 // Extra latency cycles since wbck is 7 cycles
1764 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1765 InstrStage<2, [A9_NPipe]>],
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1766 [3, 1, 2]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1767 //
1768 // VTB
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1769 InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1770 InstrStage<1, [A9_MUX0], 0>,
1771 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1772 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1773 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1774 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1775 [3, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1776 InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1777 InstrStage<1, [A9_MUX0], 0>,
1778 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1779 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1780 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1781 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1782 [3, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1783 InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1784 InstrStage<1, [A9_MUX0], 0>,
1785 InstrStage<2, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1786 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1787 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1788 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1789 [4, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1790 InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1791 InstrStage<1, [A9_MUX0], 0>,
1792 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1793 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1794 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1795 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1796 [4, 2, 2, 3, 3, 1]>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1797 //
1798 // VTBX
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1799 InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1800 InstrStage<1, [A9_MUX0], 0>,
1801 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1802 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1803 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1804 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1805 [3, 1, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1806 InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1807 InstrStage<1, [A9_MUX0], 0>,
1808 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1809 // Extra latency cycles since wbck is 7 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1810 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1811 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1812 [3, 1, 2, 2, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1813 InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1814 InstrStage<1, [A9_MUX0], 0>,
1815 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1816 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1817 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1818 InstrStage<3, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1819 [4, 1, 2, 2, 3, 1]>,
Evan Chenge790afc2010-10-11 23:41:41 +0000[diff] [blame]1820 InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
1821 InstrStage<1, [A9_MUX0], 0>,
1822 InstrStage<1, [A9_DRegsN], 0, Required>,
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1823 // Extra latency cycles since wbck is 8 cycles
Anton Korobeynikov7d62e332010-04-18 20:31:01 +0000[diff] [blame]1824 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
Evan Chenga3178152010-10-01 22:52:29 +0000[diff] [blame]1825 InstrStage<2, [A9_NPipe]>],
Evan Cheng89e6f672010-10-01 19:41:46 +0000[diff] [blame]1826 [4, 1, 2, 2, 3, 3, 1]>
Anton Korobeynikov090323a2010-04-07 18:22:11 +0000[diff] [blame]1827]>;