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Jia Liue1d61962012-02-19 02:03:36 +00001//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
Nate Begemanf26625e2005-07-12 01:41:54 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Nate Begemanf26625e2005-07-12 01:41:54 +00007//
8//===----------------------------------------------------------------------===//
9//
Evan Cheng0d639a22011-07-01 21:01:15 +000010// This file declares the X86 specific subclass of TargetSubtargetInfo.
Nate Begemanf26625e2005-07-12 01:41:54 +000011//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000014#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
Nate Begemanf26625e2005-07-12 01:41:54 +000016
Eric Christophera08f30b2014-06-09 17:08:19 +000017#include "X86FrameLowering.h"
18#include "X86ISelLowering.h"
19#include "X86InstrInfo.h"
Eric Christophera08f30b2014-06-09 17:08:19 +000020#include "X86SelectionDAGInfo.h"
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000021#include "llvm/ADT/StringRef.h"
Eric Christopherd4298462010-07-05 19:26:33 +000022#include "llvm/ADT/Triple.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000023#include "llvm/CodeGen/GlobalISel/CallLowering.h"
24#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
25#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000027#include "llvm/CodeGen/TargetSubtargetInfo.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000028#include "llvm/IR/CallingConv.h"
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000029#include "llvm/MC/MCInstrItineraries.h"
30#include "llvm/Target/TargetMachine.h"
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000031#include <memory>
Jim Laskey19058c32005-09-01 21:38:21 +000032
Evan Cheng54b68e32011-07-01 20:45:01 +000033#define GET_SUBTARGETINFO_HEADER
Evan Chengc9c090d2011-07-01 22:36:09 +000034#include "X86GenSubtargetInfo.inc"
Evan Cheng54b68e32011-07-01 20:45:01 +000035
Nate Begemanf26625e2005-07-12 01:41:54 +000036namespace llvm {
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000037
Anton Korobeynikov6dbdfe22006-11-30 22:42:55 +000038class GlobalValue;
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +000039
Sanjay Patele63abfe2015-02-03 18:47:32 +000040/// The X86 backend supports a number of different styles of PIC.
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +000041///
Duncan Sands595a4422008-11-28 09:29:37 +000042namespace PICStyles {
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000043
Anton Korobeynikova0554d92007-01-12 19:20:47 +000044enum Style {
Rafael Espindola0d348262016-06-20 23:41:56 +000045 StubPIC, // Used on i386-darwin in pic mode.
46 GOT, // Used on 32 bit elf on when in pic mode.
47 RIPRel, // Used on X86-64 when in pic mode.
48 None // Set when not in pic mode.
Anton Korobeynikova0554d92007-01-12 19:20:47 +000049};
Eugene Zelenkofbd13c52017-02-02 22:55:55 +000050
51} // end namespace PICStyles
Nate Begemanf26625e2005-07-12 01:41:54 +000052
Craig Topperec828472014-03-31 06:53:13 +000053class X86Subtarget final : public X86GenSubtargetInfo {
Mohammed Agabaria115f68e2017-11-20 08:18:12 +000054public:
Andrew Trick8523b162012-02-01 23:20:51 +000055 enum X86ProcFamilyEnum {
Mohammed Agabaria115f68e2017-11-20 08:18:12 +000056 Others,
Mohammed Agabariae9aebf22017-09-13 09:00:27 +000057 IntelAtom,
58 IntelSLM,
59 IntelGLM,
60 IntelHaswell,
61 IntelBroadwell,
62 IntelSkylake,
63 IntelKNL,
64 IntelSKX,
Craig Topper81037f32017-11-19 01:12:00 +000065 IntelCannonlake,
66 IntelIcelake,
Andrew Trick8523b162012-02-01 23:20:51 +000067 };
68
Mohammed Agabaria115f68e2017-11-20 08:18:12 +000069protected:
70 enum X86SSEEnum {
71 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
72 };
73
74 enum X863DNowEnum {
75 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
76 };
77
Sanjay Patele63abfe2015-02-03 18:47:32 +000078 /// X86 processor family: Intel Atom, and others
Andrew Trick8523b162012-02-01 23:20:51 +000079 X86ProcFamilyEnum X86ProcFamily;
Chad Rosier24c19d22012-08-01 18:39:17 +000080
Sanjay Patele63abfe2015-02-03 18:47:32 +000081 /// Which PIC style to use
Duncan Sands595a4422008-11-28 09:29:37 +000082 PICStyles::Style PICStyle;
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +000083
Rafael Espindolaab03eb02016-05-19 22:07:57 +000084 const TargetMachine &TM;
Rafael Espindola46107b92016-05-19 18:49:29 +000085
Eric Christopher11e59832015-10-08 20:10:06 +000086 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Evan Chengcde9e302006-01-27 08:10:46 +000087 X86SSEEnum X86SSELevel;
88
Eric Christopher57a6e132015-11-14 03:04:00 +000089 /// MMX, 3DNow, 3DNow Athlon, or none supported.
Evan Chengff1beda2006-10-06 09:17:41 +000090 X863DNowEnum X863DNowLevel;
91
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +000092 /// True if the processor supports X87 instructions.
93 bool HasX87;
94
Craig Topper505f38a2018-01-10 22:07:16 +000095 /// True if this processor has NOPL instruction
96 /// (generally pentium pro+).
97 bool HasNOPL;
98
Sanjay Patele63abfe2015-02-03 18:47:32 +000099 /// True if this processor has conditional move instructions
Chris Lattnercc8c5812009-09-02 05:53:04 +0000100 /// (generally pentium pro+).
101 bool HasCMov;
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +0000102
Sanjay Patele63abfe2015-02-03 18:47:32 +0000103 /// True if the processor supports X86-64 instructions.
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000104 bool HasX86_64;
Evan Cheng4c91aa32009-01-02 05:35:45 +0000105
Sanjay Patele63abfe2015-02-03 18:47:32 +0000106 /// True if the processor supports POPCNT.
Benjamin Kramer2f489232010-12-04 20:32:23 +0000107 bool HasPOPCNT;
108
Sanjay Patele63abfe2015-02-03 18:47:32 +0000109 /// True if the processor supports SSE4A instructions.
Stefanus Du Toit96180b52009-05-26 21:04:35 +0000110 bool HasSSE4A;
111
Sanjay Patele63abfe2015-02-03 18:47:32 +0000112 /// Target has AES instructions
Eric Christopher2ef63182010-04-02 21:54:27 +0000113 bool HasAES;
Coby Tayree2a1c02f2017-11-21 09:11:41 +0000114 bool HasVAES;
Eric Christopher2ef63182010-04-02 21:54:27 +0000115
Craig Topper09b65982015-10-16 06:03:09 +0000116 /// Target has FXSAVE/FXRESTOR instructions
117 bool HasFXSR;
118
Amjad Aboud1db6d7a2015-10-12 11:47:46 +0000119 /// Target has XSAVE instructions
120 bool HasXSAVE;
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000121
Amjad Aboud1db6d7a2015-10-12 11:47:46 +0000122 /// Target has XSAVEOPT instructions
123 bool HasXSAVEOPT;
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000124
Amjad Aboud1db6d7a2015-10-12 11:47:46 +0000125 /// Target has XSAVEC instructions
126 bool HasXSAVEC;
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000127
Amjad Aboud1db6d7a2015-10-12 11:47:46 +0000128 /// Target has XSAVES instructions
129 bool HasXSAVES;
130
Sanjay Patele63abfe2015-02-03 18:47:32 +0000131 /// Target has carry-less multiplication
Benjamin Kramera0396e42012-05-31 14:34:17 +0000132 bool HasPCLMUL;
Coby Tayree7ca5e5872017-11-21 09:30:33 +0000133 bool HasVPCLMULQDQ;
Bruno Cardoso Lopes09dc24b2010-07-23 01:17:51 +0000134
Coby Tayreed8b17be2017-11-26 09:36:41 +0000135 /// Target has Galois Field Arithmetic instructions
136 bool HasGFNI;
137
Sanjay Patele63abfe2015-02-03 18:47:32 +0000138 /// Target has 3-operand fused multiply-add
Craig Topper79dbb0c2012-06-03 18:58:46 +0000139 bool HasFMA;
David Greene8f6f72c2009-06-26 22:46:54 +0000140
Sanjay Patele63abfe2015-02-03 18:47:32 +0000141 /// Target has 4-operand fused multiply-add
David Greene8f6f72c2009-06-26 22:46:54 +0000142 bool HasFMA4;
143
Sanjay Patele63abfe2015-02-03 18:47:32 +0000144 /// Target has XOP instructions
Jan Sjödin1280eb12011-12-02 15:14:37 +0000145 bool HasXOP;
146
Sanjay Patele63abfe2015-02-03 18:47:32 +0000147 /// Target has TBM instructions.
Yunzhong Gaodd36e932013-09-24 18:21:52 +0000148 bool HasTBM;
149
Simon Pilgrim99b925b2017-05-03 15:51:39 +0000150 /// Target has LWP instructions
151 bool HasLWP;
152
Sanjay Patele63abfe2015-02-03 18:47:32 +0000153 /// True if the processor has the MOVBE instruction.
Craig Topper786bdb92011-10-03 17:28:23 +0000154 bool HasMOVBE;
155
Sanjay Patele63abfe2015-02-03 18:47:32 +0000156 /// True if the processor has the RDRAND instruction.
Craig Topper786bdb92011-10-03 17:28:23 +0000157 bool HasRDRAND;
158
Sanjay Patele63abfe2015-02-03 18:47:32 +0000159 /// Processor has 16-bit floating point conversion instructions.
Craig Topperfe9179f2011-10-09 07:31:39 +0000160 bool HasF16C;
161
Sanjay Patele63abfe2015-02-03 18:47:32 +0000162 /// Processor has FS/GS base insturctions.
Craig Topper228d9132011-10-30 19:57:21 +0000163 bool HasFSGSBase;
164
Sanjay Patele63abfe2015-02-03 18:47:32 +0000165 /// Processor has LZCNT instruction.
Craig Topper271064e2011-10-11 06:44:02 +0000166 bool HasLZCNT;
167
Sanjay Patele63abfe2015-02-03 18:47:32 +0000168 /// Processor has BMI1 instructions.
Craig Topper3657fe42011-10-14 03:21:46 +0000169 bool HasBMI;
170
Sanjay Patele63abfe2015-02-03 18:47:32 +0000171 /// Processor has BMI2 instructions.
Craig Topperaea148c2011-10-16 07:55:05 +0000172 bool HasBMI2;
173
Michael Zuckerman97b6a6922016-01-17 13:42:12 +0000174 /// Processor has VBMI instructions.
175 bool HasVBMI;
176
Coby Tayree71e37cc2017-11-21 09:48:44 +0000177 /// Processor has VBMI2 instructions.
178 bool HasVBMI2;
179
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000180 /// Processor has Integer Fused Multiply Add
181 bool HasIFMA;
182
Sanjay Patele63abfe2015-02-03 18:47:32 +0000183 /// Processor has RTM instructions.
Michael Liao73cffdd2012-11-08 07:28:54 +0000184 bool HasRTM;
185
Sanjay Patele63abfe2015-02-03 18:47:32 +0000186 /// Processor has ADX instructions.
Kay Tiong Khoof809c642013-02-14 19:08:21 +0000187 bool HasADX;
188
Sanjay Patele63abfe2015-02-03 18:47:32 +0000189 /// Processor has SHA instructions.
Ben Langmuir16501752013-09-12 15:51:31 +0000190 bool HasSHA;
191
Sanjay Patele63abfe2015-02-03 18:47:32 +0000192 /// Processor has PRFCHW instructions.
Michael Liao5173ee02013-03-26 17:47:11 +0000193 bool HasPRFCHW;
194
Sanjay Patele63abfe2015-02-03 18:47:32 +0000195 /// Processor has RDSEED instructions.
Michael Liaoa486a112013-03-28 23:41:26 +0000196 bool HasRDSEED;
197
Hans Wennborg5000ce82015-12-04 23:00:33 +0000198 /// Processor has LAHF/SAHF instructions.
199 bool HasLAHFSAHF;
200
Ashutosh Nema348af9c2016-05-18 11:59:12 +0000201 /// Processor has MONITORX/MWAITX instructions.
202 bool HasMWAITX;
203
Craig Topper50f3d142017-02-09 04:27:34 +0000204 /// Processor has Cache Line Zero instruction
205 bool HasCLZERO;
206
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000207 /// Processor has Prefetch with intent to Write instruction
Craig Toppere2685982017-12-22 02:30:30 +0000208 bool HasPREFETCHWT1;
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000209
Sanjay Patele63abfe2015-02-03 18:47:32 +0000210 /// True if SHLD instructions are slow.
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000211 bool IsSHLDSlow;
212
Zvi Rackover8bc7e4d2016-12-06 19:35:20 +0000213 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
214 // PMULUDQ.
215 bool IsPMULLDSlow;
216
Sanjay Patel30145672015-09-01 20:51:51 +0000217 /// True if unaligned memory accesses of 16-bytes are slow.
218 bool IsUAMem16Slow;
Evan Cheng738b0f92010-04-01 05:58:17 +0000219
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000220 /// True if unaligned memory accesses of 32-bytes are slow.
Sanjay Patel501890e2014-11-21 17:40:04 +0000221 bool IsUAMem32Slow;
Michael Liao5bf95782014-12-04 05:20:33 +0000222
Sanjay Patelffd039b2015-02-03 17:13:04 +0000223 /// True if SSE operations can have unaligned memory operands.
224 /// This may require setting a configuration bit in the processor.
225 bool HasSSEUnalignedMem;
David Greene206351a2010-01-11 16:29:42 +0000226
Sanjay Patele63abfe2015-02-03 18:47:32 +0000227 /// True if this processor has the CMPXCHG16B instruction;
Eli Friedman5e570422011-08-26 21:21:21 +0000228 /// this is true for most x86-64 chips, but not the first AMD chips.
229 bool HasCmpxchg16b;
230
Sanjay Patele63abfe2015-02-03 18:47:32 +0000231 /// True if the LEA instruction should be used for adjusting
Evan Cheng1b81fdd2012-02-07 22:50:41 +0000232 /// the stack pointer. This is an optimization for Intel Atom processors.
233 bool UseLeaForSP;
234
Simon Pilgrimfd5df632017-12-19 13:16:43 +0000235 /// True if its preferable to combine to a single shuffle using a variable
236 /// mask over multiple fixed shuffles.
237 bool HasFastVariableShuffle;
238
Yunzhong Gao0de36ec2016-02-12 23:37:57 +0000239 /// True if there is no performance penalty to writing only the lower parts
Amjad Aboud4f977512017-03-03 09:03:24 +0000240 /// of a YMM or ZMM register without clearing the upper part.
241 bool HasFastPartialYMMorZMMWrite;
Yunzhong Gao0de36ec2016-02-12 23:37:57 +0000242
Craig Topperea37e202017-11-25 18:09:37 +0000243 /// True if gather is reasonably fast. This is true for Skylake client and
244 /// all AVX-512 CPUs.
245 bool HasFastGather;
246
Nikolai Bozhenovf6795302016-08-04 12:47:28 +0000247 /// True if hardware SQRTSS instruction is at least as fast (latency) as
248 /// RSQRTSS followed by a Newton-Raphson iteration.
249 bool HasFastScalarFSQRT;
250
251 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
252 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
253 bool HasFastVectorFSQRT;
254
Sanjay Patele63abfe2015-02-03 18:47:32 +0000255 /// True if 8-bit divisions are significantly faster than
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000256 /// 32-bit divisions and should be used when possible.
257 bool HasSlowDivide32;
258
Nikolai Bozhenov6bdf92c2017-01-12 19:34:15 +0000259 /// True if 32-bit divides are significantly faster than
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000260 /// 64-bit divisions and should be used when possible.
261 bool HasSlowDivide64;
Preston Gurdcdf540d2012-09-04 18:22:17 +0000262
Pierre Gousseaub6d652a2016-10-14 16:41:38 +0000263 /// True if LZCNT instruction is fast.
264 bool HasFastLZCNT;
265
Craig Topperd88389a2017-02-21 06:39:13 +0000266 /// True if SHLD based rotate is fast.
267 bool HasFastSHLDRotate;
268
Craig Topper641e2af2017-08-30 04:34:48 +0000269 /// True if the processor supports macrofusion.
270 bool HasMacroFusion;
271
Clement Courbet203fc172017-04-21 09:20:50 +0000272 /// True if the processor has enhanced REP MOVSB/STOSB.
273 bool HasERMSB;
Clement Courbet1ce3b822017-04-21 09:20:39 +0000274
Sanjay Patele63abfe2015-02-03 18:47:32 +0000275 /// True if the short functions should be padded to prevent
Preston Gurda01daac2013-01-08 18:27:24 +0000276 /// a stall when returning too early.
277 bool PadShortFunctions;
278
Craig Topper62c47a22017-08-29 05:14:27 +0000279 /// True if two memory operand instructions should use a temporary register
280 /// instead.
281 bool SlowTwoMemOps;
Sanjay Patele63abfe2015-02-03 18:47:32 +0000282
283 /// True if the LEA instruction inputs have to be ready at address generation
284 /// (AG) time.
Preston Gurd8b7ab4b2013-04-25 20:29:37 +0000285 bool LEAUsesAG;
Preston Gurd663e6f92013-03-27 19:14:02 +0000286
Sanjay Patele63abfe2015-02-03 18:47:32 +0000287 /// True if the LEA instruction with certain arguments is slow
Alexey Volkov6226de62014-05-20 08:55:50 +0000288 bool SlowLEA;
289
Lama Saba2ea271b2017-05-18 08:11:50 +0000290 /// True if the LEA instruction has all three source operands: base, index,
291 /// and offset or if the LEA instruction uses base and index registers where
292 /// the base is EBP, RBP,or R13
293 bool Slow3OpsLEA;
294
Sanjay Patele63abfe2015-02-03 18:47:32 +0000295 /// True if INC and DEC instructions are slow when writing to flags
Alexey Volkov5260dba2014-06-09 11:40:41 +0000296 bool SlowIncDec;
297
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000298 /// Processor has AVX-512 PreFetch Instructions
299 bool HasPFI;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000300
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000301 /// Processor has AVX-512 Exponential and Reciprocal Instructions
302 bool HasERI;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000303
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000304 /// Processor has AVX-512 Conflict Detection Instructions
305 bool HasCDI;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000306
Oren Ben Simhon7bf27f02017-05-25 13:45:23 +0000307 /// Processor has AVX-512 population count Instructions
308 bool HasVPOPCNTDQ;
309
Robert Khasanovbfa01312014-07-21 14:54:21 +0000310 /// Processor has AVX-512 Doubleword and Quadword instructions
311 bool HasDQI;
312
313 /// Processor has AVX-512 Byte and Word instructions
314 bool HasBWI;
315
316 /// Processor has AVX-512 Vector Length eXtenstions
317 bool HasVLX;
318
Asaf Badouh5acf66f2015-12-15 13:35:29 +0000319 /// Processor has PKU extenstions
320 bool HasPKU;
321
Coby Tayree3880f2a2017-11-21 10:04:28 +0000322 /// Processor has AVX-512 Vector Neural Network Instructions
323 bool HasVNNI;
324
Coby Tayree5c7fe5d2017-11-21 10:32:42 +0000325 /// Processor has AVX-512 Bit Algorithms instructions
326 bool HasBITALG;
327
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000328 /// Processor supports MPX - Memory Protection Extensions
Elena Demikhovskyf7e641c2015-06-03 10:30:57 +0000329 bool HasMPX;
330
Oren Ben Simhonfa582b02017-11-26 13:02:45 +0000331 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
332 /// using Shadow Stack
333 bool HasSHSTK;
334
335 /// Processor supports CET IBT - Control-Flow Enforcement Technology
336 /// using Indirect Branch Tracking
337 bool HasIBT;
338
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000339 /// Processor has Software Guard Extensions
340 bool HasSGX;
341
342 /// Processor supports Flush Cache Line instruction
343 bool HasCLFLUSHOPT;
344
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000345 /// Processor supports Cache Line Write Back instruction
346 bool HasCLWB;
347
Craig Topper84b26b92018-01-18 23:52:31 +0000348 /// Processor support RDPID instruction
349 bool HasRDPID;
350
Eric Christopher824f42f2015-05-12 01:26:05 +0000351 /// Use software floating point for code generation.
352 bool UseSoftFloat;
353
Sanjay Patele63abfe2015-02-03 18:47:32 +0000354 /// The minimum alignment known to hold of the stack frame on
Chris Lattner351817b2005-07-12 02:36:10 +0000355 /// entry to the function and which must be maintained by every function.
Nate Begemanf26625e2005-07-12 01:41:54 +0000356 unsigned stackAlignment;
Jeff Cohen33a030e2005-07-27 05:53:44 +0000357
Rafael Espindola063f1772007-10-31 11:52:06 +0000358 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
Evan Cheng763cdfd2007-08-01 23:45:51 +0000359 ///
Rafael Espindola063f1772007-10-31 11:52:06 +0000360 unsigned MaxInlineSizeThreshold;
NAKAMURA Takumi0544fe72011-02-17 12:23:50 +0000361
Sanjay Patele63abfe2015-02-03 18:47:32 +0000362 /// What processor and OS we're targeting.
Eric Christopherd4298462010-07-05 19:26:33 +0000363 Triple TargetTriple;
Chad Rosier24c19d22012-08-01 18:39:17 +0000364
Andrew Trick8523b162012-02-01 23:20:51 +0000365 /// Instruction itineraries for scheduling
366 InstrItineraryData InstrItins;
Evan Cheng03c1e6f2006-02-16 00:21:07 +0000367
Quentin Colombet61d71a12017-08-15 22:31:51 +0000368 /// GlobalISel related APIs.
369 std::unique_ptr<CallLowering> CallLoweringInfo;
370 std::unique_ptr<LegalizerInfo> Legalizer;
371 std::unique_ptr<RegisterBankInfo> RegBankInfo;
372 std::unique_ptr<InstructionSelector> InstSelector;
Eric Christophere950b672014-08-09 04:38:53 +0000373
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000374private:
Sanjay Patele63abfe2015-02-03 18:47:32 +0000375 /// Override the stack alignment.
Bill Wendlingaef9c372013-02-15 22:31:27 +0000376 unsigned StackAlignOverride;
377
Sanjay Patele63abfe2015-02-03 18:47:32 +0000378 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
Evan Cheng13bcc6c2011-07-07 21:06:52 +0000379 bool In64BitMode;
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000380
Sanjay Patele63abfe2015-02-03 18:47:32 +0000381 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
Craig Topper3c80d622014-01-06 04:55:54 +0000382 bool In32BitMode;
383
Sanjay Patele63abfe2015-02-03 18:47:32 +0000384 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
Craig Topper3c80d622014-01-06 04:55:54 +0000385 bool In16BitMode;
386
Mohammed Agabariae9aebf22017-09-13 09:00:27 +0000387 /// Contains the Overhead of gather\scatter instructions
388 int GatherOverhead;
389 int ScatterOverhead;
390
Eric Christophera08f30b2014-06-09 17:08:19 +0000391 X86SelectionDAGInfo TSInfo;
Eric Christopher1a212032014-06-11 00:25:19 +0000392 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
393 // X86TargetLowering needs.
394 X86InstrInfo InstrInfo;
395 X86TargetLowering TLInfo;
396 X86FrameLowering FrameLowering;
Eric Christophera08f30b2014-06-09 17:08:19 +0000397
Nate Begemanf26625e2005-07-12 01:41:54 +0000398public:
Jeff Cohen33a030e2005-07-27 05:53:44 +0000399 /// This constructor initializes the data members to match that
Daniel Dunbar31b44e82009-08-02 22:11:08 +0000400 /// of the specified triple.
Nate Begemanf26625e2005-07-12 01:41:54 +0000401 ///
David Majnemerca290232016-05-20 18:16:06 +0000402 X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
Daniel Sandersa1b2db792017-05-19 11:08:33 +0000403 const X86TargetMachine &TM, unsigned StackAlignOverride);
Eric Christophera08f30b2014-06-09 17:08:19 +0000404
Eric Christopherd9134482014-08-04 21:25:23 +0000405 const X86TargetLowering *getTargetLowering() const override {
406 return &TLInfo;
407 }
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000408
Eric Christopherd9134482014-08-04 21:25:23 +0000409 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000410
Eric Christopherd9134482014-08-04 21:25:23 +0000411 const X86FrameLowering *getFrameLowering() const override {
412 return &FrameLowering;
413 }
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000414
Eric Christopherd9134482014-08-04 21:25:23 +0000415 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
416 return &TSInfo;
417 }
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000418
Eric Christopherd9134482014-08-04 21:25:23 +0000419 const X86RegisterInfo *getRegisterInfo() const override {
420 return &getInstrInfo()->getRegisterInfo();
421 }
Chris Lattner351817b2005-07-12 02:36:10 +0000422
Sanjay Patele63abfe2015-02-03 18:47:32 +0000423 /// Returns the minimum alignment known to hold of the
Chris Lattner351817b2005-07-12 02:36:10 +0000424 /// stack frame on entry to the function and which must be maintained by every
425 /// function for this subtarget.
Nate Begemanf26625e2005-07-12 01:41:54 +0000426 unsigned getStackAlignment() const { return stackAlignment; }
Jeff Cohen33a030e2005-07-27 05:53:44 +0000427
Sanjay Patele63abfe2015-02-03 18:47:32 +0000428 /// Returns the maximum memset / memcpy size
Rafael Espindola063f1772007-10-31 11:52:06 +0000429 /// that still makes it profitable to inline the call.
430 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
Anton Korobeynikov5b96cde2006-11-21 00:01:06 +0000431
432 /// ParseSubtargetFeatures - Parses features string setting specified
Evan Chengff1beda2006-10-06 09:17:41 +0000433 /// subtarget options. Definition of function is auto generated by tblgen.
Evan Cheng1a72add62011-07-07 07:07:08 +0000434 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Evan Chengff1beda2006-10-06 09:17:41 +0000435
Zvi Rackover76dbf262016-11-15 06:34:33 +0000436 /// Methods used by Global ISel
437 const CallLowering *getCallLowering() const override;
438 const InstructionSelector *getInstructionSelector() const override;
439 const LegalizerInfo *getLegalizerInfo() const override;
440 const RegisterBankInfo *getRegBankInfo() const override;
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000441
Bill Wendling61375d82013-02-16 01:36:26 +0000442private:
Sanjay Patele63abfe2015-02-03 18:47:32 +0000443 /// Initialize the full set of dependencies so we can use an initializer
Eric Christopher1a212032014-06-11 00:25:19 +0000444 /// list for X86Subtarget.
445 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
Bill Wendling61375d82013-02-16 01:36:26 +0000446 void initializeEnvironment();
Eric Christopherb68e2532014-09-03 20:36:31 +0000447 void initSubtargetFeatures(StringRef CPU, StringRef FS);
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000448
Bill Wendling61375d82013-02-16 01:36:26 +0000449public:
Eli Bendersky597fc122013-01-25 22:07:43 +0000450 /// Is this x86_64? (disregarding specific ABI / programming model)
451 bool is64Bit() const {
452 return In64BitMode;
453 }
454
Craig Topper3c80d622014-01-06 04:55:54 +0000455 bool is32Bit() const {
456 return In32BitMode;
457 }
458
459 bool is16Bit() const {
460 return In16BitMode;
461 }
462
Eli Bendersky597fc122013-01-25 22:07:43 +0000463 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
464 bool isTarget64BitILP32() const {
Rafael Espindoladdb913c2013-12-19 00:44:37 +0000465 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
Simon Pilgrima2794102014-11-22 19:12:10 +0000466 TargetTriple.isOSNaCl());
Eli Bendersky597fc122013-01-25 22:07:43 +0000467 }
468
469 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
470 bool isTarget64BitLP64() const {
Pavel Chupinf55eb452014-08-07 09:41:19 +0000471 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
Simon Pilgrima2794102014-11-22 19:12:10 +0000472 !TargetTriple.isOSNaCl());
Eli Bendersky597fc122013-01-25 22:07:43 +0000473 }
Evan Cheng54c13da2006-01-26 09:53:06 +0000474
Duncan Sands595a4422008-11-28 09:29:37 +0000475 PICStyles::Style getPICStyle() const { return PICStyle; }
476 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
Anton Korobeynikova0554d92007-01-12 19:20:47 +0000477
Andrey Turetskiy6a3d5612016-03-23 11:13:54 +0000478 bool hasX87() const { return HasX87; }
Craig Topper505f38a2018-01-10 22:07:16 +0000479 bool hasNOPL() const { return HasNOPL; }
Chris Lattnera30d4ce2010-03-14 18:31:44 +0000480 bool hasCMov() const { return HasCMov; }
Craig Toppereb8f9e92012-01-10 06:30:56 +0000481 bool hasSSE1() const { return X86SSELevel >= SSE1; }
482 bool hasSSE2() const { return X86SSELevel >= SSE2; }
483 bool hasSSE3() const { return X86SSELevel >= SSE3; }
484 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
485 bool hasSSE41() const { return X86SSELevel >= SSE41; }
486 bool hasSSE42() const { return X86SSELevel >= SSE42; }
Craig Topperb0c0f722012-01-10 06:54:16 +0000487 bool hasAVX() const { return X86SSELevel >= AVX; }
488 bool hasAVX2() const { return X86SSELevel >= AVX2; }
Craig Topper5c94bb82013-08-21 03:57:57 +0000489 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
Elena Demikhovskyeace43b2012-11-29 12:44:59 +0000490 bool hasFp256() const { return hasAVX(); }
491 bool hasInt256() const { return hasAVX2(); }
Stefanus Du Toit96180b52009-05-26 21:04:35 +0000492 bool hasSSE4A() const { return HasSSE4A; }
Eric Christopher57a6e132015-11-14 03:04:00 +0000493 bool hasMMX() const { return X863DNowLevel >= MMX; }
Evan Chengff1beda2006-10-06 09:17:41 +0000494 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
495 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
Benjamin Kramer2f489232010-12-04 20:32:23 +0000496 bool hasPOPCNT() const { return HasPOPCNT; }
Eric Christopher2ef63182010-04-02 21:54:27 +0000497 bool hasAES() const { return HasAES; }
Coby Tayree2a1c02f2017-11-21 09:11:41 +0000498 bool hasVAES() const { return HasVAES; }
Craig Topper09b65982015-10-16 06:03:09 +0000499 bool hasFXSR() const { return HasFXSR; }
Amjad Aboud1db6d7a2015-10-12 11:47:46 +0000500 bool hasXSAVE() const { return HasXSAVE; }
501 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
502 bool hasXSAVEC() const { return HasXSAVEC; }
503 bool hasXSAVES() const { return HasXSAVES; }
Benjamin Kramera0396e42012-05-31 14:34:17 +0000504 bool hasPCLMUL() const { return HasPCLMUL; }
Coby Tayree7ca5e5872017-11-21 09:30:33 +0000505 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
Coby Tayreed8b17be2017-11-26 09:36:41 +0000506 bool hasGFNI() const { return HasGFNI; }
Simon Pilgrimdb26b3d2015-11-30 22:22:06 +0000507 // Prefer FMA4 to FMA - its better for commutation/memory folding and
508 // has equal or better performance on all supported targets.
Craig Toppere4856312017-11-25 18:32:43 +0000509 bool hasFMA() const { return HasFMA; }
Simon Pilgrimdb26b3d2015-11-30 22:22:06 +0000510 bool hasFMA4() const { return HasFMA4; }
Craig Toppera8d40972017-03-17 07:37:31 +0000511 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
Jan Sjödin1280eb12011-12-02 15:14:37 +0000512 bool hasXOP() const { return HasXOP; }
Yunzhong Gaodd36e932013-09-24 18:21:52 +0000513 bool hasTBM() const { return HasTBM; }
Simon Pilgrim99b925b2017-05-03 15:51:39 +0000514 bool hasLWP() const { return HasLWP; }
Craig Topper786bdb92011-10-03 17:28:23 +0000515 bool hasMOVBE() const { return HasMOVBE; }
516 bool hasRDRAND() const { return HasRDRAND; }
Craig Topperfe9179f2011-10-09 07:31:39 +0000517 bool hasF16C() const { return HasF16C; }
Craig Topper228d9132011-10-30 19:57:21 +0000518 bool hasFSGSBase() const { return HasFSGSBase; }
Craig Topper271064e2011-10-11 06:44:02 +0000519 bool hasLZCNT() const { return HasLZCNT; }
Craig Topper3657fe42011-10-14 03:21:46 +0000520 bool hasBMI() const { return HasBMI; }
Craig Topperaea148c2011-10-16 07:55:05 +0000521 bool hasBMI2() const { return HasBMI2; }
Michael Zuckerman97b6a6922016-01-17 13:42:12 +0000522 bool hasVBMI() const { return HasVBMI; }
Coby Tayree71e37cc2017-11-21 09:48:44 +0000523 bool hasVBMI2() const { return HasVBMI2; }
Elena Demikhovsky29cde352016-01-24 10:41:28 +0000524 bool hasIFMA() const { return HasIFMA; }
Michael Liao73cffdd2012-11-08 07:28:54 +0000525 bool hasRTM() const { return HasRTM; }
Kay Tiong Khoof809c642013-02-14 19:08:21 +0000526 bool hasADX() const { return HasADX; }
Ben Langmuir16501752013-09-12 15:51:31 +0000527 bool hasSHA() const { return HasSHA; }
Craig Toppere2685982017-12-22 02:30:30 +0000528 bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
529 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
530 bool hasSSEPrefetch() const {
531 // We implicitly enable these when we have a write prefix supporting cache
532 // level OR if we have prfchw, but don't already have a read prefetch from
533 // 3dnow.
534 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
535 }
Michael Liaoa486a112013-03-28 23:41:26 +0000536 bool hasRDSEED() const { return HasRDSEED; }
Hans Wennborg5000ce82015-12-04 23:00:33 +0000537 bool hasLAHFSAHF() const { return HasLAHFSAHF; }
Ashutosh Nema348af9c2016-05-18 11:59:12 +0000538 bool hasMWAITX() const { return HasMWAITX; }
Craig Topper50f3d142017-02-09 04:27:34 +0000539 bool hasCLZERO() const { return HasCLZERO; }
Ekaterina Romanovad5fa5542013-11-21 23:21:26 +0000540 bool isSHLDSlow() const { return IsSHLDSlow; }
Zvi Rackover8bc7e4d2016-12-06 19:35:20 +0000541 bool isPMULLDSlow() const { return IsPMULLDSlow; }
Sanjay Patel30145672015-09-01 20:51:51 +0000542 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
Sanjay Patel501890e2014-11-21 17:40:04 +0000543 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
Mohammed Agabariae9aebf22017-09-13 09:00:27 +0000544 int getGatherOverhead() const { return GatherOverhead; }
545 int getScatterOverhead() const { return ScatterOverhead; }
Sanjay Patelffd039b2015-02-03 17:13:04 +0000546 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
Eli Friedman5e570422011-08-26 21:21:21 +0000547 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
Evan Cheng1b81fdd2012-02-07 22:50:41 +0000548 bool useLeaForSP() const { return UseLeaForSP; }
Simon Pilgrimfd5df632017-12-19 13:16:43 +0000549 bool hasFastVariableShuffle() const {
550 return HasFastVariableShuffle;
551 }
Amjad Aboud4f977512017-03-03 09:03:24 +0000552 bool hasFastPartialYMMorZMMWrite() const {
553 return HasFastPartialYMMorZMMWrite;
554 }
Craig Topperea37e202017-11-25 18:09:37 +0000555 bool hasFastGather() const { return HasFastGather; }
Nikolai Bozhenovf6795302016-08-04 12:47:28 +0000556 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
557 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
Pierre Gousseaub6d652a2016-10-14 16:41:38 +0000558 bool hasFastLZCNT() const { return HasFastLZCNT; }
Craig Topperd88389a2017-02-21 06:39:13 +0000559 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
Craig Topper641e2af2017-08-30 04:34:48 +0000560 bool hasMacroFusion() const { return HasMacroFusion; }
Clement Courbet203fc172017-04-21 09:20:50 +0000561 bool hasERMSB() const { return HasERMSB; }
Alexey Volkovfd1731d2014-11-21 11:19:34 +0000562 bool hasSlowDivide32() const { return HasSlowDivide32; }
563 bool hasSlowDivide64() const { return HasSlowDivide64; }
Preston Gurda01daac2013-01-08 18:27:24 +0000564 bool padShortFunctions() const { return PadShortFunctions; }
Craig Topper62c47a22017-08-29 05:14:27 +0000565 bool slowTwoMemOps() const { return SlowTwoMemOps; }
Preston Gurd8b7ab4b2013-04-25 20:29:37 +0000566 bool LEAusesAG() const { return LEAUsesAG; }
Alexey Volkov6226de62014-05-20 08:55:50 +0000567 bool slowLEA() const { return SlowLEA; }
Lama Saba2ea271b2017-05-18 08:11:50 +0000568 bool slow3OpsLEA() const { return Slow3OpsLEA; }
Alexey Volkov5260dba2014-06-09 11:40:41 +0000569 bool slowIncDec() const { return SlowIncDec; }
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000570 bool hasCDI() const { return HasCDI; }
Oren Ben Simhon7bf27f02017-05-25 13:45:23 +0000571 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
Elena Demikhovsky8cfb43f2013-07-24 11:02:47 +0000572 bool hasPFI() const { return HasPFI; }
573 bool hasERI() const { return HasERI; }
Robert Khasanovbfa01312014-07-21 14:54:21 +0000574 bool hasDQI() const { return HasDQI; }
575 bool hasBWI() const { return HasBWI; }
576 bool hasVLX() const { return HasVLX; }
Asaf Badouh5acf66f2015-12-15 13:35:29 +0000577 bool hasPKU() const { return HasPKU; }
Coby Tayree3880f2a2017-11-21 10:04:28 +0000578 bool hasVNNI() const { return HasVNNI; }
Coby Tayree5c7fe5d2017-11-21 10:32:42 +0000579 bool hasBITALG() const { return HasBITALG; }
Elena Demikhovskyf7e641c2015-06-03 10:30:57 +0000580 bool hasMPX() const { return HasMPX; }
Oren Ben Simhonfa582b02017-11-26 13:02:45 +0000581 bool hasSHSTK() const { return HasSHSTK; }
582 bool hasIBT() const { return HasIBT; }
Craig Topper3fd463a2017-02-08 05:45:46 +0000583 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
Craig Topper559f61e2017-08-29 23:13:36 +0000584 bool hasCLWB() const { return HasCLWB; }
Craig Topper84b26b92018-01-18 23:52:31 +0000585 bool hasRDPID() const { return HasRDPID; }
Evan Cheng4c91aa32009-01-02 05:35:45 +0000586
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000587 bool isXRaySupported() const override { return is64Bit(); }
Dean Michael Berris464015442016-09-19 00:54:35 +0000588
Mohammed Agabariae9aebf22017-09-13 09:00:27 +0000589 X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
590
591 /// TODO: to be removed later and replaced with suitable properties
Andrew Trick8523b162012-02-01 23:20:51 +0000592 bool isAtom() const { return X86ProcFamily == IntelAtom; }
Alexey Volkov6226de62014-05-20 08:55:50 +0000593 bool isSLM() const { return X86ProcFamily == IntelSLM; }
Eric Christopher824f42f2015-05-12 01:26:05 +0000594 bool useSoftFloat() const { return UseSoftFloat; }
Andrew Trick8523b162012-02-01 23:20:51 +0000595
Sanjay Patele9bf9932016-02-13 17:26:29 +0000596 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
597 /// no-sse2). There isn't any reason to disable it if the target processor
598 /// supports it.
599 bool hasMFence() const { return hasSSE2() || is64Bit(); }
600
Daniel Dunbar44b53032011-04-19 21:01:47 +0000601 const Triple &getTargetTriple() const { return TargetTriple; }
602
Daniel Dunbar2b9b0e32011-04-19 21:14:45 +0000603 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
Simon Pilgrima2794102014-11-22 19:12:10 +0000604 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
Rafael Espindola44eae722014-12-29 15:47:28 +0000605 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
Simon Pilgrima2794102014-11-22 19:12:10 +0000606 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
Paul Robinson78a69532016-11-30 23:14:27 +0000607 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
Tim Northover9653eb52013-12-10 16:57:43 +0000608
609 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
610 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
Eric Christopher21895152014-12-05 00:22:38 +0000611 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
Tim Northover9653eb52013-12-10 16:57:43 +0000612
Cameron Esfahani943908b2013-08-29 20:23:14 +0000613 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
Marcin Koscielnicki0275fac2016-05-05 11:35:51 +0000614 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
615 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
Evgeniy Stepanov5fe279e2015-10-08 21:21:24 +0000616 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
Cameron Esfahani943908b2013-08-29 20:23:14 +0000617 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
Nick Lewycky73df7e32011-09-05 21:51:43 +0000618 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
619 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
Michael Kupersteine1194bd2015-10-27 07:23:59 +0000620 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
Petr Hoseka7d59162017-02-24 03:10:10 +0000621 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
Yaron Keren28954962014-04-02 04:27:51 +0000622
623 bool isTargetWindowsMSVC() const {
624 return TargetTriple.isWindowsMSVCEnvironment();
625 }
626
Yaron Keren136fe7d2014-04-01 18:15:34 +0000627 bool isTargetKnownWindowsMSVC() const {
NAKAMURA Takumi09717bd2014-03-30 04:35:00 +0000628 return TargetTriple.isKnownWindowsMSVCEnvironment();
Saleem Abdulrasooledbdd2e2014-03-27 22:50:05 +0000629 }
Yaron Keren28954962014-04-02 04:27:51 +0000630
Pat Gavlinb3990952015-08-14 22:41:43 +0000631 bool isTargetWindowsCoreCLR() const {
632 return TargetTriple.isWindowsCoreCLREnvironment();
633 }
634
Yaron Keren28954962014-04-02 04:27:51 +0000635 bool isTargetWindowsCygwin() const {
Saleem Abdulrasooledbdd2e2014-03-27 22:50:05 +0000636 return TargetTriple.isWindowsCygwinEnvironment();
637 }
Yaron Keren28954962014-04-02 04:27:51 +0000638
639 bool isTargetWindowsGNU() const {
640 return TargetTriple.isWindowsGNUEnvironment();
641 }
642
Saleem Abdulrasool2f3b3f32014-11-20 18:01:26 +0000643 bool isTargetWindowsItanium() const {
644 return TargetTriple.isWindowsItaniumEnvironment();
645 }
646
Chandler Carruthebd90c52012-02-05 08:26:40 +0000647 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +0000648
Yaron Keren79bb2662013-10-23 23:37:01 +0000649 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
650
Reid Kleckner9cdd4df2017-10-11 21:24:33 +0000651 bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
Evan Chengd22a4a12011-02-01 01:14:13 +0000652
Reid Kleckner9cdd4df2017-10-11 21:24:33 +0000653 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
Anton Korobeynikova5a64552010-09-02 23:03:46 +0000654
Duncan Sands595a4422008-11-28 09:29:37 +0000655 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
Duncan Sands595a4422008-11-28 09:29:37 +0000656 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
Chris Lattnere2f524f2009-07-10 20:47:30 +0000657
Chris Lattner21c29402009-07-10 21:00:45 +0000658 bool isPICStyleStubPIC() const {
Chris Lattnerba4d7332009-07-10 20:58:47 +0000659 return PICStyle == PICStyles::StubPIC;
660 }
661
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000662 bool isPositionIndependent() const { return TM.isPositionIndependent(); }
Davide Italianoef5d8be2016-06-18 00:03:20 +0000663
Charles Davise8f297c2013-07-12 06:02:35 +0000664 bool isCallingConvWin64(CallingConv::ID CC) const {
Reid Kleckner4f21df22015-07-08 21:03:47 +0000665 switch (CC) {
666 // On Win64, all these conventions just use the default convention.
667 case CallingConv::C:
668 case CallingConv::Fast:
Saleem Abdulrasoolaff96d92017-09-20 21:00:40 +0000669 case CallingConv::Swift:
Reid Kleckner4f21df22015-07-08 21:03:47 +0000670 case CallingConv::X86_FastCall:
671 case CallingConv::X86_StdCall:
672 case CallingConv::X86_ThisCall:
673 case CallingConv::X86_VectorCall:
674 case CallingConv::Intel_OCL_BI:
675 return isTargetWin64();
676 // This convention allows using the Win64 convention on other targets.
Martin Storsjo2f24e932017-07-17 20:05:19 +0000677 case CallingConv::Win64:
Reid Kleckner4f21df22015-07-08 21:03:47 +0000678 return true;
679 // This convention allows using the SysV convention on Windows targets.
680 case CallingConv::X86_64_SysV:
681 return false;
682 // Otherwise, who knows what this is.
683 default:
684 return false;
685 }
Charles Davise8f297c2013-07-12 06:02:35 +0000686 }
Mikhail Glushenkovabd56bd2010-02-28 22:54:30 +0000687
Rafael Espindolacb2d2662016-05-19 18:34:20 +0000688 /// Classify a global variable reference for the current subtarget according
689 /// to how we should reference it in a non-pcrel context.
Rafael Espindolac7e98132016-05-20 12:20:10 +0000690 unsigned char classifyLocalReference(const GlobalValue *GV) const;
691
692 unsigned char classifyGlobalReference(const GlobalValue *GV,
693 const Module &M) const;
Rafael Espindolaab03eb02016-05-19 22:07:57 +0000694 unsigned char classifyGlobalReference(const GlobalValue *GV) const;
Anton Korobeynikov93acb492006-12-20 01:03:20 +0000695
Rafael Espindolacb2d2662016-05-19 18:34:20 +0000696 /// Classify a global function reference for the current subtarget.
Rafael Espindolac7e98132016-05-20 12:20:10 +0000697 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
698 const Module &M) const;
Rafael Espindola46107b92016-05-19 18:49:29 +0000699 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
Asaf Badouh89406d12016-04-20 08:32:57 +0000700
Sanjay Patele63abfe2015-02-03 18:47:32 +0000701 /// Classify a blockaddress reference for the current subtarget according to
702 /// how we should reference it in a non-pcrel context.
Rafael Espindolacb2d2662016-05-19 18:34:20 +0000703 unsigned char classifyBlockAddressReference() const;
Dan Gohman7a6611792009-11-20 23:18:13 +0000704
Sanjay Patele63abfe2015-02-03 18:47:32 +0000705 /// Return true if the subtarget allows calls to immediate address.
Rafael Espindola46107b92016-05-19 18:49:29 +0000706 bool isLegalToCallImmediateAddr() const;
Evan Cheng96098332009-05-20 04:53:57 +0000707
Andrew Tricke97d8d62013-10-15 23:33:07 +0000708 /// Enable the MachineScheduler pass for all X86 subtargets.
Craig Topper73156022014-03-02 09:09:27 +0000709 bool enableMachineScheduler() const override { return true; }
Andrew Tricke97d8d62013-10-15 23:33:07 +0000710
Andrew V. Tischenko75745d02017-04-14 07:44:23 +0000711 // TODO: Update the regression tests and return true.
712 bool supportPrintSchedInfo() const override { return false; }
713
Eric Christopher6b0fcfe2014-05-21 23:40:26 +0000714 bool enableEarlyIfConversion() const override;
715
Sanjay Patele63abfe2015-02-03 18:47:32 +0000716 /// Return the instruction itineraries based on the subtarget selection.
Eric Christopherd9134482014-08-04 21:25:23 +0000717 const InstrItineraryData *getInstrItineraryData() const override {
718 return &InstrItins;
719 }
Sanjay Patela2f658d2014-07-15 22:39:58 +0000720
721 AntiDepBreakMode getAntiDepBreakMode() const override {
722 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
723 }
Marina Yatsinaf9371d82017-10-22 17:59:38 +0000724
Benjamin Kramera7c822a2017-10-22 19:16:31 +0000725 bool enableAdvancedRASplitCost() const override { return true; }
Evan Cheng47455a72009-09-03 04:37:05 +0000726};
Evan Chenga8b4aea2006-10-16 21:00:37 +0000727
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000728} // end namespace llvm
Nate Begemanf26625e2005-07-12 01:41:54 +0000729
Eugene Zelenkofbd13c52017-02-02 22:55:55 +0000730#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H